JPH02501253A - Induced metallization treatment with dissociated aluminum nitride ceramic - Google Patents
Induced metallization treatment with dissociated aluminum nitride ceramicInfo
- Publication number
- JPH02501253A JPH02501253A JP63507973A JP50797388A JPH02501253A JP H02501253 A JPH02501253 A JP H02501253A JP 63507973 A JP63507973 A JP 63507973A JP 50797388 A JP50797388 A JP 50797388A JP H02501253 A JPH02501253 A JP H02501253A
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- laser energy
- metal
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- 239000000919 ceramic Substances 0.000 title claims description 37
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 title claims description 12
- 238000001465 metallisation Methods 0.000 title description 13
- 239000000758 substrate Substances 0.000 claims description 56
- 238000000034 method Methods 0.000 claims description 53
- 239000004020 conductor Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 239000010409 thin film Substances 0.000 claims description 17
- 239000010408 film Substances 0.000 claims description 9
- 238000010494 dissociation reaction Methods 0.000 claims description 8
- 230000005593 dissociations Effects 0.000 claims description 8
- 239000000470 constituent Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims 4
- 229910002092 carbon dioxide Inorganic materials 0.000 claims 2
- 239000001569 carbon dioxide Substances 0.000 claims 2
- 238000002224 dissection Methods 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 229920000642 polymer Polymers 0.000 claims 1
- 239000010410 layer Substances 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 230000008901 benefit Effects 0.000 description 8
- 238000009966 trimming Methods 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 210000003746 feather Anatomy 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229920002994 synthetic fiber Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
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- C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
- C04B41/0072—Heat treatment
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
- C04B41/009—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone characterised by the material treated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/28—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/105—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by conversion of non-conductive material on or in the support into conductive material, e.g. by using an energy beam
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1136—Conversion of insulating material into conductive material, e.g. by pyrolysis
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0029—Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
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- Manufacturing & Machinery (AREA)
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- Materials Engineering (AREA)
- Organic Chemistry (AREA)
- General Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Thermal Sciences (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Laser Beam Processing (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 解離された窒化アルミニウムセラミックによる誘起金属化処理 [発明の背景] この発明は、非導電性基体上の導電性回路の形成に関するものであり、特に導電 性回路をその上に形成するために窒化アルミニウムセラミック基体または絶縁層 の局部的部分を選択的に解離するための技術に関するものである。[Detailed description of the invention] Induced metallization treatment with dissociated aluminum nitride ceramic [Background of the invention] This invention relates to the formation of electrically conductive circuits on non-conductive substrates, and in particular to the formation of electrically conductive circuits on non-conductive substrates. an aluminum nitride ceramic substrate or insulating layer to form a circuit on it The present invention relates to a technique for selectively dissociating local portions of.
ハイブリッドマイクロ回路としても知られているハイブリッド回路構造は個々の 分離した回路装置の相互接続およびパッケージを備え、回路素子を支持するため に1以上の非導電性セラミック基体または層を備え、それはマイクロ回路の両側 に設けられることができる。回路素子の接続のために走る導体は基体またはその 次の層の表面に形成され、金属化された貫通通路がセラミック基体の両側上の回 路の相互接続または居間を接続するために設けられてもよい。Hybrid circuit structures, also known as hybrid microcircuits, are For providing interconnection and packaging of separate circuit devices and supporting circuit elements has one or more non-conductive ceramic substrates or layers on both sides of the microcircuit. can be provided. Conductors that run to connect circuit elements are connected to the substrate or its Formed in the surface of the next layer, metallized through passages are formed on both sides of the ceramic substrate. It may be provided for the interconnection of roads or living rooms.
接続のために走る導体は、例えば厚膜スクリーン印刷または薄膜金属化技術によ って形成されることができ、貫通通路金属化は厚膜スクリーン印刷によって形成 されることができる。しかしながら、よく知られているようにこのような技術は 時間がかかり、多くの工程を必要とする。例えば厚膜スクリーン印刷法はシリク スクリーンの処理および使用ならびに導電性ペーストの適用が必要であり、一方 薄膜金属化技術は蒸気付着、マスクおよびエツチングが必要である。The conductors that run for the connection may be made by thick film screen printing or thin film metallization techniques, for example. The through-pass metallization can be formed by thick film screen printing. can be done. However, as is well known, such technology It is time consuming and requires many steps. For example, the thick film screen printing method is Treatment and use of screens and application of conductive paste are required, while Thin film metallization techniques require vapor deposition, masks and etching.
さらに、よく知られている技術により形成された導電路について考えなければな らないことは、抵抗値を減少させるための抵抗体のトリミングができないことで ある。一般的に現在の技術による抵抗体のトリミングは抵抗値を増加させること しかできない。Additionally, one must consider conductive paths formed by well-known techniques. The reason for this is that the resistor cannot be trimmed to reduce the resistance value. be. Trimming the resistor with current technology generally increases the resistance value. I can only do it.
[発明の概要] それ放卵導電性セラミックまたは絶縁層上に導電性回路を形成する簡単な方法を 提供することは有効である。[Summary of the invention] It is an easy way to form conductive circuits on conductive ceramic or insulating layers. It is effective to provide
厚膜および薄膜金属化処理を避けて非導電性セラミック基体または絶縁層上に導 電性回路を形成する方法を提供することは別の利益を与える。Conductive on non-conductive ceramic substrates or insulating layers avoiding thick and thin film metallization processes Providing a method for forming electrical circuits provides other benefits.
導電材料をそれに適用することを避けて非導電性セラミック基体または絶縁層上 に導電性回路を形成する方法を提供することも有効である。on a non-conductive ceramic substrate or insulating layer avoiding applying conductive materials to it It would also be advantageous to provide a method for forming a conductive circuit.
抵抗値を減少させる抵抗体のトリミングを可能にして非導電性セラミック基体ま たは絶縁層上に導電性回路を形成する方法を提供することはさらに別の利点を与 える。Non-conductive ceramic substrates allow trimming of the resistor to reduce resistance. Providing a method for forming conductive circuits on or insulating layers provides yet another advantage. I can do it.
絶縁層または金属非導電性基体を通る貫通通路を金属化する方法を提供すること はさらに別の利点を与える。Provided is a method for metallizing a through passageway through an insulating layer or a metallic non-conductive substrate. gives yet another advantage.
以上およびその他の効果および特徴は、金属成分を有し、レーザエネルギの供給 によってセラミック基体に接着される解離された金属を与える構成成分に解離さ れることのできる非導電性セラミック基体を与える工程を含む金属非導電性基体 または絶縁層上に導電性回路を形成する方法によって与えられる。非導電性セラ ミック基体の表面の予め定められた区域に与えられたレーザエネルギはその予定 された区域に解離した導体を与える。These and other effects and features have a metallic component and the delivery of laser energy. Dissociated into constituents giving dissociated metal adhered to ceramic substrate by A metal non-conductive substrate comprising a process to provide a non-conductive ceramic substrate capable of being Or by a method of forming a conductive circuit on an insulating layer. non-conductive ceramic Laser energy applied to a predetermined area on the surface of a microsubstrate Apply a dissociated conductor to the area where the
この発明の別の観点によれば、非導電性セラミック基体にレーザエネルギを与え ることによって金属化したスルーホールが形成され、解離した金属がスルーホー ルの内面上に形成される。According to another aspect of the invention, laser energy is applied to a non-conductive ceramic substrate. A metalized through hole is formed by this process, and the dissociated metal formed on the inner surface of the tube.
この発明のさらに別の別の観点によれば、2個の金属化した区域の間に導電的に 結合された厚膜または薄膜抵抗をトリミングして抵抗値を低下させることが可能 になる。レーザエネルギは厚膜または薄膜抵抗の一部分および予め定められたパ ターンで金属非導電性セラミック基体の一部分に供給されて連続的に解離された 金属導体を提供し、この金属導体は厚膜または薄膜抵抗を通過し、2個の導電性 金属化区域の一つに導電的に接続される。According to yet another aspect of the invention, a conductive conductor between the two metallized areas is provided. Bonded thick-film or thin-film resistors can be trimmed to reduce resistance become. Laser energy is applied to a portion of a thick or thin film resistor and a predetermined pattern. The metal was supplied to a portion of the non-conductive ceramic substrate by turning and was continuously dissociated. Provide a metal conductor that passes through a thick or thin film resistor and connects two conductive conductively connected to one of the metallized areas.
[図面の簡単な説明] 開示された発明の利点および特徴は添附図面を参考にした以下の詳細な説明から 当業者には容易に認識されるであろう。[Brief explanation of the drawing] Advantages and features of the disclosed invention will emerge from the following detailed description with reference to the accompanying drawings. It will be readily recognized by those skilled in the art.
第1図は、この発明の方法を適用する導電性構造の概略図である。FIG. 1 is a schematic illustration of a conductive structure to which the method of the invention is applied.
第2図は、抵抗値を減少させるように抵抗をトリミングするこの発明の方法を適 用する導電性構造の概略図である。FIG. 2 shows the application of the method of the present invention for trimming a resistor to reduce its resistance value. 1 is a schematic diagram of a conductive structure used.
第3図は、この発明の方法を適用する金属被覆スルーホールの概略図である。FIG. 3 is a schematic diagram of a metallized through hole to which the method of the invention is applied.
[詳細な説明] 以下の詳細な説明および各図面において同様の素子には同じ参照記号が付されて いる。[Detailed explanation] Like elements in the following detailed description and in the drawings are provided with the same reference symbols. There is.
第1図を参照すると、ハイブリッド回路の、例えば窒化アルミニウムセラミック 基体のような非導電性セラミック基体または絶縁層11の平面図が示されている 。基体11上には回路装置13が取付けられ、さらにその周縁に分布して接続パ ッド15、17.19.21を備えている。接続パッド15.17.19.21 は導体配線23と同様に既知の厚膜または薄膜金属化技術によって金属化されて いる。周知の技術によってワイヤボンド25が回路装置13の端子と接続パッド 15.17.19.21および導体配線23との間の接続に使用されている。Referring to FIG. 1, a hybrid circuit, such as an aluminum nitride ceramic A plan view of a non-conductive ceramic substrate such as a substrate or an insulating layer 11 is shown. . A circuit device 13 is mounted on the base body 11, and connection pads are further distributed around the periphery of the circuit device 13. It is equipped with heads 15, 17, 19, and 21. Connection pad 15.17.19.21 are metallized by known thick film or thin film metallization techniques like the conductor wiring 23. There is. Wire bonds 25 are connected to terminals and connection pads of circuit device 13 by well-known techniques. 15, 17, 19, 21 and the conductor wiring 23.
第1図の窒化アルミニウムセラミック基体11はさらに接続パッド27.29お よび導体配線31.33を有している。これらの接続パッドおよび導体配線27 .29.31.33は窒化アルミニウムセラミック基体11に接着された解離さ れたアルミニウムで構成される。このような解離されたアルミニウムの接続パッ ドおよび導体配線はセラミック基体11の領域にレーザエネルギを供給すること によって形成され、そこにそのような接続パッドおよび導体配線27.29.3 1.33が形成される。例として、レーザエネルギはイツトリウム・アルミニウ ム・ガーネット(YAG)レーザまたは2酸化炭素(CO2)レーザによって供 給されることができる。レーザビームは制御されて基体からアルミニウムが解離 されるべき区域を走査し、それによって金属化された接続パッドおよび導体配線 27.29.31゜33が形成される。幅0.001インチ程度の非常に微細な 配線が得られる。これは通常の処理技術によって形成されるマイクロ回路よりも 大きな回路密度を有するマイクロ回路の形成を可能にする。The aluminum nitride ceramic substrate 11 of FIG. and conductor wiring 31 and 33. These connection pads and conductor traces 27 .. 29.31.33 is a dissociated material bonded to an aluminum nitride ceramic substrate 11. Constructed from polished aluminum. Such dissociated aluminum connection pads The conductive wires and conductive traces are capable of supplying laser energy to areas of the ceramic substrate 11. 27.29.3 formed by and therein such connection pads and conductor traces 27.29.3 1.33 is formed. As an example, laser energy can be Provided by a YAG laser or a CO2 laser. can be paid. The laser beam is controlled to dissociate aluminum from the substrate scan the area to be processed, thereby metallizing connection pads and conductor traces 27.29.31°33 is formed. Very fine particles with a width of about 0.001 inch Wiring is obtained. This is more than microcircuits formed by normal processing techniques. Allows the formation of microcircuits with large circuit densities.
特定の例について説明すると、YAGレーザは次のパラメータで接続パッドおよ び導体配線27.29.31.33を形成するために使用することができる。To discuss a specific example, a YAG laser has the following parameters for connecting pads and It can be used to form conductor lines 27, 29, 31, 33.
装置 ESI44型YAGレーザ 電力設定 14.5アンペア パルス率 2000パルス/秒 速度 4mm/秒 開示された解離処理の特にすぐれている点は、他の金属化部分が例えば厚膜また は薄膜技術によってすでに形成された後に特定の位置を金属化することができる ことである。したがって、ここに示された解離処理はすでに製造された回路また は原型回路に接続パッドおよび導体配線を追加するのに使用することができる利 点がある。Equipment: ESI44 type YAG laser Power setting: 14.5 amps Pulse rate: 2000 pulses/second Speed 4mm/sec A particular advantage of the disclosed dissociation process is that other metallizations, such as thick films or can be metallized at specific locations after they have already been formed by thin film technology That's true. Therefore, the dissociation process shown here can be applied to already fabricated circuits or is an advantage that can be used to add connection pads and conductor traces to the prototype circuit. There is a point.
特定の位置を金属化することができることを利用した応用の例が第2図に示され ている。第2図には薄膜抵抗113がその上に形成された例えば窒化アルミニウ ムセラミック基体111が示されている。薄膜抵抗113は2個の導体パッド1 15゜117間に結合された状態で示されている。U形の解離アルミニウム導体 119が導体パッド115から伸び出て導体パッド115から離れた位置で薄膜 抵抗113を横断している。この解離アルミニウム導体119によって、薄膜抵 抗113の抵抗値はもとの抵抗値に比較して減少される。何故ならば解離アルミ ニウム導体119と導体パッド115との間の抵抗材料は実効的に短絡されるか らである。したがって解離処理は抵抗値を減少させるための抵抗のトリミングに 使用されることができる。An example of an application that takes advantage of the ability to metallize specific locations is shown in Figure 2. ing. In FIG. A ceramic substrate 111 is shown. The thin film resistor 113 has two conductor pads 1 It is shown coupled between 15° and 117°. U-shaped dissociated aluminum conductor 119 extends from the conductor pad 115 and forms a thin film at a position away from the conductor pad 115. It crosses resistance 113. This dissociated aluminum conductor 119 provides a thin film resistor. The resistance value of resistor 113 is reduced compared to the original resistance value. Because dissociated aluminum Is the resistive material between conductor 119 and conductor pad 115 effectively shorted? It is et al. Therefore, the dissociation process is used to trim the resistance to reduce the resistance value. can be used.
従来ハイブリッドマイクロ回路中に形成された厚膜または薄膜抵抗の抵抗値を減 少させる処理は通常の抵抗トリミング技術によっては不可能であった。Reduce the resistance of thick-film or thin-film resistors traditionally formed in hybrid microcircuits. This reduction was not possible using conventional resistor trimming techniques.
抵抗はまたレーザを使用してそれらの値を増加するようなトリミングもできるこ とを理解すべきである。これは一般にU形(Uの脚は抵抗の縁にある)に抵抗の 一部をレーザを使用して切断することによって行われる。このような切断は抵抗 材料の量を実効的に減少させる。Resistors can also be trimmed using a laser to increase their value. should be understood. This is generally a U-shape (the legs of the U are on the edge of the resistor) of the resistor. This is done by cutting a portion using a laser. Such cutting is resisted Effectively reduces the amount of material.
第3図を参照すると、この発明の金属解離処理のさらに別の利用が示されている 。スルーホール213が例えばレーザによって窒化アルミニウムセラミック基体 211中に形成される。Referring to FIG. 3, yet another use of the metal dissociation process of the present invention is shown. . Through-holes 213 are cut into an aluminum nitride ceramic substrate by, for example, a laser. Formed during 211.
レーザエネルギにより解離されたアルミニウムがスルーホール213の内面およ びその開口の周囲に形成される。したがって導電性のスルーホールが従来知られ ている方法のようにセラミック基体211中に最初に孔を形成してからその孔を 金属化することなく形成される。この方法により形成されたスルーホールは窒化 アルミニウムセラミック基体または絶縁層の両側の回路を接続するのに使用され ることができる。Aluminum dissociated by the laser energy forms on the inner surface of the through hole 213 and and around its opening. Therefore, conductive through holes were conventionally known. As in the method described above, holes are first formed in the ceramic substrate 211 and then Formed without metallization. Through holes formed by this method are nitrided. Used to connect circuits on both sides of aluminum ceramic substrate or insulation layer can be done.
以上、従来の厚膜または薄膜金属化技術を使用せずに、迅速に、容易に解離され た金属導体を形成することができることを含めて多くの利点および特徴を有する 金属解離処理法が説明された。さらに、示された金属解離処理法は抵抗値を減少 させるような抵抗のトリミング法を与える。また解離処理法はレーザによって孔 を形成することによって簡単に金属化したスルーホールを生成するのに利用され ることができる。are quickly and easily dissociated without using traditional thick or thin film metallization techniques. has many advantages and characteristics, including the ability to form metallic conductors The metal dissociation treatment method was explained. Furthermore, the presented metal dissociation treatment method reduces the resistance value. A method for trimming the resistor is given. In addition, the dissociation treatment method uses a laser to create holes. It is used to easily produce metallized through holes by forming can be done.
この方法は、金属化層を相互接続する表面層を処理し、直接導体ラインを描き、 金属化された貫通通路を形成するためにレーザのプログラムによりスルーホール を介して金属化することを可能にする。この方法は他の金属化技術が接続パッド または抵抗その他を形成するのに使用される前、または後に行われることができ る。この発明の処理方法を使用することによって、著しい処理速度の増加が得ら れ、面倒でコストのかかるスクリーン印刷および付着、エツチングおよびマスク 処理が必要なくなる。またこの発明を使用して抵抗値を減少させる抵抗トリミン グを行うことが可能である。This method treats the surface layer interconnecting metallization layers, directly drawing conductor lines, Through-holes by laser programming to form metalized through-paths allows for metallization through. This method is similar to other metallization techniques when connecting pads. or can be done before or after being used to form resistors etc. Ru. By using the processing method of this invention, a significant increase in processing speed can be obtained. cumbersome and costly screen printing and deposition, etching and masking Processing is no longer necessary. This invention can also be used to trim resistance to reduce resistance. It is possible to perform
以上この発明の特定の実施例について説明し、図示したが、当業者には以下の請 求の範囲に記載されたこの発明の技術的範囲を逸脱することなくそれに対する各 種の変形変更が可能であることは明白であろう。特にこの発明の実施例として窒 化アルミニウムが示されているが、この発明は窒化アルミニウムの基体または絶 縁層に限定されるものではなく、ここで説明したように解離するその他の非導電 性材料も含まれるものである。Having described and illustrated specific embodiments of the invention, those skilled in the art will appreciate the following: The scope of the present invention described in the scope of the request shall be It will be clear that variations in species are possible. In particular, as an embodiment of this invention, Although aluminum nitride is shown, the present invention does not require an aluminum nitride substrate or an aluminum nitride substrate. Other non-conducting materials that are not limited to the marginal layer and dissociate as described here This also includes synthetic materials.
国際調査報告 m*S、I呻−^−IllIImIIII−PCT/υS羽102E−i+SA 24407international search report m*S, I groan-^-IllIImIII-PCT/υS feather 102E-i+SA 24407
Claims (13)
Applications Claiming Priority (2)
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US9608387A | 1987-09-14 | 1987-09-14 | |
US096,083 | 1987-09-14 |
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JPH02501253A true JPH02501253A (en) | 1990-04-26 |
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JP63507973A Pending JPH02501253A (en) | 1987-09-14 | 1988-07-29 | Induced metallization treatment with dissociated aluminum nitride ceramic |
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JP (1) | JPH02501253A (en) |
KR (1) | KR890702417A (en) |
IL (1) | IL87417A0 (en) |
WO (1) | WO1989002697A1 (en) |
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US9148956B2 (en) | 2012-04-27 | 2015-09-29 | Seiko Epson Corporation | Base substrate, electronic device, and method of manufacturing base substrate |
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DE3942472A1 (en) * | 1989-12-22 | 1991-06-27 | Asea Brown Boveri | COATING PROCESS |
DE4342258A1 (en) * | 1993-12-10 | 1995-06-14 | Resma Gmbh | Conductive region prodn. on or in ceramic |
DE4401612A1 (en) * | 1994-01-20 | 1995-07-27 | Resma Gmbh | Conductive region prodn. in or on ceramic workpiece |
US8003513B2 (en) | 2002-09-27 | 2011-08-23 | Medtronic Minimed, Inc. | Multilayer circuit devices and manufacturing methods using electroplated sacrificial structures |
US20040061232A1 (en) | 2002-09-27 | 2004-04-01 | Medtronic Minimed, Inc. | Multilayer substrate |
US7138330B2 (en) | 2002-09-27 | 2006-11-21 | Medtronic Minimed, Inc. | High reliability multilayer circuit substrates and methods for their formation |
DE102006017630A1 (en) * | 2006-04-12 | 2007-10-18 | Lpkf Laser & Electronics Ag | Method for producing a printed conductor structure and a printed conductor structure produced in this way |
EP1845170A3 (en) * | 2006-04-12 | 2007-11-21 | LPKF Laser & Electronics AG | Method for manufacturing a conductor path structure and such a conductor path structure |
DE102016200062B4 (en) * | 2016-01-06 | 2023-08-10 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Process for the formation of electrically conductive vias in ceramic circuit carriers |
CN112420300A (en) * | 2020-11-11 | 2021-02-26 | 昆山丰景拓电子有限公司 | Novel resistor and manufacturing method thereof |
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US3256109A (en) * | 1962-12-20 | 1966-06-14 | Berger Carl | Metal formation within a substrate |
GB1251451A (en) * | 1969-03-19 | 1971-10-27 | ||
DE3103986A1 (en) * | 1981-02-05 | 1982-09-09 | Reiner Dipl.-Phys. 8011 Vaterstetten Szepan | Method for producing drilled holes for through-plated contact making in electronic printed-circuit boards |
JPS62136897A (en) * | 1985-12-11 | 1987-06-19 | 株式会社東芝 | Manufacture of ceramic circuit substrate |
US4691091A (en) * | 1985-12-31 | 1987-09-01 | At&T Technologies | Direct writing of conductive patterns |
-
1988
- 1988-07-29 JP JP63507973A patent/JPH02501253A/en active Pending
- 1988-07-29 KR KR1019890700839A patent/KR890702417A/en not_active Application Discontinuation
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US9148956B2 (en) | 2012-04-27 | 2015-09-29 | Seiko Epson Corporation | Base substrate, electronic device, and method of manufacturing base substrate |
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