JPH0247038U - - Google Patents
Info
- Publication number
- JPH0247038U JPH0247038U JP12644488U JP12644488U JPH0247038U JP H0247038 U JPH0247038 U JP H0247038U JP 12644488 U JP12644488 U JP 12644488U JP 12644488 U JP12644488 U JP 12644488U JP H0247038 U JPH0247038 U JP H0247038U
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- integrated circuit
- semiconductor integrated
- semiconductor chip
- tab pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
第１図および第２図はそれぞれ本孝案の一実施
例を示す組立プロセス図およびその完成品の断面
図である、第３図ａ，ｂおよびｃは本考案のパツ
ド・レイアウトの縮小効果を説明する図、第４図
は従来のプラスチツク封止半導体集積回路装置の
断面図である。
１……リード・フレーム、２……テープ状の絶
縁フイルム、３……ＩＣチツプ、４……プラスチ
ツク封入樹脂、８……外部リード、９……内部活
性領域、１０……ボンデイング・パツド、１１…
…ＴＡＢパツド。
Figures 1 and 2 are an assembly process diagram and a sectional view of the completed product, respectively, showing an embodiment of the present invention. Figures 3a, b, and c show the reduction effect of the pad layout of the present invention. The explanatory diagram, FIG. 4, is a sectional view of a conventional plastic-sealed semiconductor integrated circuit device. DESCRIPTION OF SYMBOLS 1... Lead frame, 2... Tape-shaped insulating film, 3... IC chip, 4... Plastic encapsulation resin, 8... External lead, 9... Internal active region, 10... Bonding pad, 11 …
...TAB pad.
Claims (1)
れぞれを配線パターンを介し前記絶縁フイルム上
のＴＡＢパツドに引出される半導体チツプと、前
記ＴＡＢパツドと電気接続される外部への引出リ
ードと、前記半導体チツプを絶縁フイルムと共に
被覆するプラスチツク封入樹脂とを含むことを特
徴とする半導体集積回路装置。 A semiconductor chip mounted on a tape-shaped insulating film and having each of its electrodes drawn out to a TAB pad on the insulating film through a wiring pattern, an external lead electrically connected to the TAB pad, and the semiconductor chip 1. A semiconductor integrated circuit device comprising: a plastic encapsulation resin covering the semiconductor integrated circuit along with an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12644488U JPH0247038U (en) | 1988-09-27 | 1988-09-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12644488U JPH0247038U (en) | 1988-09-27 | 1988-09-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0247038U true JPH0247038U (en) | 1990-03-30 |
Family
ID=31377975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12644488U Pending JPH0247038U (en) | 1988-09-27 | 1988-09-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0247038U (en) |
-
1988
- 1988-09-27 JP JP12644488U patent/JPH0247038U/ja active Pending