JPH0241058B2 - - Google Patents
Info
- Publication number
- JPH0241058B2 JPH0241058B2 JP57089844A JP8984482A JPH0241058B2 JP H0241058 B2 JPH0241058 B2 JP H0241058B2 JP 57089844 A JP57089844 A JP 57089844A JP 8984482 A JP8984482 A JP 8984482A JP H0241058 B2 JPH0241058 B2 JP H0241058B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- write
- data
- read
- partial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012937 correction Methods 0.000 claims description 22
- 230000006870 function Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 238000012546 transfer Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57089844A JPS58208996A (ja) | 1982-05-28 | 1982-05-28 | 誤り訂正を行なう記憶装置の部分書込みを含む連続アドレスへの連続動作方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57089844A JPS58208996A (ja) | 1982-05-28 | 1982-05-28 | 誤り訂正を行なう記憶装置の部分書込みを含む連続アドレスへの連続動作方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58208996A JPS58208996A (ja) | 1983-12-05 |
| JPH0241058B2 true JPH0241058B2 (US20090163788A1-20090625-C00002.png) | 1990-09-14 |
Family
ID=13982069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57089844A Granted JPS58208996A (ja) | 1982-05-28 | 1982-05-28 | 誤り訂正を行なう記憶装置の部分書込みを含む連続アドレスへの連続動作方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58208996A (US20090163788A1-20090625-C00002.png) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62278651A (ja) * | 1986-05-28 | 1987-12-03 | Hitachi Ltd | 部分書込制御装置 |
-
1982
- 1982-05-28 JP JP57089844A patent/JPS58208996A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58208996A (ja) | 1983-12-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0549139B1 (en) | Programmable memory timing | |
| US20040172581A1 (en) | External storage device and memory access control method thereof | |
| JPS5847741B2 (ja) | パタ−ン発生器 | |
| JPH1198462A (ja) | データ再生装置 | |
| JPH0241058B2 (US20090163788A1-20090625-C00002.png) | ||
| JPS6323581B2 (US20090163788A1-20090625-C00002.png) | ||
| JPS6349809B2 (US20090163788A1-20090625-C00002.png) | ||
| JPH08115268A (ja) | メモリ回路装置 | |
| JP2854301B2 (ja) | メモリアクセス回路 | |
| JPH10340596A (ja) | データ記憶装置および半導体記憶装置 | |
| JPH0672910B2 (ja) | テストパタ−ンメモリ回路 | |
| JPS6232818B2 (US20090163788A1-20090625-C00002.png) | ||
| JP3655658B2 (ja) | 数値制御装置 | |
| JPS6019258A (ja) | 記憶装置 | |
| JPS6349808B2 (US20090163788A1-20090625-C00002.png) | ||
| JP2969645B2 (ja) | タイムスロット入替回路 | |
| JPH0467661B2 (US20090163788A1-20090625-C00002.png) | ||
| JPH0227600A (ja) | 集積回路装置 | |
| JPS58208997A (ja) | 誤り訂正を行なう記憶装置の部分書込みを含む連続動作方式 | |
| JPH01171191A (ja) | 演算機能付記憶素子 | |
| JPS63175956A (ja) | パリテイ回路 | |
| JPH06110824A (ja) | バスブリッジ装置 | |
| JPS635778B2 (US20090163788A1-20090625-C00002.png) | ||
| JPS63126047A (ja) | メモリ制御方式 | |
| JPH02125769A (ja) | 描画制御回路 |
