JPH0237878A - Clamp pulse generating circuit for video signal - Google Patents

Abstract

PURPOSE:To generate a clamp pulse which is strong in a noise and surely synchronizes in a back-porch by providing an AND output circuit of a clamp pulse output permitting signal and a clamp pulse timing signal. CONSTITUTION:For a video signal inputted to a terminal 1, a chrominance signal is removed by a low pass filter 2 and separated to a luminance signal. A clamp pulse output permitting signal is obtained through a counter 5 which is separated to a horizontal synchronizing signal with a synchronizing separating circuit 3, synchronized to the front end of an AFC circuit 4 and the synchronizing signal, initialized and counts a clock. By passing through a mono-stable vibrator 6 from a horizontal synchronizing signal, a clamp pulse timing signal to synchronize the rear edge of the synchronizing signal is obtained and both obtained signals are made into the output through an AND gate 7 to a clamp pulse output terminal 8. Thus, the clamp pulse can be surely synchronized in the back-porch and the stability for the noise can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clamp circuit that performs DC reproduction of a video signal in a video control system.

BACKGROUND OF THE INVENTION In recent years, there has been an increase in the number of video control systems that have additional functions that utilize digital technology.

In these systems, video signals are quantized and inversely quantized, and at that time, clamp circuits are often used to fix the DC level of the video signals. In particular, when only the luminance signal portion is quantized, a black level clamp is used, and since a synchronous clamp method is used, a separate timing pulse for clamping is required. FIGS. 3 and 4 are block diagrams of conventional video signal clamping pulse generation circuits.

1 is a video input terminal, 2 is a low-pass filter that separates the luminance signal from the video signal, 3 is a synchronization separation circuit for separating the horizontal synchronization signal, 4 is an automatic frequency control (AFC) circuit,
5 is a counter that is initialized in synchronization with the leading edge of the horizontal synchronizing signal and counts an output clock; 8 is a clamp pulse output terminal.

In FIG. 4, it has a monostable vibrator circuit 6 that generates a pulse of a constant width in synchronization with the trailing edge of the separated synchronization signal,
Other constituent blocks are the same as in FIG. Problems to be Solved by the Invention of Obtaining Clamp Pulses for Video Signals by the Structures of either FIG. 3 or FIG. 4. However, in the case of the structure shown in FIG. This circuit starts counting from the point of change in the output signal and generates a clamp pulse after a certain count, and is resistant to noise because it uses the AFC output signal as the reference for starting the count. However, the actual VTR
In non-standard signals such as playback signals, the width of the horizontal synchronization pulse may not comply with the broadcasting standard. In addition, there is a time delay in the synchronization signal output from the AFC circuit, so if the count is constant from the leading edge of the sync level, the clamp pulse may not be located at the back porch position, resulting in inaccurate positioning. ing.

On the other hand, in the case of the configuration shown in FIG. 4, the monostable vibrator circuit 6
is a circuit that generates a constant clamp pulse, but when the video signal input is weak, there is a high possibility that noise will be mixed into the separated composite synchronization signal. As a result, the monostable vibrator malfunctions and generates clamp pulses outside the back porch, resulting in the drawback that normal lamp pulse generation is no longer possible.

The present invention solves the above conventional problems, and aims to reliably synchronize the clamp pulse within the back porch with a simple configuration and improve stability against noise.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention cancels each other's shortcomings by performing a logic 81 (AND) of output signals obtained from a counter circuit and a monostable pie-break circuit. It has such a configuration.

With this configuration, when obtaining a clamp pulse generation circuit from a video signal, it can be synchronized reliably during the back porch with the circuit shown in Figure 3, which is strong against noise but has the characteristic that the synchronization position does not fall within the back porch. However, the AND of the output signal with the circuit shown in Figure 4, which has the possibility of generating a clamp pulse outside of the back porch due to its sensitivity to noise, is used as the clamp pulse to create a clamp pulse that is resistant to noise and reliably synchronizes during the back porch. can be obtained.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a video signal clamp pulse generation circuit according to an embodiment of the present invention.

In Fig. 1, 1 is a video signal input terminal, 2 is a low-pass filter (L P F ), 3 is a synchronous separation circuit, and 4 is an A
FC circuit, 5 is a counter, 6 is a monostable vibrator,
7 is an AND gate, and 8 is a clamp pulse output terminal.

9 is a clamp pulse output permission signal, and 10 is a clamp pulse timing signal.

The video signal input to terminal 1 is passed through a low-pass filter (LP
F) In step 2, the color signal is removed and separated into a luminance signal. Then, it is separated into a horizontal synchronization signal by a synchronization separation circuit 3, and then passes through an AFC circuit 4 and a counter 5 that is initialized in synchronization with the leading edge of the synchronization signal and counts clocks, as shown in FIG. Obtain a clamp pulse output permission signal that is slightly wider than the back porch. Further, by passing the horizontal synchronization signal through the monostable pie break 6, a clamp pulse timing signal synchronized with the trailing edge of the synchronization signal as shown in the figure is obtained. Both signals obtained in this way are A
By passing it through the ND gate 7 and outputting it to the clamp pulse output terminal 8, clamp pulses generated by noise can be removed from the monostable vibrator, and stability against noise can be improved.

Effects of the Invention As described above, according to the present invention, in order to generate a clamp pulse from a horizontal synchronization signal, a simple configuration is provided in which an AND output circuit of a clamp pulse output permission signal and a clamp pulse timing signal is provided, thereby reducing noise. This makes it possible to realize a device that generates clamp pulses that provide reliable synchronization in the back porch.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a video signal clamp pulse generation circuit according to an embodiment of the present invention, FIG. 2 is a timing waveform diagram thereof, and FIGS. 3 and 4 are diagrams showing a conventional video signal clamp pulse generation circuit. FIG. 1...Video signal input terminal, 2...Low pass filter, 3...Synchronization separation circuit, 4...
...AFC circuit, 5...Counter, 6...
... Monostable vibrator, 7 ... AND gate, 8 ... Clamp pulse output terminal. Name of agent: Patent attorney Shigetaka Awano and 1 other person Club output signal

Claims (1)

[Claims] A low-pass filter for separating the luminance signal from the video signal, a sync separation circuit for separating the horizontal sync signal,
an AFC (automatic frequency adjustment) circuit, a counter that is initialized in synchronization with the leading edge of the separated synchronizing signal and counts a clock, and a pulse of a constant width is generated in synchronization with the trailing edge of the separated synchronizing signal. A video signal clamp pulse generation circuit having a monostable vibrator circuit.