JPS6042664B2 - vertical synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization device for frequency-dividing a clock signal synchronized with a horizontal synchronization signal and synchronizing the divided output with a vertical synchronization signal in a television receiver or the like. .

Figure 1 shows the synchronization device that has been proposed in the past.
This is the clock input terminal of a frequency divider 2 configured to connect type flip-flops in series to obtain a divided output whose repetition frequency is equal to the vertical synchronization signal.

Terminal 4 is an input terminal of vertical synchronization separation circuit 5, receives a composite synchronization signal, and outputs a vertical synchronization signal. The phase comparator 6 receives the frequency divided output of the frequency divider 2 and the vertical synchronization signal, and the phase mismatch signal output of the phase comparator 6 is inputted to a first M-ary counter configured with a T-type flip-flop and a gate circuit. The phase match signal output of the phase comparator 6 is connected to the reset terminal of the first counter 7. The reset signal generator 8 receives the output of the first counter 7 and the output of the vertical synchronization circuit 5, and outputs it to the reset input terminal of the frequency divider 2. The conventional vertical synchronizer having such a configuration performs the following operations to synchronize and maintain synchronization between the frequency-divided output of the frequency divider 2 and the vertical synchronization signal.
In FIG. 1, for example, assuming that the vertical synchronization signal and the divided output of the frequency divider 2 are in an asynchronous state, only the phase mismatch signal of the phase comparator 6 is output, and the first counter 7 outputs the phase mismatch signal. Start counting.

The first counter 7 is not reset by the phase matching signal of the phase comparator 6, and counts the phase mismatching signal M times,
A reset signal generator 8 is used to reset the frequency divider 2 using a vertical synchronization signal.

Frequency divider 2 reset by reset signal generator 8
outputs a divided output synchronized with the vertical synchronization signal, so
The phase comparator 6 detects phase coincidence between the frequency divided output and the vertical synchronization signal, and the phase mismatch signal generates a phase coincidence signal, so the first counter 7 is reset by the phase coincidence signal. Frequency divider 2 is never reset by the vertical synchronization signal.

The above is the synchronous pull-in operation. The frequency divider 2 outputs a frequency-divided output synchronized with the vertical synchronization signal to a terminal 3, and maintains synchronization unless the phases of the frequency-divided output and the vertical synchronization signal differ due to disturbance or the like. Also, the sync separation output of the vertical sync separation circuit 5 is
In addition to the vertical synchronization signal, disturbance noise and the like are mixed, and the first counter 7 removes the disturbance noise.

That is, assuming that the frequency division output of the frequency divider 2 and the vertical synchronization signal are in a synchronized state, the first counter 7 is reset during the vertical synchronization signal period by the phase matching output of the phase comparator 6.
However, the phase comparator 6 compares the phases of the disturbance noise in the synchronous separation output and the frequency-divided output, and since the phases do not match, it outputs phase mismatch signals equal to the number of disturbance noises in the synchronous separation output.

The first counter 7 counts the corresponding phase mismatch signals, and the number of disturbance noises in the synchronization separation output is 1 vertical period (
The first counter 7 does not output disturbance noise if it is within M-1 in the period from when it is reset by the phase matching signal by the phase comparator 6 until the next reset). Therefore, the synchronization between the frequency-divided output and the vertical synchronization signal is maintained.

However, if M or more disturbance noises are mixed in the synchronized separated output during one vertical period, the first counter 7 outputs the Mth disturbance noise, and the reset signal generator 8 outputs the Mth disturbance noise, causing the frequency divider 2 to To reset, frequency divider 2 is reset by the disturbance noise in the synchronization separation output without performing regular frequency division (frequency division operation that obtains a divided output whose repetition frequency is equal to the vertical synchronization signal), and the frequency divider 2 Therefore, the frequency-divided output of the device 2 cannot be stably supplied.

For these reasons, not only is it not possible to obtain a stable playback screen, but if the number of disturbance noises during the synchronization separation output becomes extremely large, the frequency divider 2 will be constantly reset by the disturbance noise, resulting in the frequency division output could no longer be supplied to the output terminal 3, and the playback screen had a serious drawback of becoming a single horizontal character in the center of the cathode ray tube.

In conventional vertical synchronizers, a measure to prevent such a single horizontal character in a reproduced image is to increase the count value of the first counter 7, but the count value M of the counter 7 and the time D required for synchronization pull-in If one vertical period is V, then D=M■.

That is, since the time required for synchronization pull-in increases in proportion to the count value of the counter 7, the disadvantage remains that the time required for synchronization pull-in increases. In view of this, an object of the present invention is to obtain a stable playback screen without increasing the time required for synchronization acquisition even when a large number of disturbance noises are mixed in the synchronization separation output during one vertical period, and The purpose of the present invention is to propose a vertical synchronization device that does not cause the playback screen to become a single horizontal character.

One embodiment of the present invention will be described below with reference to FIG.

In FIG. 2, parts corresponding to those in FIG. 1 described above are given the same reference numerals, and detailed explanation of the invention will be omitted. That is, in FIG. 2, a clock signal with twice the frequency of the horizontal synchronizing signal is input to input terminal 1, and ten T-type flip-flops are connected in series to output a divided output with a repetition frequency equal to the vertical synchronizing signal. This is the clock input terminal of the frequency divider 2, which is configured as shown in FIG.

The input terminal 4 is an input terminal of a vertical synchronization separation circuit 5, into which a composite synchronization signal is input, and the vertical synchronization separation circuit 5 outputs a vertical synchronization signal.

The phase comparator 6 receives the divided output of the frequency divider 2 and the vertical synchronization signal, and outputs a phase mismatch signal and a phase match signal. T
a clock input terminal of an M-ary counter, that is, a first counter 7, configured by a type flip-flop and a gate circuit;
A phase mismatch signal output terminal of the phase comparator 6 is connected, and a phase match signal output of the phase comparator 6 is connected to a reset terminal of the first counter 7. The reset signal generator 8 receives the output of the first counter 7 and the output of the vertical synchronization separation circuit 5, and outputs it to the reset input terminal of the frequency divider 2. The clock input terminal of the second counter 9 configured as an F-adic counter using a T-type flip-flop and a gate circuit is connected to the phase mismatch signal output of the phase comparator 6, and the reset terminal of the second counter 9 is connected to the phase mismatch signal output of the phase comparator 6. The output of the second counter 9 is connected to the reset terminal of the fourth counter 7.
The vertical synchronizer of the present invention having such a configuration performs synchronization pull-in and synchronization maintenance between the frequency-divided output of the frequency divider 2 and the vertical synchronization signal by the following operations. That is, in FIG. 2, when disturbance noise is not mixed in the vertical synchronization separation output, the synchronization pull-in and synchronization holding operations are the same as those of the conventional vertical synchronization device shown in FIG. 1 described above, and a detailed explanation of the invention will be omitted.

When disturbance noise is present in the vertical synchronization separation output, the first counter 7 and the second counter 9 remove the disturbance noise.

That is, assuming that the divided output of the frequency divider 2 and the vertical synchronization signal are in a synchronized state, the first counter 7 is reset between the vertical synchronization signals by the phase comparator 6, and the second counter 9 is reset between the vertical synchronization signals.
is reset by the frequency division output of the frequency divider 2 (since the frequency division output and the vertical synchronization signal are synchronized, the first and second counters 7 and 9 are reset almost at the same time) However, the phase comparator 6 compares the phases of the disturbance noise in the synchronization separation output with the frequency-divided output, and outputs phase mismatch signals corresponding to the number of disturbances and noises. First counter 7 and second counter 9
counts the corresponding phase mismatch signals, but if the phase mismatch signals are within M-1 within one vertical period (=1V), the operation is the same as the disturbance noise elimination operation of the conventional example in Fig. 1 described above. A detailed explanation of the invention will be omitted. If M or more disturbance noises are mixed in the synchronization separation output, the phase comparator 6 outputs phase mismatch signals equal to the number of disturbance noises as described above.
The first counter 7 and the second counter 9 start counting the corresponding phase mismatch signals after each is reset as described above.

Here, if the first and second counters 7 and 9 are configured such that M>F, the second counter 9 resets the first counter 7 with the F-th phase mismatch output. In order to do this, divider 2
is not reset by disturbance noise during the synchronous separation output, and the frequency divider 2 outputs a stable frequency divided output to the output terminal 3.

Further, the count value M of the first counter 7 is larger than the count value F of the second counter 9, and it is usually best to use M=F+1.

Practically speaking, M=4 and F=3 are good. Due to this operation, the vertical synchronization device of the present invention does not disturb the synchronization relationship between the frequency division output of the frequency divider 2 and the vertical synchronization signal even when disturbance noise is mixed in the vertical synchronization separation output. Further, according to the invention, it is effective even if the synchronization pull-in time is sufficiently shortened,
It also contributes to shortening the synchronization pull-in time.

Note that the reset signal generator 8 is used to align the edges of the frequency-divided output and the vertical synchronization signal and is omitted, and the first counter 7
Directly connecting the output of the frequency divider 2 to the reset terminal of the frequency divider 2 does not affect the operation of the vertical synchronizer of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventionally proposed vertical synchronization device. FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, 1... clock input terminal of frequency divider 2 to which a clock signal of N times the horizontal frequency is input, 2...
・Frequency divider that outputs a divided output whose repetition frequency is equal to the vertical synchronization signal, 3... Output terminal of frequency divider 2, 4.
. . . Composite synchronization signal input terminal, 5 . . . Vertical synchronous separation circuit, 6 . ...First counter, 8...Pulse signal generator, 9...
- Shows the second counter.

Claims (1)

[Claims] 1 A vertical synchronization separation circuit that extracts a vertical synchronization signal from a composite synchronization signal, and a clock signal having a repetition frequency that is an arbitrary N times the horizontal synchronization signal (N is an integer greater than "0") is divided so that the repetition frequency becomes the vertical synchronization signal. a frequency divider that obtains a frequency division output equal to a synchronization signal; a phase comparator that compares the phases of the vertical synchronization signal and the frequency division output and outputs a phase match signal and a phase mismatch signal; and the frequency divider. A first counter that is reset by the output of the phase mismatch signal and generates a first counting output every time the phase mismatch signal is counted F times (F is an integer greater than "0") and the phase mismatch signal is counted M times (M is an integer larger than "0"). an integer greater than F) that produces a second count output for each count and whose count content is reset by either the phase matching signal or the first count output; and the second count. A vertical synchronization device comprising: a reset means for resetting the frequency divider according to an output.