JPH0379189A - H clear pulse generator - Google Patents

Abstract

PURPOSE:To easily form an LSI by counting down the integer multiple clock pulse of a sub carrier synchronous with the color burst of an input signal until a horizontal scanning frequency, generating an H clear pulse and specifiedly resetting the counter. CONSTITUTION:A clock pulse 55 of the integer multiple frequency of a sub carrier 56 synchronous with a color burst 54 included in an input video signal 51 is generated by a voltage controlled oscillator 6, etc., and a horizontal synchronizing signal 57 is generated from the signal 51 by a separator circuit 8. Then, the pulse 55 is counted down by a counter 9 and an OR circuit 10 and an H clear pulse 56 is generated. Further, a window pulse 58, which sub carrier cycle width is almost + or -1/4 to that of the pulse 56, is generated by a decoder 11 and a delay circuit 12 and the signal 57 is gated by the pulse 58 in an error counter 13 and an AND circuit 14. Then, the counter 9 is reset and the pulse 56 is digitally generated and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an H clear pulse generator, and more particularly to an H clear pulse generator that generates an H clear pulse used for detecting a horizontal scanning position in video signal processing. .

[Conventional technology]

Conventionally, this type of H clear pulse generator is configured in an analog format and generates a horizontal synchronization signal separated from the input video signal so as to be in phase with a subcarrier synchronized in frequency and phase with the color burst of the input video signal. This was achieved through phase modulation using a feedback loop. The horizontal synchronization signal is initially given a fixed delay of 1/2 subcarrier period for each line, then is variable delayed, enters a phase comparison circuit with the subcarrier, and the output of this phase comparison circuit is given the variable delay described above. It was designed to be controlled.

[Problem to be solved by the invention]

The above-mentioned conventional H clear pulse generator is composed of analog circuits, so it is not easy to integrate such as LSI, and it also requires a regulator, etc., so it has the disadvantage that it cannot save enough labor. There is.

An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to
An object of the present invention is to provide an H clear pulse generator that is easy to manufacture and can be expected to reduce the size and cost of the device.

[Means to solve the problem]

The H clear pulse generation device of the present invention includes a crop pulse generation means for generating a clock pulse having a frequency that is an integral multiple of a subcarrier synchronized with a color burst of an input video signal, and a horizontal synchronization signal for extracting a horizontal synchronization signal from the input video signal. a signal extracting means, a counter means for counting down the clock pulse to a horizontal scanning frequency to obtain an H clear pulse, and a window pulse generating means for obtaining a window pulse in which a predetermined variation width is added to the pulse width of the H clear pulse. and reset means for gating the horizontal synchronization signal and resetting the counter means using the window pulse.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the H clear pulse generator of the present invention. The embodiment shown in FIG.
The frequency of the crop pulse is set to NTS for practical convenience.
Four times the subcarrier frequency (fsc) of the C signal (4fs
Case c) is taken as an example.

In FIG. 1, a synchronization separation circuit 2, a burst flag generation circuit 3, a burst gate circuit 4, a phase comparator circuit 5, a voltage controlled oscillator 6, and a 1/4 frequency divider circuit 7 are subcarriers synchronized with the color burst of the input video signal. This is a crop pulse generating means for obtaining a clock pulse having a frequency that is an integral multiple of . Further, the horizontal synchronization separation circuit 8 is horizontal synchronization signal extraction means for obtaining a horizontal synchronization signal from the input video signal. Further, the 1/910 counter 9 and the OR circuit 10 are counter means for counting down the clock pulse to obtain an H clear pulse. Further, the decoder 11 and the delay circuit 12 are
This is a window pulse generating means that obtains a window pulse with approximately ±1/4 subcarrier cycle width relative to the H clear pulse, and the error counter 13 and the AND circuit 14 gate the horizontal synchronization signal with the window pulse and generate a window pulse with a width of 1/9.
10 is a reset means for resetting the counter 9.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

A video signal 51 input from the input terminal 1 is sent to the sync separation circuit 2 and the burst gate circuit 4. The synchronization separation circuit 2 extracts the synchronization signal 52 and supplies it to the burst flag generation circuit 3. The burst flag generation circuit 3 generates a burst flag pulse 53, thereby separating the color burst contained in the video signal 51. 54 is extracted by the burst gate circuit 4. Color burst 54 is
The clock pulse 55 generated by the voltage controlled oscillator 6 is divided into 1/2 by the phase comparison circuit 5.
Subcarrier 5 that counts down with 4 frequency divider circuit 7
The phase is compared with 6. Since this phase comparison output controls the voltage controlled oscillator 6, the subcarrier 56 is held in synchronization with the color burst 54 and in phase.

Since the subcarrier (f sc) of the NTSC signal and the horizontal scanning frequency (fH) have a relationship of fn = fsc The H clear pulse 56 obtained by counting down is synchronized with the horizontal synchronization signal 57 obtained from the synchronization signal 52 through the horizontal synchronization separation circuit 8. The decoder 11 generates a pulse with a 1/2 subcarrier cycle width of ±1 clock width for each reference edge of the H clear pulse 56, and a pulse with a total width of ±1/4 cycle. A window pulse 58 compensated for the operation time of the AND circuit 14 is generated and sent to the error counter 13.

The error counter 13 compares the window pulse 58 and the horizontal synchronizing signal 57, and when the phases match, A
The ND circuit 14 is turned off and the 1/910 counter 9 is operated at the same cycle. When the phase mismatch continues for a certain period of time, the AND circuit 14 is enabled and the 1/910 counter 9 is operated at the same cycle.
910 counter 9 is cleared externally to match the phases.

When actually used, the number of buses of the error counter 13 is determined by taking into consideration the time of synchronization separation errors and momentary signal interruptions. In this way, the H clear pulse can be digitally generated and output. Note that for signals with a lot of noise, since the means for generating the clock pulse 55 has a lot of jitter, a method is adopted in which the pulse width of the window pulse 58 is slightly widened in the delay circuit 12.
It is clear that this also falls within the scope of the present invention.

〔Effect of the invention〕

As explained above, the present invention digitally processes the relationship between color bursts and horizontal synchronization signals, thereby making it easier to integrate into an LSI than in the prior art, making it possible to downsize and reduce equipment costs. This has the effect of realizing a clear pulse generator.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the clear pulse generator of the present invention. 2... Synchronous separation circuit, 3... Burst flag generation circuit, 4... Burst gate circuit, 5... Phase comparison circuit, 6... Voltage controlled oscillator, 7... 1/4 frequency division Circuit, 8... Horizontal synchronization separation circuit, 9... 1/910 counter, 10... OR circuit, 11... Decoder, 12
...Delay circuit, 13...Error counter, 14...
・AND circuit.

Claims (2)

[Claims] (1) crop pulse generation means for obtaining a clock pulse having a frequency that is an integral multiple of a subcarrier synchronized with a color burst of an input video signal; horizontal synchronization signal extraction means for extracting a horizontal synchronization signal from the input video signal; a counter means for obtaining an H clear pulse by counting down the pulse to a horizontal scanning frequency; a window pulse generating means for obtaining a window pulse in which a predetermined variation width is added to the pulse width of the H clear pulse; and reset means for gating a horizontal synchronizing signal and resetting the counter means. (2) The H clear pulse generating device according to claim 1, wherein the predetermined fluctuation width to be given to the window pulse is set to ±1/4 cycle width of the subcarrier.