JPH0234467B2 - - Google Patents
Info
- Publication number
- JPH0234467B2 JPH0234467B2 JP58230288A JP23028883A JPH0234467B2 JP H0234467 B2 JPH0234467 B2 JP H0234467B2 JP 58230288 A JP58230288 A JP 58230288A JP 23028883 A JP23028883 A JP 23028883A JP H0234467 B2 JPH0234467 B2 JP H0234467B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- channel
- output
- transistors
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58230288A JPS60121760A (ja) | 1983-12-06 | 1983-12-06 | 相補型半導体集積回路装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58230288A JPS60121760A (ja) | 1983-12-06 | 1983-12-06 | 相補型半導体集積回路装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60121760A JPS60121760A (ja) | 1985-06-29 |
| JPH0234467B2 true JPH0234467B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1990-08-03 |
Family
ID=16905460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58230288A Granted JPS60121760A (ja) | 1983-12-06 | 1983-12-06 | 相補型半導体集積回路装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60121760A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH041151U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1990-04-18 | 1992-01-07 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS587857A (ja) * | 1981-07-06 | 1983-01-17 | Nippon Telegr & Teleph Corp <Ntt> | 相補型ｍｉｓ回路装置 |
-
1983
- 1983-12-06 JP JP58230288A patent/JPS60121760A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH041151U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1990-04-18 | 1992-01-07 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60121760A (ja) | 1985-06-29 |