JPH023307B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same;
Specifically, the present invention relates to a semiconductor device manufactured using a semiconductor layer formed on an insulating substrate and a method for manufacturing the same.

Technical background of the invention and its problems A semiconductor device formed on an insulating substrate is, for example,
It is known as SOS (Silicon on Sapphire) structure.

In a semiconductor device with an SOS structure, the silicon layer outside the element formation region (field region) is usually oxidized in an oxidizing atmosphere to form a field oxide film that reaches the insulating substrate, thereby separating the elements.
Recently, when oxidizing the silicon layer in the field region, in addition to forming a first oxide film that reaches the insulating substrate for element isolation, a second oxide film that does not reach the insulating substrate is formed. A structure in which a silicon layer remains under the oxide film is manufactured. In this way, the silicon layer remaining under the thick second oxide film is not easily affected by the elements and wiring formed on the second oxide film, so it is used for wiring connecting elements and for fixing the substrate potential of transistors. It is useful for electrode leads, etc., and can also be used as a resistance element by appropriately selecting the impurity concentration.

By the way, conventionally, a semiconductor device having the above-mentioned structure,
For example, an ER type inverter is manufactured by the method shown in FIGS. 1a to 1d.

First, a P-type silicon layer 2 is placed on a sapphire substrate 1.
is epitaxially grown, and an oxidation-resistant mask material such as Si ₃ N ₄ film pattern 3 is selectively formed thereon. At this time, silicon layer 2 is formed in a later thermal process.
In order to prevent defects from entering the silicon layer 2 due to the difference in thermal expansion coefficient with the Si ₃ N ₄ film pattern 3, an SiO ₂ film or the like may be formed between the two. Continuing,
Silicon layer 2 using Si ₃ N ₄ film pattern 3 as a mask
The exposed region 4 is removed by etching to reduce its thickness to about half (as shown in FIG. 1a).
Next, a part of the Si ₃ N ₄ film pattern 3 is removed by photolithography to form an opening 5 (as shown in FIG. 1b). After this, the silicon layer 2 in the opening 5 may be slightly etched if necessary. Next, thermal oxidation treatment is performed. At this time, due to the difference in the thickness of the silicon layer 2, a first oxide film 6 that reaches the sapphire substrate 1 is formed in the region 4, and a second oxide film 7 that does not reach the sapphire substrate 1 is formed in the opening 5, respectively.
A resistive element 8 made of silicon is formed under the second oxide film 7 (as shown in FIG. 1c). Then,
After removing the Si ₃ N ₄ film pattern 3, a thin thermal oxide film 9 and a gate electrode 10 are sequentially formed using a conventional method.
Next, an n-type impurity such as phosphorus is ion-implanted.
Subsequently, a CVD-SiO ₂ film 11 is deposited on the entire surface.
At this time, the ion-implanted phosphorus is activated and the source/drain regions 12 and 13 and the resistance extraction portion 1 are activated.
4 is formed. Next, contact hole 1
After opening the holes 5, an Al film is deposited on the entire surface, and this is patterned to form Al wiring 16, thereby manufacturing an ER type inverter (as shown in FIG. 1d).

In the semiconductor device described above, the first oxide film 6 must be formed sufficiently thick so as to reach the sapphire substrate 1 and cover the ends of the island-shaped silicon layer. On the other hand, the second oxide film 7 must be formed so that a silicon layer (for example, the resistive element 8) of a certain thickness remains thereunder. In this step, since the second oxide film 7 is formed simultaneously with the first oxide film 6, its thickness is determined by the oxidation time for forming the first oxide film 6. Therefore, it is difficult to make the thickness of the silicon layer under the second oxide film 7 constant, and there is a problem that the controllability of the resistance value is poor.

Therefore, before removing a part of the Si ₃ N ₄ film pattern 3 to form the opening 5, thermal oxidation treatment is performed to form the first
There is also a method of forming a second oxide film 6, then removing a part of the Si ₃ N ₄ film pattern 3 to form an opening 5, and performing thermal oxidation treatment again to form a second oxide film 7. Conceivable.

However, in this case, the time required for the thermal oxidation treatment performed at high temperature increases, causing problems such as autodoping of Al from the sapphire substrate 1 to the silicon layer 2.

Purpose of the Invention The present invention provides a method for forming a film with a constant thickness under the second oxide film regardless of the formation conditions of the first oxide film for element isolation.
It is an object of the present invention to provide a semiconductor device having a semiconductor layer used for wiring, a resistance element, etc., and a method for manufacturing the same.

Summary of the Invention The first invention of the present application includes an insulating substrate, an island-shaped semiconductor layer provided on the insulating substrate and separated by a first oxide film, and an island-shaped semiconductor layer provided partially on the surface of the semiconductor layer. and an oxidation-resistant insulating layer provided at the bottom of the second oxide film at a predetermined distance from the surface of the insulating substrate.

Examples of the insulating substrate in the present invention include sapphire, spinel, garnet, and silicon dioxide.

The semiconductor layer in the present invention is, for example, Si,
Examples include common semiconductor layers such as Ge, GaAs, and InSb. Although these materials may be single crystal, polycrystalline, or amorphous, single crystal materials are generally used from the viewpoint of element performance of semiconductor devices.

In the present invention, the oxidation-resistant insulating layer provided at the bottom of the second oxide film so as to be separated from the surface of the insulating substrate by a predetermined distance may be made of Si ₃ N ₄ or the like. This oxidation-resistant insulating layer serves to prevent further growth of the second oxide film in a subsequent thermal oxidation step. Therefore, the semiconductor device of the present invention has a semiconductor layer of a constant thickness between the oxidation-resistant insulating layer and the insulating substrate, and can achieve high performance.

Further, the second invention of the present application is a method of manufacturing the semiconductor device of the first invention of the present application by the following steps.

First, a semiconductor layer is formed on an insulating substrate, and then an oxidation-resistant mask material is selectively formed on the semiconductor layer, and the exposed semiconductor layer is partially etched away using this mask material. Here, an example of the oxidation-resistant mask material is a Si ₃ N ₄ film pattern. In addition, when the semiconductor layer is a silicon layer and the oxidation-resistant mask material is a Si ₃ N ₄ film pattern, defects may occur in the silicon layer during the thermal process due to the difference in thermal expansion coefficient between the silicon layer and the Si ₃ N ₄ film pattern. In order to prevent this from occurring, a SiO ₂ film or the like may be formed between the two.

Next, a portion of the oxidation-resistant mask material is removed to form an opening, and a substance for forming an oxidation-resistant insulating layer is ion-implanted into the semiconductor layer through the opening. Here, examples of the substance forming the oxidation-resistant insulating layer include nitrogen when the semiconductor layer is silicon. These react to form a Si ₃ N ₄ layer in a later heat treatment step. When the semiconductor layer between the oxidation-resistant insulating layer and the insulating substrate is used, for example, as a lead for an electrode for fixing the substrate of a transistor, impurity ions can be implanted before or after the above steps to increase the conductivity. Furthermore, the resistance value when used as a resistance element can be similarly controlled by ion implantation.

Next, a thermal oxidation treatment is performed after the heat treatment, or a single thermal oxidation treatment is performed to form a first oxide film on the etched portion of the semiconductor layer reaching the insulating substrate, and a second oxide film partially on the surface of the semiconductor layer. An oxidation-resistant insulating layer is formed on the oxide film and the bottom of the second oxide film at a predetermined distance from the surface of the insulating substrate. The oxidation-resistant insulating layer is formed during the heat treatment if thermal oxidation treatment is performed after heat treatment, or at the beginning of the heat treatment if one-time thermal oxidation treatment is performed, and the second oxide film forms the oxidation-resistant insulating layer. Prevents growth beyond layers. Therefore, a semiconductor device having a semiconductor layer with a constant thickness between the oxidation-resistant insulating layer and the insulating substrate can be manufactured regardless of the conditions for forming the first oxide film.

Embodiment of the Invention An embodiment in which the present invention is applied to an ER type inverter having an SOS structure will be described with reference to FIGS. 2a to 2f.

[] First, a p-type silicon layer 102 is formed on a sapphire substrate 101, and selectively
A Si ₃ N ₄ film pattern 103 was formed. next,
Using the Si ₃ N ₄ film pattern 103 as a mask, the exposed region 104 of the silicon layer 102 was removed by etching to reduce its thickness to about half (as shown in FIG. 2A). Next, a photoresist pattern 105 is used as a mask by photolithography.
A part of the Si ₃ N ₄ film pattern 103 is selectively removed to form an opening 106 and the silicon layer 102 is removed.
The surface was exposed (as shown in Figure 2b).

[] Next, nitrogen ions were implanted through the opening 105 at an implantation energy of 130 KeV and a dose of 2×10 ¹⁸ /cm ² (as shown in FIG. 2c). Next, photoresist pattern 10
5 was removed and subjected to thermal oxidation treatment in high temperature steam. Nitrogen ions implanted into the silicon layer at an early stage of this thermal oxidation process react with surrounding silicon to form a Si ₃ N ₄ layer 107. Furthermore, in the region 104, a first oxide film 108 is formed that reaches the sapphire substrate 101. Also,
A second oxide film 109 is formed in the opening 106, but since the Si ₃ N ₄ layer 107 has already been formed, it does not grow beyond this Si ₃ N ₄ layer 107. Therefore, a resistive element 110 made of silicon having a constant thickness is formed between the Si ₃ N ₄ layer 107 and the sapphire substrate 101 (as shown in FIG. 2d).

[] Next, the Si ₃ N ₄ film pattern 103 was removed and dry oxidation was performed to form an oxide film 111 of 500 Å on the exposed silicon layer surface. Subsequently, polycrystalline silicon was deposited on the entire surface and a gate electrode 112 was formed by photolithography, followed by implantation energy of 150 KeV and dose of 5×10 ¹⁵ /cm ²
Phosphorus ions were implanted under the following conditions (as shown in Figure 2e). Next, CVD was applied to the entire surface to a thickness of 1 μm.
A SiO ₂ film 113 was deposited. At this time, the phosphorus ions are activated and the source/drain regions 114,
115 and a resistance extraction portion 116 are formed.
Subsequently, contact holes 117 were opened, and an Al film was deposited on the entire surface, followed by patterning to form Al interconnections 118 (as shown in FIG. 2f).

As described above, an ER type inverter with an SOS structure was manufactured.

Therefore, in the ER type inverter of the above embodiment, the Si ₃ N ₄ layer 107 is provided under the second oxide film 109, and the silicon layer between the Si ₃ N ₄ layer 107 and the sapphire substrate 101 is used as a resistance element. Therefore, even in the thermal oxidation treatment to form the oxide film 111 (gate oxide film), the second oxide film 109 grows due to the presence of the Si ₃ N ₄ layer 107, and the resistor element 11
This can prevent the thickness of 0 from decreasing. Therefore, the resistance value of the resistance element 110 could be maintained.

Furthermore, according to the above method, the growth of the second oxide film 109 is inhibited by the Si ₃ N ₄ layer 107;
Regardless of the conditions for forming the first oxide film 108,
An ER type inverter having a resistance element 110 made of silicon with a constant thickness between the Si ₃ N ₄ layer 107 and the sapphire substrate 101 could be manufactured with high precision and high performance could be achieved. Furthermore, since the first and second oxide films 108 and 109 can be formed in one thermal oxidation process, autodoping of Al from the sapphire substrate 101 to the silicon layer can be reduced.

Note that the silicon layer between the oxidation-resistant insulating film and the insulating substrate is not limited to being used as a resistance element as in the above embodiment, but can also be used, for example, as a lead for an electrode for fixing the substrate potential of a transistor. In such cases, impurity ions are usually implanted before or after the ion implantation of the material forming the oxidation-resistant insulating film. Although the ion-implanted impurities are activated and diffused during thermal oxidation treatment, they do not diffuse beyond the oxidation-resistant insulating film, so the resistance value of the silicon layer can be precisely controlled.

Further, in the above embodiment, the n-channel device was manufactured using phosphorus as the n-type impurity, but arsenic or antimony may be used as the n-type impurity. Also, p
P-channel devices can also be manufactured using aluminum, boron, gallium, indium, etc. as type impurities.

Effects of the Invention According to the present invention, regardless of the formation conditions of the first oxide film for element isolation, it can be used for wiring, resistive elements, etc. with a constant thickness between the oxidation-resistant insulating film and the insulating substrate. It is possible to provide a semiconductor device in which a semiconductor layer can be formed and high performance can be achieved, and a method for manufacturing the same.

[Brief explanation of drawings]

Figures 1a to d are cross-sectional views showing a conventional method for manufacturing an E-R inverter with an SOS structure in order of process, and Figures 2a to f are E-R inverters with an SOS structure according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a method for manufacturing an R-type inverter in order of steps. 101...Saphire substrate _, 102...Silicon layer, 103... _Si3N4 film pattern, 107...
Si ₃ N ₄ layer, 108...first oxide film, 109...
Second oxide film, 110...Resistance element, 111...
Oxide film, 112... Gate electrode, 113...
CVD-SiO ₂ film, 114, 115...source/drain region, 116...resistance extraction part, 117...
...Contact hole, 118...Al wiring.

Claims (1)

[Scope of Claims] 1. an insulating substrate; a first insulating substrate provided on the insulating substrate;
an island-shaped semiconductor layer separated by an oxide film;
A second oxide film partially provided on the surface of the semiconductor layer; and an oxidation-resistant insulating layer provided at the bottom of the second oxide film so as to be separated from the surface of the insulating substrate by a predetermined distance. Characteristic semiconductor devices. 2. Forming a semiconductor layer on an insulating substrate, selectively forming an oxidation-resistant mask material on the semiconductor layer, and partially etching away the exposed semiconductor layer using this mask material. a step of removing a portion of the oxidation-resistant mask material to form an opening, and then ion-implanting a substance to form an oxidation-resistant insulating layer into the semiconductor layer through the opening; and a step of performing heat treatment after heat treatment. An oxidation treatment or a single thermal oxidation treatment is performed to form a first oxide film on the etched portion of the semiconductor layer that reaches the insulating substrate, a second oxide film partially on the surface of the semiconductor layer, and a second oxide film on the surface of the semiconductor layer. A method for manufacturing a semiconductor device, comprising the step of forming an oxidation-resistant insulating layer on the bottom of the oxide film of No. 2 at a predetermined distance from the surface of the insulating substrate. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the component of the semiconductor layer is silicon, and the substance forming the oxidation-resistant insulating layer is nitrogen.