JPH01143337A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the position of channel stopper to be accurate by forming the second non-oxidizable layer while covering the first non-oxidizable layer formed selectively, by allowing the second non-oxidizable layer to be transmitted, and introducing impurities with the first non-oxidizable layer as a mask. CONSTITUTION:An SiO2 film 21, an Si3N4 film 22, and an SiO2 film 23 are formed on an element-forming area of an Si substrate 11 to form the first non-oxidizable film. Then, an Si3N4 film 24 is formed over the entire surface as the second non-oxidizable film and impurities 26 for channel stopper are introduced through the film 24. Then, an SiO2 film 25 is formed over the entire surface and etched back to form the side wall of the first non-oxidizable film. The RIE is performed to the film 24 with this side wall as a mask and the sectional area of film 24 is configured in L shape. After eliminating the film 25, the LOCOS is performed and an SiO2 film for separating elements 2 is formed. Then, the offset amount of the channel stopper 13 from an element formation area 14 can be controlled accurately. Also, a birds' beak 12a can be made smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having an element isolation region and an element formation region in contact with the element isolation region.

[Summary of the invention]

The present invention provides a method for manufacturing a semiconductor device as described above, in which a second oxidation-resistant layer is formed on a semiconductor substrate to cover the selectively formed first oxidation-resistant layer, and the second oxidation-resistant layer is transmitted through the second oxidation-resistant layer. By introducing an impurity for a channel stopper into the semiconductor substrate using the first oxidation-resistant layer as a mask, it is possible to precisely control the position of the impurity introduction region with respect to the element formation region, and to achieve high integration and high quality. This makes it possible to manufacture semiconductor devices.

[Conventional technology]

The element isolation region of a semiconductor device is generally formed by the LOCO5 method. FIG. 3 shows a MOS transistor manufactured using the conventionally known LOCO3 method.

That is, a SiO□ film 1 for element isolation is formed on the surface of the Si substrate 11.
2 is formed by the LOCO3 method, and this SiO□ film I
A channel stopper 13 is formed below 2. Furthermore, a gate electrode 16 is formed on the element formation region 14 surrounded by the SiO□ film 12 via a Sing film 15 which is a gate oxide film.

By the way, the data retention characteristics of the resistive load type MO3-3RAM are determined by the current drive capability ratio of the driver transistor and the switching transistor. Therefore, it is necessary to narrow the inside of the gate of the switching transistor.

However, in the conventionally known LOCO3 method, the third
As is clear from the figure, the bird's beak 12a of the SiO□ film 12 is long and the channel stopper 13 extends widely into the element forming region 14, so the narrow channel effect is too large. Therefore, the inside of the gate could not be made very narrow, and the data retention characteristics of the SRAM were not very high.

Also, if the bird's beak 12a is long like this, the SRAM
It has not been possible to increase the degree of integration of semiconductor devices such as these.

In order to solve these problems, various modified LOCO3 methods have been proposed. Figure 4 is one of them, an Extended Abstract of
The 17th Conference on 5o
lid 5tate Devices and Mate
Rials, Tokyo, 1985. pp, 337-3
Offcent LOGO3 (O3EL) listed in 40
O) Shows the law.

In this 03ELO method, as shown in FIG. 4A, a pad 17) SiO2 film 21 and an Si3 film are formed on the Si substrate 11.
N, selectively forming the film 22 and the SiO□ film 23, and further forming sidewalls consisting of the 5iJ4 film 24 and the SiO□ film 25 having an L-shaped cross section on the sides of these films 21 to 23; Using these films 21 to 25 as a mask, impurity 26 for a channel stopper is ion-implanted.

Then, by removing the SiO□ film 23.25 and oxidizing the Si substrate 11, as shown in FIG. 4B,
A 5iOz film 12 for element isolation and a channel stopper 13 are formed.

According to this 03ELO method, the 5iJa film 24 is
23, that is, offset from the films 21-23, as shown in FIG. 4B.
The bird's beak 12a of the NG film 12 is short.

[Problem that the invention seeks to solve]

However, in the above-mentioned 03ELO method, bird's beak 12a
Since the 5iaN4 film 24 for suppressing the ions also serves as a mask for the ion implantation of the impurity 26, the amount of offset of the channel stopper 13 from the element formation region 14 is also very large, as shown in FIG. 4B.

Therefore, the narrow channel effect hardly appears, which makes it impossible to increase the current drive capability ratio between the driver transistor and the switching transistor, and the data retention characteristics of the SRAM are not very high. .

Moreover, it is not easy to suppress variations in the thickness of the sidewalls made up of the 5isNa film 24 and the 5402 film 25, and it is also not possible to accurately control the amount of offset of the channel stopper 13 from the element forming region 14.

Furthermore, since the impurity 26 is ion-implanted with the sidewalls made of the Si3N4 film 24 and the Sin film 25 formed, if the element formation regions 14 are placed too close to each other, the impurity 26 will be ion-implanted between them. It is not possible to form a channel stopper 13.

Therefore, even though the bird's beak 12a is short, a semiconductor device with a high degree of integration cannot be manufactured.

Furthermore, since the ion implantation of the impurity 2G is performed directly into the Si substrate 11, the Si substrate 11 is often damaged, making it impossible to manufacture a high quality semiconductor device.

[Means for solving problems]

The method for manufacturing a semiconductor device according to the present invention includes a semiconductor device 11
a step of selectively forming a first oxidation-resistant layer 21, 22, 23 in a portion of the semiconductor substrate that should be aligned with the element forming region 14; forming a second oxidation-resistant layer 24 on the first oxidation-resistant layer 21 .
A step of introducing an impurity 26 for the semiconductor substrate 11 into the semiconductor substrate 11 using 22.23 as a mask, and a step in which the second oxidation-resistant layer 24 is at least the first oxidation-resistant layer 2
1.22.The second oxidation-resistant layer 2 remains on the sides of 23.
4, and after this step, the semiconductor substrate 1
1 to form an element isolation region 12.

[Effect]

In the method for manufacturing a semiconductor device according to the present invention, the selectively formed first oxidation-resistant layer 21, 22, 23 is covered with the second oxidation-resistant layer 24, and the first oxidation-resistant layer 21, 22, 23 is masked. Since the impurity 26 for the channel stopper 13 is introduced into the semiconductor substrate 11, the effective area of the mask increases by the thickness of the second oxidation-resistant layer 24, and the position of the impurity introduction region is The thickness of the oxidation-resistant layer 24 can be controlled.

Further, when introducing the impurity 26 for the channel stopper 13, the second oxidation-resistant layer 24 is formed on the semiconductor substrate 11, and the semiconductor substrate 11 is not exposed, so that the semiconductor substrate 11 is less damaged.

〔Example〕

Hereinafter, first and second embodiments of the present invention applied to the manufacture of Mo3) transistors will be described with reference to FIGS. 1 and 2.

FIG. 1 shows a first embodiment. In this first embodiment, as shown in FIG.
First, a SiO2 film 21 for a pad of about 100000000000000000000000000000000000000000000000000000000000000000000000000000000],N400 film 21 is formed on this SiO□ film 21.
A 5i02 film 23 having a thickness of about 3,000 layers is formed thereon by CVD.

Next, as shown in FIG. 1B, the films 21 to 2 of the part of the St substrate 11 corresponding to the part to be the element formation region are
The other portions of the films 21 to 23 are removed by RIB so that only the film 3 remains. Thereafter, a 5iJn film 24 is formed on the Si substrate 11 by low pressure CVD so as to cover the remaining films 21 to 23 as well.

And B as an impurity 26 for the N-channel stopper.
Ion implantation is performed at an energy of 50 keV. This impurity 26 does not pass through the three-layer films 21 to 23, but
3N passes through the membrane 24 and is introduced into the Si substrate 11 at a concentration of 5xlOI3 atoms cm-2.

Next, as shown in FIG. 1C, a film with a thickness of 3.
A 5i02 film 25 with a thickness of about 1,000 yen is formed by CVD, and this SiO□ film is etched back to form an S as shown in FIG. 1D.
The side walls of the iO□ film 25 are formed. And this 5i02
Using the film 25 as a mask, RIB is performed on the 5iJa film 24 to form the Si3N4 film 24 into a cross-section.

Next, the 510□ film 25 is removed by etching, and in this state, LOGO3 is performed as shown in FIG. 1E. Thereafter, a MoS transistor as shown in FIG. 1F is manufactured through conventionally known steps.

In the first embodiment as described above, as is clear from FIG. 1B, the sidewall made of the Si3N film 24 also serves as a mask for the ion implantation of the impurity 26, so that the film thickness of the Si, N, film 24 is By controlling , the region where the impurity 26 is introduced can be controlled.

The film thickness 4 controllability of the Si+Na film 24 by low pressure CVD is very high. Therefore, as is clear from FIGS. 1E and 1F, the amount of offset of the channel stopper 13 from the element formation region 14 can be controlled to an optimal value.

Therefore, such a Mo3) transistor can generate an optimal narrow channel effect, and by using such a Mo3) transistor, an SRAM with high data retention characteristics can be manufactured.

FIG. 2 shows a second embodiment. This second embodiment is also similar to the first embodiment up to the step shown in FIG. 1B. Next to this process, the Si3N4 film 24 is etched back, and the Si3N film 24 is converted into a three-layer film 21 as shown in FIG. 2A.
~23 left only on the sides.

Next, the SiO□ film 23 is removed by etching, and in this state, LOGO3 is performed as shown in FIG. 2B. Thereafter, a MOS transistor as shown in FIG. 2C is manufactured through conventionally known steps.

Even in the second embodiment as described above, the same effects as in the first embodiment described above can be obtained.

〔Effect of the invention〕

In the method for manufacturing a semiconductor device according to the present invention, since the position of the impurity doped region can be controlled by the thickness of the second oxidation-resistant layer, the position of the impurity doped region with respect to the element formation region can be precisely controlled. .

Furthermore, since the position of the impurity introduction region is controlled by the thickness of the second oxidation-resistant layer, it is possible to introduce impurities into the element isolation region even if the element formation regions are placed close to each other. It is possible to manufacture multiple semiconductor devices.

Furthermore, since the semiconductor substrate is less damaged when impurities for channel stoppers are introduced, high-quality semiconductor devices can be manufactured.

[Brief explanation of the drawing]

1 and 2 are side sectional views sequentially showing first and second embodiments of the present invention, respectively. FIG. 3 is a side sectional view of a MOS transistor manufactured according to one conventional example, and FIG. 4 is a side sectional view showing another conventional example. In addition, in the symbols used in the drawings, 11...-------3i base 12.2
1,23-----3iOz film 13---------1.-Channel stopper 14-----1-----------
--------Element formation area 22.24------
--813Nm membrane.

Claims (1)

[Claims] A method for manufacturing a semiconductor device having an element isolation region and an element formation region in contact with the element isolation region, wherein a first oxidation-resistant layer is provided in a portion of the semiconductor substrate that is to be the element formation region. selectively forming a second oxidation-resistant layer on the semiconductor substrate, covering the first oxidation-resistant layer; introducing an impurity for a channel stopper into the semiconductor substrate using the first oxidation-resistant layer as a mask; A method for manufacturing a semiconductor device, comprising the steps of: removing the oxidation-resistant layer; and forming the element isolation region by selectively oxidizing the semiconductor substrate after this step.