JPH0468564A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of process by simplifying the process of forming an element isolation layer for forming a C-MOS which possesses an n-channel field effect transistor (n-MOS-FET) and a p-channel field-effect transistor (p- MOS-FET) on the same semiconductor substrate. CONSTITUTION:After forming element isolation trenches 4 on a semiconductor substrate 1, respective conductivity type channel stopper layers 5 and 6 are formed, then, an insulating layer is embedded in each trench 4. The insulating layer is etched back so as to form an element isolation separating layer 8, then, ions are implanted for forming a well region which forms respective conductivity type regions 10 and 11 having the trench 4 as the target. Therefore, conventional special target formation is not necessary for each well region formation. Since the well region formation is performed after the trench is formed, for, example, punch through prevention and ion implantation for Vth adjustment can be carried out using the same mask as the ion implantation mask simultaneously with the ion implantation process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in which an n-channel field effect transistor (nMC) S-F is formed on a common semiconductor substrate.
ET) and P-channel field effect transistor (pMO3
-FET), for example, in which a so-called C-MOS is formed.

[Summary of the invention]

The present invention relates to a method for manufacturing a semiconductor device, in which a semiconductor substrate has a first conductivity type region and a second conductivity type region each serving as a circuit element formation portion, and an element isolation trench is provided. After forming an element isolation trench in this semiconductor substrate and filling the trench with an insulating material, impurity ions are used to form a well region for forming a first conductivity type region and a second conductivity type region in predetermined portions. By performing the ion implantation process, the manufacturing method is simplified, and in particular, the number of manufacturing steps is reduced.

[Conventional technology]

Conventionally, as shown in the manufacturing process diagram in Fig. 4, for example, C
- When manufacturing a semiconductor integrated circuit having a MOS, first, as shown in FIG. 4A, a semiconductor substrate (1) made of a p-type or n-type high resistivity semiconductor, such as a Si substrate, is prepared;
A material layer (2) for forming marks to be described later on its surface.
2) is formed, for example, by surface thermal oxidation of the substrate (1).

Next, as shown in FIG. 4B, for the material layer (22),
Pattern etching is performed by RIE (reactive ion etching) using photolithography to form a target layer (23) of a predetermined shape at a predetermined position, and the photoresist used in the photolithography for forming this mark is removed, and then With this target (23) as a landmark,
For example, by forming a P-type well and an n-type well, respectively,
A P-type head region (24) and an N-type region (25) are formed by each well. To form each of these regions (24) and (25), that is, each well region, first perform ion implantation of P-type impurities to form an n-type well, using the target as a mark, and then implant the other n-type well. An ion implantation operation of n-type impurity is performed to form a . After that, heat treatment for activation and diffusion of these implanted impurities is performed to form an n-type head region (24) and an n-type region (25) by each n-type and n-type well region.
form.

After that, using photolithography to create trenches (30) at predetermined positions, for example, between each region (24) and (25), and further at a predetermined part within each region (24) and (25), using Tagela (23) as a landmark. formed by For example, as shown in FIG. A polycrystalline silicon layer (27) is formed to a certain thickness, a photoresist (28) is applied over the entire surface, and this is exposed and developed to form a core (30) in the trench forming area.

Then, as shown in the fourth diagram, after forming trenches (30) to a depth of, for example, 5,000 mm by RIE, each trench (30) for forming a p-channel stop region and an n-channel stop region is formed from the inner surface of each trench (30). Ion implantation of n-type and n-type impurities is performed.

After that, as shown in FIG. 4E, after forming a SiO□ film (32) by thermal oxidation, etc., including the inside of the trench (30),
An insulating material (33A) made of SiO□ or the like is formed on the entire surface including the inside of the trench (30) by, for example, CVD (chemical vapor deposition).

Thereafter, as shown in FIG.
), the SiO2 layer (26) and the polycrystalline silicon layer (27) are removed.

Next, as shown in FIG. 4G, in order to prevent punch-through, P is applied to the n-type and n-type regions (24) and (25), respectively.
Relatively deep ion implantation of type and n type impurities is performed, and relatively shallow ion implantation for vth adjustment is performed to form both P type and n type impurity implanted regions (34) and (35).

As mentioned above, in a general trench element isolation type semiconductor device, the P-type head region (24) and n
Each well region constituting the mold region (25) is formed, and in this case, since the trenches (30) are formed after each region (24) and (25) are formed, their alignment is necessary. A mark or target (23) is required for this purpose, and the complicated work described in FIG. 4A is required to form this.

In addition, in the case of the above method, the area of each MO3 forming part (
24) and (25), the ion implantation process for adjusting the dark value voltage vth and the ion implantation process for punch-through prevention are performed in separate processes from the ion implantation process for well formation, so the number of work steps is reduced. The problem is that there are too many.

Note that, instead of conventional trench isolation, a semiconductor device manufacturing method is widely used in which an insulating layer is formed by deep thermal oxidation and this is used as an isolation insulating layer, so-called LOGOS. In this case, as shown in FIG. 5A, for example, 540
Using an oxide mask layer (53) with a SiN layer (52) formed through the second layer (51), ion implantation is performed using this as a mask to implant impurities for forming a channel stopper and well, and then As shown in FIG. 5B, there is a method of forming an isolation insulating layer (54) by performing thermal oxidation using a mask layer (53) as a mask.

This case has the advantage that it is not necessary to form the above-mentioned target, but in this case, the implanted impurity diffusion increases due to the long thermal oxidation when forming the isolation insulating layer (54). The channel stop region formed in this way largely penetrates into the element forming area,
There is a problem in that the narrow channel effect of the MOS-FET becomes large.

On the other hand, as shown in FIG.
A conceivable method is to perform ion implantation through the isolation insulating layer (54) to form a channel stopper and to form each well region. It is necessary to perform ion implantation so as to obtain a concentration distribution that satisfies the stopper characteristics and also satisfies the characteristics of the MOS-FET forming part.
There is a problem in that it is difficult to set such ion implantation conditions and it is difficult to form with good reproducibility.

[Problems to be Solved by the Invention] The method for manufacturing a semiconductor device according to the present invention solves the above-mentioned problems, simplifies the process of forming an element isolation layer, and reliably produces a semiconductor device with desired characteristics with good reproducibility. be able to obtain it.

[Means for Solving the Problems] Process diagrams of an example of a method for manufacturing a semiconductor device according to the present invention are shown in FIGS. 1A-H.

The present invention provides a method for manufacturing a semiconductor device in which a semiconductor substrate (1) has a first conductivity type region and a second conductivity type region, each of which serves as a circuit element formation portion, and is provided with an element isolation trench. A step of forming an element isolation trench (4) in this semiconductor substrate (1) as shown in FIG.
As shown in this trench (4), insulating material (8A) is placed inside this trench (4).
Thereafter, as shown in FIG. An ion implantation process is performed to perform ion implantation.

[Effect]

As described above, according to the method for manufacturing a semiconductor device according to the present invention, after forming the element isolation trench (4) in the semiconductor substrate (1), the channel stopper layers (5) and (6) of each conductivity type are formed. , then an insulating layer (
8A) and etch-hack it to form an element isolation layer (
8), and then each conductivity type region (10) and (11
), ion implantation is performed to form a well region.
In forming the well region, a well region can be formed at a predetermined position using the trench (4) as a mark, that is, as a target. Therefore, there is no need to specially form a target for forming each well region as in the conventional case. In addition, since this well region formation is performed after trench formation, the same ion implantation mask can be used during this ion implantation process to perform ion implantation for punch-through prevention and vth adjustment, for example, reducing the number of steps. This can simplify the work.

Furthermore, since there is no long-term thermal oxidation process such as LOGO5 formation after ion implantation, it is possible to suppress the diffusion of impurities and to prevent the channel stop region from entering the element formation area, thereby suppressing the MOS-FET. Narrow channel effects can be suppressed.

Example C] Hereinafter, the manufacturing process of an example of the method for manufacturing the semiconductor device of the present invention will be explained as follows.
This will be explained in detail with reference to Figures AH.

First, as shown in FIG. 1A, a semiconductor substrate (1), for example, a Si substrate, made of a p-type or n-type high resistivity semiconductor is prepared, and an element isolation trench (4) is formed in a predetermined portion of its surface by photolithography. It is formed by RIE using. Formation of this trench (4) is carried out by thermal oxidation, for example, 5i (
After forming an insulating layer (2) made of a material such as H on the entire surface to a thickness of, for example, 1,000 layers, a polycrystalline semiconductor layer (3) to a thickness of 1,500 layers is formed thereon. Then, photoresist is applied over the entire surface, and this is exposed and developed to form a photoresist pattern. Using this photoresist pattern as a mask, the polycrystalline semiconductor layer (3) and the insulating layer [2] are formed.
Then, a trench (4) is formed on the substrate (2) to a predetermined depth, for example, 5000 mm, by anisotropic etching such as RIE.

Next, ions of P-type and n-type impurities are implanted from the inner surface of each trench (4) to form a P-channel stop region and an n-channel stop region. In this case, as shown in FIG. 1B, first, a photoresist (5R) of the second conductivity type, for example, an n-type region, is formed, and then this photoresist (5R), a polycrystalline semiconductor layer (3), and an insulating layer (2) are formed. )
A channel stopper layer (5) of a first conductivity type is formed by selectively ion-implanting an impurity of a first conductivity type, for example, p-type boron B, into the trench (4) using the same as a mask.

After that, the P-type region is covered with a photoresist in the same way, and this photoresist is combined with the polycrystalline semiconductor layer (3) and the insulating layer (2).
) as a mask, an n-type impurity such as arsenic As is selectively ion-implanted into the trench (4) to form a channel stopper layer (6) of the second conductivity type, as shown in FIG. 1C. . Then, the inside of the trench (4) is thermally oxidized to S.
After forming a thin oxide film (7) made of iO□ etc. on the entire surface, an insulating material (8A) made of 5iOz etc. is formed in the trench (4).
) is formed entirely by CV or D method, for example.

Next, as shown in the first diagram, an etch bank is performed using anisotropic RIE or the like to form an element isolation layer (8).

After that, as shown in Figure 1, after removing the polycrystalline semiconductor layer (3) and the insulating layer (2), a sacrificial oxide film (9) consisting of a thin oxide film is formed by thermal oxidation or the like on the entire surface. .

Next, as shown in FIG. 1F, first, for example, a photoresist (IOR) is formed on the n-type well formation region, and then a p-type impurity such as B is ion-implanted using the photoresist (IOR) as a mask. I do. At this time, pM
As shown in the impurity concentration distribution of O3-FET, each a −
The depth at which the peak of c is located is the first conductivity type, for example, the p-type well region (10), the ion implantation layer for punch-through prevention (IOA), and the ion implantation layer for vth adjustment (IOA).
Impurity ions are implanted by high-acceleration ion implantation with ion implantation conditions set to correspond to the depth of OB).

Next, as shown in Figure 1G, photoresist (IOR) is applied.
After removing the photoresist (IIR), a photoresist (IIR) is formed on the P-type well region (10).
Using R) as a mask, ion implantation of n-type impurities such as As is performed. At this time, as shown in FIG. 3, which shows the impurity concentration distribution of the nMO5FET, the depth at which each of the peaks of d to r is located corresponds to the second conductivity type, for example, the n-type well region (11).
, ion implantation layer (IIA) for punch-through prevention,
Impurity ions are implanted by a high acceleration ion implantation method in which ion implantation conditions are set to correspond to the depth of the vth adjustment ion implantation layer (IIB).

Thereafter, as shown in FIG. 1H, a gate oxide film (12) is formed on the entire surface by thermal oxidation, etc., and then a gate electrode (13) made of, for example, a polycrystalline Si layer is formed in a predetermined pattern in each element isolation region. Using the gate electrode (13) and element isolation layer (8) as a mask, p-p is applied at a low concentration.
A low concentration source/drain region (14) is formed by implanting type and n-type impurities, and an insulating layer made of, for example, SiO□ is formed on the entire surface and then etched back to form a side surface of the gate electrode (13). A sidewall (15) is formed on the S, and each p-type and n-type impurity is implanted at a high concentration using this sidewall (15), gate electrode (13), and element isolation layer (8) as a mask. A source/drain region (16) is formed, and a MOS with an opposite conductivity type channel is formed in each conductivity type region, so that, for example, a large number of C-MOs are formed.
A semiconductor device (18) constituting S is obtained.

In the above-mentioned example, the high resistivity semiconductor substrate, that is, S
Although the case where each conductivity type region is formed on the i-substrate (1) has been described, various other configurations are possible, such as the case where a double-door conductivity type region is formed by forming a p-type well on an n-type semiconductor substrate. The present invention can be applied to semiconductor devices according to the present invention.

[Effects of the Invention] As described above, according to the method for manufacturing a semiconductor device according to the present invention, after forming the element isolation trench (4) in the semiconductor substrate (1), each conductivity type channel stopper (5) and (
6) and then an insulating layer (8) in each trench (4).
A) is buried and etched banked to form an element isolation layer (8).
), and then each conductivity type region (10) and (11)
Since ion implantation is performed to form a well region, the well region can be formed at a predetermined position using the trench (4) as a mark, that is, as a target. Therefore, there is no need to specially form targets for forming each L region as in the prior art, and the number of steps can be reduced.

Also, since this well region is formed after trench formation,
During this ion implantation process, the same ion implantation mask can be used to perform, for example, ion implantation for bunch-through prevention and VTH adjustment, which reduces the number of steps and simplifies the work. .

In addition, since there is no long-term thermal oxidation process such as LOGO5 formation after ion implantation, it is possible to suppress the diffusion of impurities and to prevent them from entering the element forming area in the channel stomb region. The narrow channel effect can be suppressed.

Furthermore, as shown in FIG. 2, for example, a P-type well region (1
Since the p-type impurity concentration in the trench (4) is increased in the deep part, it is possible to omit the formation of the channel stopper diffusion layer at the bottom of the trench (4). The process can be further simplified.

[Brief explanation of the drawing]

Figures 1A-H are manufacturing process diagrams showing an example of the method for manufacturing a semiconductor device according to the present invention, Figure 2 shows the impurity concentration distribution of a pMO3,-FET, and Figure 3 shows the impurity concentration distribution of an nM O5FET. 4A to 4G are manufacturing process diagrams showing an example of a conventional method for manufacturing a semiconductor device, FIGS. 5A and 5B are manufacturing process diagrams showing another example of a conventional method for manufacturing a semiconductor device, and FIG. The figure is a cross-sectional view showing another example of the conventional method for manufacturing a semiconductor device. (1) is a semiconductor substrate, (2) is an insulating layer, (3) is a polycrystalline semiconductor layer, (4) is a trench, (5) and (6) are a first
conductivity type and second conductivity type channel stopper layer, (7)
is an oxide film, (8A) is an insulating material, (8) is an element isolation layer, (
9) is a sacrificial oxide film, (10) is a first conductivity type region, and (10) is a sacrificial oxide film.
4) and (IOB) are ion implantation layers, (11) are second conductivity type regions, (IIA) and (IIB) are ion implantation layers,
(IOR) and (IIR) are photoresists, (12)
is a gate oxide film, (13) is a gate electrode, (14) is a low concentration source/drain region, (15) is a side wall, (16) is a source/train region, (18) is a semiconductor device, (22) is a material layer, (23) is the target, (2
4) is a p-type head region, (25) is an n-type region, and (26) is a Si
n□ layer, (27) is polycrystalline Si layer, (28) is photoresist, (29) is window, (30) is trench, (32)
is Si02 layer, (33A) is insulating material, (33) is element isolation layer, (51) is SiO□ layer, (52) is SiN layer, (
53) is a mask layer, and (54) is an element isolation layer.

Claims (1)

[Scope of Claims] A method for manufacturing a semiconductor device in which a semiconductor substrate has a first conductivity type region and a second conductivity type region each serving as a circuit element forming portion, and is provided with an element isolation trench, forming the element isolation trench, filling the trench with an insulating material, and then forming a well region for forming the first conductivity type region and the second conductivity type region in predetermined portions. 1. A method for manufacturing a semiconductor device, comprising: an ion implantation step of implanting impurity ions.