JP2002043534A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the PN-separation-oriented withstanding voltage of a semiconductor device without increasing largely the separation width of its trench, without altering the doses of its ion implantations, and without increasing the number of its manufacturing processes. SOLUTION: In the semiconductor device, a P-well region 20 having on its surface a P+-diffusion-layer region 26 and an N-well region 12 having on its surface an N+-diffusion-layer region 25 are separated from each other by a trench oxide film 6. Also, on the sides of the P-well and N-well regions 20, 12, there are provided respectively P-type and N-type heavily doped regions 22b, 14b which are formed equally on the bottom surface of the trench oxide film 6. Further, the impurity concentrations of the P+-diffusion-layer region 26 and the P-type heavily doped region 22b are made higher than the one of the P-well region 20. Moreover, the impurity concentrations of the N+-diffusion- layer region 25 and the N-type heavily doped region 14b are made higher than the one of the N-well region 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a structure in which a P-well and an N-well are trench-isolated, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional method for fabricating a CMOS semiconductor device using trench isolation will be described with reference to sectional views shown in FIGS.

First, as shown in FIG. 12A, a silicon oxide film 2 and a silicon nitride film 3 are formed on a semiconductor substrate 1, and a silicon nitride film 3 and a silicon nitride film 3 in an element isolation region are formed by photolithography and etching. The oxide film 2 and the semiconductor substrate 1 are removed, and a trench 4 is formed. Here, the semiconductor substrate 1 needs to have a desired depth required for trench isolation. Subsequently, as shown in FIG. 12B, the surface of the semiconductor substrate 1 is oxidized, and an oxide film 5 is formed on the entire surface by chemical vapor deposition (CVD).

Subsequently, as shown in FIG. 13C, the oxide film 5 is polished by CMP using the silicon nitride film 3 as a stopper so as to leave the trench oxide film 6 in the trench groove 4. After removing the silicon oxide film 2, a silicon oxide film 2a is formed. Subsequently, as shown in FIG. 13D, a resist 7 is patterned on the semiconductor substrate 1 by photolithography to form an N-well region.

Subsequently, as shown in FIG. 14E, an N well region 12 is formed by implanting phosphorus ions 8 by ion implantation. The implantation condition of phosphorus ions 8 is 300 to
0.4 [V] from the substrate surface with high energy of 700 [keV]
1 × 10 ¹⁷ [cm ⁻³ ] to a depth of 0.8 μm
The implantation is performed so that the phosphorus concentration becomes about 3 × 10 ¹⁷ [cm ⁻³ ]. Therefore, no impurity layer is formed immediately below the substrate surface, and an impurity layer of phosphorus ions 8 is formed in a region deep from the substrate surface. Also, an impurity layer serving as the N well region 12 is formed below the trench oxide film 6 due to high energy implantation conditions. Subsequently, FIG.
As shown in (F), arsenic ions 13 for controlling Vt (threshold voltage) in the surface channel portion are 5 × 10 ¹⁷ [cm].
⁻³ ] to 1 × 10 ¹⁸ [cm ⁻³ ]. As a result, an N-type high-concentration impurity region 14 that is a high-concentration arsenic impurity layer is formed only immediately below the substrate surface. Of course, the N-type high concentration impurity region 14 is not formed below the trench oxide film 6.

Subsequently, as shown in FIG. 15G, a resist 15 is patterned by photolithography in order to form a P-well region on the semiconductor substrate 1. Subsequently, as shown in FIG. 15H, a P-well region 20 is formed by implanting boron ions 16. Boron ions 16 are in the range of 150 [keV] to 300.
With an energy of [keV], 0.4 to 0.1 mm from the substrate surface.
1 × 10 ¹⁷ [cm ⁻³ ] to 3 × at a depth of 8 [μm]
The boron is implanted so as to have a boron concentration of about 10 ¹⁷ [cm ⁻³ ]. Therefore, an impurity layer is formed by boron ions 16 in a region deep from the substrate surface without forming an impurity layer immediately below the substrate surface. Further, an impurity layer serving as the P well region 20 is also formed below the trench oxide film 6 because of the high energy implantation condition.

Subsequently, as shown in FIG. 16I, low energy boron ions 21 are implanted into the substrate surface for controlling Vt of the surface channel. The boron ion 21 is 5
The boron is implanted so as to have a boron concentration of about × 10 ¹⁷ [cm ⁻³ ] to 1 × 10 ¹⁸ [cm ⁻³ ]. Therefore, a boron impurity layer is not formed immediately below the trench oxide film 6, but is a P-concentration boron impurity layer having a high concentration only directly under the substrate surface.
Form high concentration impurity region 22 is formed. Subsequently, FIG.
As shown in (J), the photoresist is removed. Thereafter, active elements and wirings are formed by a usual method.

[0008]

However, the above-mentioned prior art has the following problems.

In recent years, in LSIs mainly equipped with SRAMs, those having a minimum trench isolation width of 0.50 [μm] or less have emerged, and it has become necessary to satisfy the criteria of the trench isolation width. On the other hand, as shown in FIG. 17, when the trench isolation width of this size is reached, the PN in the N well and the P well separated by the trench are reduced.
The separation characteristics have been significantly reduced. That is, the breakdown voltage between the N well region 12 and the P ⁺ diffusion layer region 26 in the P well and the breakdown voltage between the P well region 20 and the N ⁺ diffusion layer region 25 in the N well cannot be said to be sufficient. The characteristics deteriorate. As a result, the occurrence of inter-element leakage current has reduced the yield and prevented improvement in reliability.

In order to prevent such a problem from occurring, it is conceivable to change the ion implantation dose, for example, by changing the well dose or the Vt control dose for the purpose of improving the isolation characteristics. However, if the dose of the ion implantation is changed, another problem arises that the Tr characteristics and device characteristics change. Another problem arises in that increasing the trench isolation width increases the chip area.

[0011]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device capable of improving the PN isolation breakdown voltage without increasing the trench isolation width, changing the ion implantation dose, and increasing the number of steps. It is to provide a manufacturing method thereof.

[0012]

In a semiconductor device according to the present invention, a P-well having a first P-type impurity layer on its surface and an N-well having a first N-type impurity layer on its surface are formed by a trench insulating film. Separated from the bottom surface of the trench insulating film.
A second P-type impurity layer is provided on the well side, a second N-type impurity layer is provided on the N-well side of the bottom surface of the trench insulating film, and the impurity concentration of the first and second P-type impurity layers is P
Higher than the well, and the impurity concentration of the first and second N-type impurity layers is higher than that of the N well.
Further, the first P-type impurity layer and the first N-type impurity layer
The threshold voltage of the transistor may be set according to the respective impurity concentrations. Further, P
An n-channel MOS transistor is formed in the well,
A p-channel MOS transistor may be formed in the N-well.

From the first P-type impurity layer on the P-well surface, N
The second P-type impurity layer formed on the bottom surface of the trench insulating film acts as a barrier for the holes that are going to flow into the well. On the other hand, the second N-type impurity layer formed on the bottom surface of the trench insulating film serves as a barrier for electrons flowing from the first N-type impurity layer on the N-well surface to the P-well. In other words, it can be said that the trench insulating film is deepened by the thickness of the second P-type impurity layer and the second N-type impurity layer. Therefore, without increasing the trench isolation width and without changing the ion implantation dose. The PN separation withstand voltage is improved.

A manufacturing method according to the present invention is a method for manufacturing a semiconductor device according to the present invention, and includes the following steps. Forming a trench on the semiconductor substrate; A step of patterning a first resist on one of the two divided bottom surfaces of the trench groove and on the semiconductor substrate around the one; By performing ion implantation using the first resist as a mask, a first well of the first conductivity type is formed on the other half of the trench having the bottom surface and the semiconductor substrate around the other half. Process. By performing ion implantation using the first resist as a mask, a first impurity layer of a first conductivity type having a higher impurity concentration than the first well is formed on the surface of the first well and the bottom of the trench groove. Forming a. Removing the first resist; Patterning a second resist on the other half of the bottom of the trench groove and the semiconductor substrate around the other half; By performing ion implantation using the second resist as a mask, the bottom surface of the trench is divided into two portions and the semiconductor substrate around the one of the two portions is provided with a second conductive type opposite to the first conductive type. Forming a second well having the conductivity type of By performing ion implantation using the second resist as a mask, a second impurity layer of a second conductivity type having a higher impurity concentration than the second well is formed on the surface of the second well and the bottom of the trench. Forming a. Removing the second resist; Forming a trench isolation region by burying an insulating film in the trench. Further, the first and second impurity layers formed on the semiconductor substrate around the trench groove are for setting a threshold voltage of the transistor according to the respective impurity concentrations.
It may be.

By performing ion implantation using the first resist as a mask, a first impurity layer is formed on the surface of the first well and the bottom of the trench. Here, if the first conductivity type is P-type, the first P-type impurity layer on the surface of the P-well and the second P-type impurity layer on the bottom surface of the trench can be simultaneously formed in the semiconductor device according to the present invention. Similarly, by performing ion implantation using the second resist as a mask,
A second impurity layer is formed on the surface of the second well and the bottom of the trench. Here, if the second conductivity type is N-type, the first N-type surface of the N-well in the semiconductor device according to the present invention will be described.
The impurity layer and the second N-type impurity layer on the bottom of the trench can be simultaneously formed. Therefore, when forming the existing first P-type impurity layer and first N-type impurity layer, a new second P-type impurity layer and a second N-type impurity layer can be formed, so that the number of steps is increased. do not do.

Furthermore, the threshold voltage is further increased by further performing ion implantation of the opposite conductivity type to the first and second impurity layers into the first and second impurity layers formed on the semiconductor substrate around the trench groove. May be provided. In this case, the impurity concentrations of the first and second impurity layers can be reduced without changing the impurity concentrations of the first and second impurity layers on the bottom surface of the trench groove, that is, while improving the PN isolation breakdown voltage.

In other words, in the present invention, a step of etching a substrate surface to form a trench isolation region, a step of patterning a resist so as to separate a trench bottom to form a well region, The method includes a step of implanting ions for formation, a step of implanting ions for Vt control, and a step of burying an oxide film in a trench.

[0018]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention. Hereinafter, description will be made based on this drawing. However, the first P-type impurity layer, the P-well, the first N-type impurity layer, the N-well, the trench insulating film, the second P-type impurity layer, and the second N-type impurity layer according to Claims 1 to 3 Are specifically referred to as a P ⁺ diffusion layer region, a P well region, an N ⁺ diffusion layer region, an N well region, a trench oxide film, a P-type high concentration impurity region, and an N-type high concentration impurity region, respectively.

The semiconductor device of the present embodiment is a CMOS semiconductor device using trench isolation, and has a P well region 20 having a P ⁺ diffusion layer region 26 on its surface and an N well having an N ⁺ diffusion layer region 25 on its surface. Region 12 is separated by trench oxide film 6, a P-type high-concentration impurity region 22 b is provided on the bottom of trench insulating film 6 on the side of P-well region 20, and N-type is formed on the bottom of trench oxide film 6 on the side of N-well region 12.
High concentration impurity region 14b is provided, and the impurity concentration of P ⁺ diffusion layer region 26 and P type high concentration impurity region 22b is
N ⁺ diffusion layer region 25 and N ⁺
The impurity concentration of the high-concentration impurity region 14 b is higher than that of the N-well region 12.

The P ⁺ diffusion layer region 26 and the N ⁺ diffusion layer region 25 are for setting the threshold voltage of the transistor according to the respective impurity concentrations. Further, an n-channel MOS transistor (not shown) is formed in P-well region 20, and a p-channel MOS transistor is formed in N-well region 12.
An OS transistor (not shown) is formed.

P ⁺ diffusion layer region 2 on the surface of P well region 20
The P-type high-concentration impurity region 22b formed on the bottom surface of the trench oxide film 6 serves as a barrier for holes that are to flow from the N-type well 6 to the N-well region 12. On the other hand, the N well region 12
The N-type high-concentration impurity region 14b formed on the bottom surface of the trench oxide film 6 serves as a barrier against electrons flowing from the surface N ⁺ diffusion layer region 25 to the P well region 20. In other words, it can be said that the trench oxide film 6 is deepened by the thickness of the P-type high-concentration impurity region 22b and the N-type high-concentration impurity region 14b, so that the trench isolation width is not increased.
In addition, the PN isolation breakdown voltage is improved without changing the ion implantation dose.

2 to 5 are sectional views showing a first embodiment of the manufacturing method according to the present invention. Hereinafter, description will be made based on these drawings. The manufacturing method according to the present embodiment is a method for manufacturing the semiconductor device according to the first embodiment. However, the first conductivity type, the first well, the first impurity layer, the second conductivity type, the second well, and the second impurity layer according to claims 4 to 6 are P-type and P-well regions. , P-type high-concentration impurity regions, N-type and N-well regions, and N-type high-concentration impurity regions.

First, as shown in FIG. 2A, a silicon oxide film 2 and a silicon nitride film 3 are formed on a semiconductor substrate 1 to a thickness of 10 nm and 150 nm, respectively. By removing the silicon nitride film 3, the silicon oxide film 2 and the substrate surface in the element isolation region by the etching technique, the trench groove 4 is formed at 350 [n].
m]. Subsequently, as shown in FIG. 2B, the silicon nitride film 3 is removed, and the resist 7 is patterned by photolithography to form an N-well region on the semiconductor substrate 1. At this time, N
Since the well region and the P well region are separated from each other at the lower portion of the trench, patterning is performed so that the bottom of the trench groove 4 is separated by the resist. Subsequently, FIG.
As shown in (C), phosphorus ions 8 were obtained by ion implantation.
Is implanted to form an N well region 12. At this time, the implantation conditions of the phosphorus ions 8 are, for example, 300 keV to 7 keV.
With a high energy of 00 [keV], 0.4 to 0.8 [μ
m] at a depth of 1 × 10 ¹⁷ [cm ⁻³ ] to 3 × 10
^It is implanted so as to have a phosphorus concentration of about ¹⁷ [cm ⁻³ ]. The impurity layer of phosphorus ions is formed in a region deep from the silicon substrate toward the back surface. The impurity layer of phosphorus ions is an impurity layer formed below the element forming portion and the bottom of the trench groove 4, and the impurity layer formed below the bottom of the trench groove 4 is formed in the element forming portion. It is formed deeper than the impurity layer by the depth of the trench.

Subsequently, as shown in FIG. 3D, 5 × 10 ¹⁷ arsenic ions 13 are used for controlling Vt in the surface channel.
By implanting so as to have a concentration of about [cm ⁻³ ] to 1 × 10 ¹⁸ [cm ⁻³ ], an N-type impurity region, which is a high-concentration impurity region of arsenic ions 13, is provided directly below the substrate surface 1 and directly below the bottom of the trench 4. The high concentration impurity regions 14a and 14b are formed. The N-type high-concentration impurity diffusion layers 14a and 14b are implanted in the same pattern as the above-described N well region 12, but are implanted immediately below the substrate surface and immediately below the trench bottom, respectively, without being implanted deep into the substrate. Is done. This allows
Immediately below the trench 4, an N-type impurity region (N-type high-concentration impurity region 14) having a higher concentration than the impurity layer formed by the phosphorus ions 8 implanted to form the N-well region 12.
b) can be formed. Subsequently, as shown in FIG. 3E, after removing the resist, the resist 15 is patterned by lithography to form a P-well region on the semiconductor substrate 1. At this time, as in the case of patterning the N-well region, the N-well region and the P-well region are separated at the lower part of the trench, so that the resist is patterned so as to separate the bottom of the trench.

Subsequently, as shown in FIG. 4F, boron ions 16 are implanted to form a P-well region 20. At this time, the implantation condition of the boron ions 16 is, for example, 150
Under an energy condition of ~ 300 [keV], 0.4 ~ 0.
1 × 10 ¹⁷ [cm ⁻³ ] to 3 × at a depth of 8 [μm]
The boron is implanted so as to have a boron concentration of about 10 ¹⁷ [cm ⁻³ ]. The impurity layer of boron ions 16 is formed in a region deeper from the front surface to the back surface of the substrate. Further, the impurity layer of boron ions is an impurity layer formed below the element forming portion and the bottom of the trench groove 4, and the impurity layer formed below the bottom of the trench groove 4 is formed in the element forming portion. Formed by the depth of the trench. Subsequently, as shown in FIG. 4 (G), low energy boron ions 21 for controlling Vt in the surface channel portion.
From 5 × 10 ¹⁷ [cm ⁻³ ] to 1 × 10 ¹⁸ [c
m ⁻³ ], and the semiconductor substrate 1
Boron ions 2 just below the surface and directly below the bottom of the trench 4
1 to form P-type high-concentration impurity regions 22a and 22b, which are high-concentration impurity regions. P type high concentration impurity region 22
a and 22b are implanted in the same pattern as the resist pattern for forming the P well region 20 described above, but are not implanted deep into the semiconductor substrate 1 because of the low energy implantation condition. They are respectively implanted just below the substrate surface and just below the trench bottom. Thus, a P-type impurity region (P-type high-concentration impurity region 22b) having a higher concentration than the impurity layer formed by the boron ions 16 implanted to form the P-well region 20 is formed immediately below the trench 4. can do.

Subsequently, as shown in FIG. 5H, after removing the resist 14, an oxide film 5 is formed on the entire surface of the semiconductor substrate 1 by a chemical vapor deposition method (CVD method). Subsequently, the oxide film 5 is polished by CMP so as to form a trench oxide film 6 in the trench 4 as shown in FIG. Subsequently, the silicon oxide film 2 is removed and the oxide film 2 is removed.
a is formed on the entire surface. Thereafter, an active element such as a gate element and a wiring are formed by a usual method.

In this embodiment, as shown in FIG.
In addition, arsenic ions and boron for Vt control are located just below the trench bottom.
Ions are implanted, and the N-type high-concentration impurity regions 14b and P
Formed high-concentration impurity regions 22b are formed. At this time,
As shown in FIG. 2, arsenic ions and boron ions for Vt control are used.
The impurity concentration of ON is determined by the phosphorus concentration in the N well region or the P well.
Higher than the boron concentration in the region,
The pure concentration can be set higher than in the prior art. Therefore,
As shown in FIG. 1, N well region 12 and P
⁺Breakdown voltage between diffusion layer region 26 and P well region 20
And N in N-well ⁺Improves breakdown voltage between diffusion layer region 25
Therefore, leakage current can be reduced.

7 to 11 are sectional views showing a second embodiment of the manufacturing method according to the present invention. Hereinafter, description will be made based on these drawings. This embodiment shows a method for manufacturing a CMOS semiconductor device in which a transistor having a low impurity concentration on the substrate surface and a transistor having a high impurity concentration on the substrate surface are mixed. In the present embodiment,
Unless otherwise described, conditions for ion implantation are the same as those described in the first embodiment.

The steps from FIG. 7A to FIG. 9F in this embodiment are the same as those in the first embodiment. In this embodiment, as shown in FIG. 10G and thereafter, in order to form a transistor having a low surface impurity concentration, the N-type high-concentration impurity region 14a and the P-type high-concentration impurity region 22a formed on the substrate surface are formed. And ion implantation of the opposite conductivity type is performed.

First, as shown in FIG. 10G, in order to form a transistor having a low surface impurity concentration on the P well region, a resist 7 is formed by photolithography.
b is patterned. Subsequently, arsenic ions 13a are implanted into the P-type high-concentration impurity region 22a by an ion implantation method, and a second P-type high-concentration impurity region 22c is formed on the substrate surface on the P-well region. The arsenic ions 13a are ions of the opposite conductivity type to the ionic impurities in the P-type high-concentration impurity region 22a. Therefore, the P-type high-concentration impurity region 22c has a lower P-type impurity concentration than the P-type high-concentration impurity region 22a. Subsequently, after the resist is stripped, FIG.
As shown in (H), in order to form a transistor having a low surface impurity concentration on the N-well region, the resist 15b is patterned by a photolithography technique.
Subsequently, boron ions 21a are implanted into the N-type high concentration impurity region 14a by an ion implantation method. Boron ion 21
By implantation of a, a second N-type high-concentration impurity region 14c is formed on the substrate surface above the N-well region. Boron ion 2
1a is an ion of the opposite conductivity type to the ionic impurities in the N-type high concentration impurity region 14a. Therefore, the second N
N-type high-concentration impurity region 14c
N-type impurity concentration is lower than 4a.

Subsequently, as shown in FIG. 11I, the resist 15b is removed. Thereafter, an active element such as a gate element and a wiring are formed by a usual method.

In the present embodiment, FIGS.
As shown in (H), the second P-type high concentration impurity diffusion layer 22 is formed.
c and surface impurities of the second N-type high concentration impurity diffusion layer 14c
This is the case when the concentration is low. For example, a train in the N-well area
N-type impurity diffusion layer with low surface impurity concentration
When formed, N in the N well⁺Diffusion layer area and P-well area
The withstand voltage between these regions is reduced. In the present embodiment, N
N-type impurity region formed on the substrate surface in the well region
Only implant ions of the opposite conductivity type (boron ions).
Thus, an N-type impurity region having a low surface impurity concentration can be formed.
You. P in P well ⁺Between the diffusion layer region and the N-well region
The same applies to the breakdown voltage of the substrate.
Ion of opposite conductivity type only in P-type impurity region formed on surface
(Arsenic ions) to lower the surface impurity concentration
P-type impurity regions can be formed. Therefore, surface impure
Transistor with high impurity concentration and transistor with low surface impurity concentration
With the transistor, without lowering the separation withstand voltage
Can be mixed.

[0033]

According to the semiconductor device of the present invention, the P-well having the first P-type impurity layer on the surface and the N-well having the first N-type impurity layer on the surface are separated by the trench insulating film. The second P-type impurity layer is provided on the P-well side of the bottom surface of the trench insulating film, and the second N-type impurity layer is provided on the N-well side of the bottom surface of the trench insulating film. PN separation voltage can be improved without increasing the ion implantation dose and without changing the ion implantation dose. The reason for this is that the second P-type impurity layer formed on the bottom surface of the trench insulating film acts as a barrier for holes that are going to flow from the first P-type impurity layer on the P-well surface to the N-well, The second N-type impurity layer formed on the bottom surface of the trench insulating film acts as a barrier against electrons flowing from the first N-type impurity layer on the surface to the P-well, thereby forming a second P-type impurity layer. This is because it can be said that the trench insulating film is deepened by the thickness of the second N-type impurity layer.

In other words, an N-type high-concentration impurity region is formed immediately below the trench bottom in the N-well region, and a P-type high-concentration impurity region is formed immediately below the trench bottom in the P-well region. For this reason, the separation withstand voltage between the P well region and the N ⁺ diffusion layer region in the N well, and the P breakdown voltage in the N well region and the P well
^This has the effect of improving the withstand voltage for separation from the ⁺ diffusion layer region. Therefore, the breakdown voltage between the N well region and the N ⁺ diffusion layer region in the P well and the breakdown voltage between the P well region and the P ⁺ diffusion layer region in the N well can be maintained. And a reliable semiconductor device can be provided.

According to the manufacturing method of the present invention, the first impurity layer is formed on the surface of the first well and the bottom of the trench by using the first resist as a mask, and the second impurity is formed by using the second resist as a mask. Forming the second impurity layer on the well surface and the bottom surface of the trench groove, the first P-type impurity layer on the P-well surface and the second P-type impurity layer on the trench groove bottom surface can be formed simultaneously, A first N-type impurity layer on the surface of the N-well and a second N-type impurity layer on the bottom surface of the trench;
Since it can be formed simultaneously with the mold impurity layer, the PN isolation breakdown voltage can be improved without increasing the number of steps.

In addition, by implanting opposite conductivity type ions into the first and second impurity layers formed on the semiconductor substrate around the trench groove, the first and second impurity layers on the bottom surface of the trench groove are implanted. The impurity concentration of the first and second impurity layers can be reduced without changing the impurity concentration, that is, while improving the PN isolation breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a first embodiment of a manufacturing method according to the present invention, and the process proceeds in the order of FIGS. 2 (A) to 2 (C).

FIG. 3 is a cross-sectional view showing a first embodiment of a manufacturing method according to the present invention, and the process proceeds in the order of FIGS. 3 (D) to 3 (E).

FIG. 4 is a cross-sectional view showing the first embodiment of the manufacturing method according to the present invention, and the process proceeds in the order of FIGS. 4 (F) to 4 (G).

FIG. 5 is a cross-sectional view showing a first embodiment of a manufacturing method according to the present invention, and the process proceeds in the order of FIGS. 5 (H) to 5 (I).

FIG. 6 is a graph showing an impurity profile below a trench in the semiconductor device of the first embodiment.

FIG. 7 is a cross-sectional view showing a second embodiment of the manufacturing method according to the present invention, and the process proceeds in the order of FIGS. 7 (A) and 7 (B).

FIG. 8 is a cross-sectional view illustrating a second embodiment of the manufacturing method according to the present invention, and the process proceeds in the order of FIGS. 8 (C) to 8 (D).

FIG. 9 is a cross-sectional view illustrating a second embodiment of the manufacturing method according to the present invention, and the process proceeds in the order of FIGS. 9 (E) to 9 (F).

FIG. 10 is a cross-sectional view showing a second embodiment of the manufacturing method according to the present invention, and the process proceeds in the order of FIGS. 10 (G) to 10 (H).

FIG. 11 is a sectional view showing a second embodiment of the manufacturing method according to the present invention.

FIG. 12 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device, and the process proceeds in the order of FIGS.

FIG. 13 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device, and the process proceeds in the order of FIGS. 13 (C) to 13 (D).

FIG. 14 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device, and the process proceeds in the order of FIGS. 14 (E) to 14 (F).

FIG. 15 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device, and the process proceeds in the order of FIGS. 15 (G) to 15 (H).

FIG. 16 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device, and the process proceeds in the order of FIGS. 16 (I) to 16 (J).

FIG. 17 is a cross-sectional view showing a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2, 2a silicon oxide film 3 silicon nitride film 4 trench groove 5 oxide film 6 trench oxide film 7, 7a, 7b resist 8 phosphorus ion 12 N well region 13, 13a arsenic ion 14, 14a, 14b, 14c N type high Concentration impurity region 15, 15a, 15b Resist 16 Boron ion 20 P well region 21, 21a Boron ion 22, 22a, 22b, 22c P-type high concentration impurity region 25 N ⁺ diffusion layer region 26 P ⁺ diffusion layer region

Claims (6)

[Claims] An N-well having a first P-type impurity layer on a surface thereof and an N-well having a first N-type impurity layer on a surface thereof are separated by a trench insulating film; The second P on the well side
A second N-type impurity layer is provided on the bottom surface of the trench insulating film on the N-well side, and the first and second P-type impurity layers have an impurity concentration of the P-type impurity layer.
A semiconductor device, wherein the impurity concentration of the first and second N-type impurity layers is higher than that of the well and higher than that of the N well. 2. The semiconductor device according to claim 1, wherein said first P-type impurity layer and said first N-type impurity layer are for setting a threshold voltage of a transistor according to respective impurity concentrations. . 3. An n-channel MOS transistor is formed in the P well, and a p-channel MOS transistor is formed in the N well.
3. The semiconductor device according to claim 2, wherein an S transistor is formed. 4. A step of forming a trench on the semiconductor substrate, and a step of patterning a first resist on one of the two divided bottom surfaces of the trench and on the semiconductor substrate around the other of the two. By performing ion implantation using the first resist as a mask, a first conductive type of the first conductivity type is formed on the other half of the bottom surface of the trench groove and on the semiconductor substrate around the other half. Forming a well, and performing ion implantation using the first resist as a mask, so that the surface of the first well and the bottom of the trench have a higher impurity concentration than the first well. Forming a first impurity layer of one conductivity type; removing the first resist; dividing the bottom surface of the trench groove into two parts; A step of patterning a second resist on the body substrate, and performing ion implantation using the second resist as a mask, thereby dividing the bottom surface of the trench groove into two parts and the semiconductor around the one part. Forming a second well of a second conductivity type opposite to the first conductivity type on the substrate, and performing ion implantation using the second resist as a mask, thereby forming the second well. Forming a second impurity layer of the second conductivity type having a higher impurity concentration than the second well on the surface of the well and the bottom surface of the trench, and removing the second resist. A method of manufacturing a semiconductor device, comprising: a step of forming a trench element isolation region by burying an insulating film in the trench. 5. The first and second impurity layers formed on the semiconductor substrate around the trench groove are for setting a threshold voltage of a transistor according to respective impurity concentrations. Item 5. The method for manufacturing a semiconductor device according to Item 4. 6. The method according to claim 1, further comprising performing ion implantation of a conductivity type opposite to that of the first and second impurity layers into the first and second impurity layers formed on the semiconductor substrate around the trench groove. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of setting the threshold voltage according to the following.