JPH02308557A - Resin sealed semiconductor device - Google Patents

Abstract

PURPOSE:To prevent sealed resin from being exfoliated and microcracks from being produced on the sealed for improvement of reliability by providing silane resin on a surface where a semiconductor chip and the sealed resin are directly bonded. CONSTITUTION:A semiconductor chip 1 is fixed to a frame 2 and is directly connected to a lead wire 7 through a bonding wire 3. A polyimide film 5 is formed on the chip 1 to moderate internal stress in the resin 4, and a region of the polyimide film 5 which is cut away dicing permits the chip 1 to be exposed therethrough as it is. The bonding strength of a portion where the chip 1 and the resin 4 are directly brought into contact is improved by at least using silane resin 6. Thus, the resin film 6 can moderate exfoliation of the resin at four corners of the resin where concentrated the most, and for reducing the deformation of wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device with improved reliability.

[Conventional technology]

A semiconductor device in which a semiconductor element is molded is assembled by first fixing the semiconductor element to a frame, and then wiring wires to corresponding lead portions. Then, it is molded and sealed with epoxy resin or the like by a transfer molding method or the like.

In semiconductor devices where semiconductor chips are sealed with resin,
In the semiconductor chip and the sealing resin in which it is embedded, defects due to stress may occur in a portion corresponding to the periphery of the semiconductor chip, which may impede the operation of the semiconductor device. The above-mentioned stress is caused by the difference in thermal expansion coefficient between the semiconductor chip and the encapsulating resin, curing shrinkage of the encapsulating resin, and the like, and tends to increase as the area approaches the periphery. Conventionally, a device as described in Japanese Patent Publication No. 61-171156 has been proposed. FIG. 6 shows the conventional device, in which a semiconductor chip 1 fixed to a frame 2 is electrically connected to lead wires via bonding wires 3, and is embedded in a sealing resin. here,
In order to prevent stress concentration in the area corresponding to the periphery of the semiconductor chip, a dicing groove was formed in the area corresponding to the periphery of the chip, and the buffer film 10 was provided thereon. That is, the purpose of the prior art is to prevent the internal stress of the sealing resin from concentrating on a portion corresponding to the periphery of the semiconductor chip by providing the buffer film 10 to relieve stress;
A highly reliable resin-sealed semiconductor device was obtained.

In addition, in semiconductor devices in which semiconductor chips are sealed with resin,
Moisture adsorbed by the sealing resin expands due to heating during reflow, and cracks occur.

Conventionally, a device as described in Japanese Patent Publication No. 61-184856 has been proposed. FIG. 5 shows the above conventional device, in which a semiconductor chip 10 is fixed to a lead frame 20 and embedded in a sealing resin 30. In addition, FIG. 6 shows an enlarged view of the part surrounded by the broken line in FIG. An inclined portion 100 was provided at the upper end portion of the device forming surface 70, that is, at an approximately right angle edge of the element forming surface 70. In the right half of FIG. 5, illustrations of bottles, bonding wires, etc. are omitted. The main purpose of the above-mentioned prior art is to prevent the stress generated by heating during reflow from concentrating on the edge portion of the element forming surface of the semiconductor chip, and to limit the occurrence of cracks.

[Problem to be solved by the invention]

The above-mentioned conventional technology requires easy bonding between the semiconductor chip and the buffer film, and heat? # No consideration is given to the stress generated during the impact test. For example, when dicing is performed on a buffer film, the adhesion between the semiconductor chip and the buffer film deteriorates, resulting in peeling at the four corners of the semiconductor chip where stress is most concentrated. There is a problem in that there is no sufficient countermeasure against the deformation and damage of the wiring caused by the above-mentioned peeling. Also, semiconductor chips (dicing surface, etc.)
No consideration was given to the adhesion between the wire and the sealing resin, and similarly to the above, no measures were taken against deformation or damage to the wiring. Furthermore, it is not sufficiently effective in solving the problem that stress due to the difference in thermal expansion coefficient between the semiconductor chip and the sealing resin is concentrated at the four corners of the semiconductor chip during a thermal shock test. In other words, it is not enough to simply tilt the edges of the conventional semiconductor chip; stress concentrates on the four corners of the semiconductor chip, causing cracks (micro-cracks) in the encapsulation resin and cracks between the semiconductor chip and the encapsulation resin. Causes peeling etc. The cracks and peeling mentioned above are the cause.

There was a problem in that the wiring inside the semiconductor chip was deformed or damaged.

The purpose of the present invention is to improve the structure of the peripheral part of the semiconductor, further improve the adhesive force between the semiconductor chip and the sealing resin, and eliminate stress concentration at the four corners of the chip, thereby preventing peeling of the sealing resin. An object of the present invention is to obtain a highly reliable semiconductor device that prevents the occurrence of microcracks and reduces wiring deformation and damage within a semiconductor chip.

[Means for solving the problem] The above purpose is to remove the buffer film on the guideline part, provide an area for cutting by dicing method, and at least place the semiconductor chip and the sealing resin on the surface where the semiconductor chip and the sealing resin are directly bonded. This can be achieved by providing a silane-based resin that improves the adhesion with the encapsulating resin, and by making the dicing surface and element forming surface of at least four corners of the semiconductor chip sloped or rounded. be done.

In the present invention, the above-mentioned guideline part is not necessary, and the semiconductor chip surface is not flat, but the dancing surface of the chip having an inclination and roundness may be 'IX' not only at the chip corner but also at all the dancing surfaces around the chip. The closer it is to 45@ with respect to the dancing surface, the better, and the larger the radius of the roundness, the better.

[Effect]

When a semiconductor chip is encapsulated with resin, the stress caused by the shrinkage of the encapsulation resin on the semiconductor chip and the stress caused by the shrinkage of the encapsulation resin outside the semiconductor chip attract each other.
At this time, it is thought that the stress that causes the sealing resin on the semiconductor chip to shrink is concentrated at the four corners of the chip farthest from the center of the semiconductor chip, causing cracks or peeling. In other words, peeling occurs at the interface between the buffer film and the semiconductor chip, or between the sealing resin and the semiconductor chip, and cracks (microcracks) occur in the sealing resin.
occurs. This peeling and cracking causes a problem in that the wiring within the semiconductor chip is deformed and damaged. Therefore, by improving the adhesive force between the buffer film or sealing resin at the corner of the chip and the semiconductor chip interface,
Peeling at the four corners of the semiconductor chip can be reduced,
Furthermore, by polishing and slanting the dancing surface and the element forming surface of the chip corners, the stress at the four corners of the semiconductor chip is dispersed around the chip, and microcracks at the corners can be prevented. Deformation and damage to the wiring can be suppressed. The adhesive force between the sealing resin and the semiconductor chip interface is preferably 150 g/aJ or more when measured using a peeling method, and if it is less than 150 g/cd, it may peel off at the corner of the semiconductor chip. may occur. Therefore, in order to increase reliability, the above adhesive strength must be 200g/c.
It is more preferable that it is m2 or more.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

A sectional view of a resin-sealed semiconductor device according to a first embodiment of the present invention is shown in FIG. 1, and FIG. 2 is an enlarged view of the broken line area shown in FIG. , is electrically connected to the lead wire 7 via the bonding wire 3, and is embedded in the sealing resin 4. It is placed on the semiconductor chip 1 to relieve the internal stress of the sealing resin 4.

A polyimide film 5 is formed. However, in the area cut by dicing, the semiconductor chip 1 is exposed as it is. At least the silane resin 6 is used in the portion where the semiconductor chip 1 and the sealing tree IM4 are in direct contact to improve adhesiveness. After connecting the bonding wires 3, the silane-based resin film 6 is sprayed with a silane-based coupling agent on the entire semiconductor chip 1, frame 2, etc., and excess silane-based coupling agent is removed by pressurized air, nitrogen, etc. After removing the coupling agent, heat treatment was performed in air or oxygen atmosphere. However, the silane resin film 6 is formed very thin. In the present invention, N-β(aminoethyl)γ-aminopropylmethyldimethoxysilane was used as the silane coupling agent, but other silane coupling agents include N-β(
(aminoethyl) γ-aminopropyltrimethoxysilane, β-(3,4 epoxycyclohexyl)ethyltrimethoxysilane, γ-glycidoxypropylmethoxysilane, rudiethoxysilane, γ-methacryloxypropyltrimethoxysilane, γ-chloropropyltrimethoxysilane, γ-
Other resins such as mercaptopropyltrimethoxysilane and γ-aminopropyltriethoxysilane may also be used.

Figure 3 shows the effect of this embodiment. This figure shows the wiring deformation at the four corners of the semiconductor chip in comparison with the conventional method.As can be seen from the figure, the amount of deformation is greater than that in the conventional method was able to be reduced to about 1/2.

According to this embodiment, by providing the silane resin film 6 on the upper surface of the semiconductor chip 1 between the semiconductor chip 1 and the sealing resin film 4, the internal stress of the sealing resin 4 is concentrated the most. Peeling at the four corners of the semiconductor chip could be reduced, and the amount of deformation of the wiring could be reduced. Although a silane-based coupling agent was used in this example, the effect of the present invention can also be obtained by using an aluminum alcoholate-based coupling agent that improves the adhesion between the semiconductor chip 1 and the sealing resin 4. It goes without saying that you can get it.

4 and 5 are diagrams showing a second embodiment and a third embodiment of the present invention. In the second embodiment shown in FIG. 4, after the dicing process, at least the edge portions of the dicing surface at the four corners of the semiconductor chip After providing a slope, a silane resin film 6 is formed in the same manner as in the first embodiment. By this embodiment, the internal stress acting on the surface of the semiconductor chip is dispersed, and the stress at the four corners of the semiconductor chip is reduced. However, this embodiment is more effective in reducing wiring deformation than the above embodiments. Furthermore, in the third embodiment shown in FIG. 5, the semiconductor chip, frame, bonding wires, lead parts, etc. are wrapped with silane resin and further covered with polyimide resin for resin sealing. As in the example, the adhesiveness between the semiconductor chip and the sealing resin is improved, cracking and peeling can be prevented, and deformation of the wiring can be reduced. In this example, the chip etc. were covered with a polyimide film, but they may also be covered with a silicone resin.Also, as a result of measuring the peeling strength of the above coupling agents, it was found that none of the coupling agents had a
Above 0 g/cm2, the silane-based power was measured by Saiki et al.
The famous Journal of the Electrochemical Society, Volume 129.

No. 10, pp. 2278-2282 (Oct. 19
The method described in 82) was used.

A fourth embodiment of the present invention will be described with reference to FIG.

A semiconductor chip 1 fixed to a lead frame 2 is embedded in a sealing resin 4. Further, 10 indicates a pin. Here, in the right half of FIG. 6, pins, bonding wires, etc. are omitted from illustration.

FIG. 7 shows an enlarged view of the part indicated by the broken line in FIG.
Polyimide w1 is placed on top of the semiconductor chip l for stress relief.
50 was formed using an applicator. After that, polishing is performed to reduce stress by 500 mm from the dicing surface 60 and the chip corner.
A stress dispersion slope 80 was formed on the element forming surface 70 within μm. The effect of the present invention is shown in FIG. 8, which shows the amount of wiring deformation at the four corners of the semiconductor chip 1 in comparison with the conventional method.

As can be seen from FIG. 8, the amount of deformation of the wiring could be reduced to about 1/2 compared to the conventional method. That is, it is shown that there is an effect of suppressing the peeling of the sealing resin 4 at the four corners of the semiconductor chip and the occurrence of microcracks. Note that in the semiconductor device described above, the effects of the present invention can be further improved by applying a silane-based resin that improves the adhesiveness between the sealing resin and the semiconductor chip before resin sealing.

FIG. 9 shows a fifth embodiment of the present invention. Deformation of wiring can also be reduced by providing stress dispersion roundness 9o by polishing or the like on the dicing surface 60 and element forming surface 70 at the four corners of the semiconductor chip. .

The above effects were obtained. Further, in the above semiconductor device, the effects of the present invention can be further improved by applying a silane-based resin before resin sealing to improve the adhesiveness between the sealing resin and the semiconductor chip.

〔Effect of the invention〕

As described above, the resin-sealed semiconductor device according to the present invention is a semiconductor device in which a semiconductor chip is molded and sealed with a resin material, and has an adhesive force of 150 g expressed as a beading strength on at least a layer around the semiconductor chip. By providing a coating layer with a thickness of /aJ or more or by providing slopes at the four corners of the semiconductor chip, peeling at the interface between the sealing resin and the semiconductor chip can be reduced, and deformation of the wiring can be reduced.
The reliability of the 411 fat-sealed semiconductor device can be improved. Note that since the silane-based coating layer is a very thin layer, it does not cause any electrical problems even if it is covered with lead wires and the like.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a first embodiment of the resin-sealed semiconductor device of the present invention, FIG. 2 is a partial sectional view of the above embodiment, FIG. 3 is a diagram showing the effects of the above embodiment, and FIG. The figure shows a second embodiment of the invention, FIG. 5 shows a third embodiment of the invention,
FIG. 6 is a diagram showing a fourth embodiment of the present invention, FIG. 7 is a partially enlarged view of the above embodiment, FIG. 8 is a diagram showing the effect of the above embodiment, and FIG. 9 is a fifth embodiment of the present invention. FIG. 10 is a sectional view of a conventional semiconductor device, FIG. 11 is a diagram showing another example of the conventional semiconductor device, and FIG. 12 is a partially enlarged view of the conventional example. 1.10... Semiconductor chip, 2, 20... Frame, 3... Bonding wire, 4, 30... Sealing resin, 5... Polyimide film, 6... Silane resin, 7
...Leader 1 Figure ￥J 3 Ensen 91 Ryōkera's Y Giant Candle Plan (nuL) flノ
7 Lee Y Hidetsuhi Figure 4 Figure 6 Cause Tomi Figure 7 Ina 8 Figure q Kuchi Tomi Figure 10

Claims (1)

[Claims] 1. In a resin-sealed semiconductor device in which a semiconductor chip is molded and sealed with a resin material, the adhesion strength expressed as peeling strength on at least a layer around the semiconductor chip is 150 g/cm^2. A resin-sealed semiconductor device characterized by being provided with one of the above coating layers. 2. The resin-sealed semiconductor device according to claim 1, wherein the coating layer is made of a silane-based, aluminum chelate-based, or aluminum alkote-based coupling agent. 3. The semiconductor chip, together with a frame supporting the semiconductor chip and bonding wires, is covered with a polyimide resin or silicone resin material without directly touching it, as set forth in claim 1. A resin-encapsulated semiconductor device. 4. In a resin-sealed semiconductor device in which a semiconductor chip is molded and sealed with a resin material, corner portions of the four corners of the semiconductor chip in which semiconductor elements and wiring are provided within at least 500 μm from the corner. A resin-sealed semiconductor device characterized by having a slope.