JPH02303038A - Wire bonding - Google Patents

Wire bonding

Info

Publication number
JPH02303038A
JPH02303038A JP1123813A JP12381389A JPH02303038A JP H02303038 A JPH02303038 A JP H02303038A JP 1123813 A JP1123813 A JP 1123813A JP 12381389 A JP12381389 A JP 12381389A JP H02303038 A JPH02303038 A JP H02303038A
Authority
JP
Japan
Prior art keywords
bonding
wire
electrode
wires
ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1123813A
Other languages
Japanese (ja)
Inventor
Yuji Ito
裕二 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1123813A priority Critical patent/JPH02303038A/en
Publication of JPH02303038A publication Critical patent/JPH02303038A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce bonding time by connecting electrodes mutually with wires in such a way that the wires are connected continuously at the same place and cutting the wires after performing wedge bonding. CONSTITUTION:A wire derived from the 1st electrode and the wire leading into the 3rd electrode are connected continuously to the 2nd electrode 2 at the same place in such a way as to allow the side faces of wires to be pressed under pressure. First of all, ball bonding is performed at the electrode 2 on an IC chip 1 and the shape of looping 8 is formed to reach an interchange range 5. The wire is not cut and stitching bonding 9 is performed by using bonding conditions under which the wire is connected to the interchange range 5. Subsequently, the shape of looping 10 is formed to reach an inner lead 6. Then the wire is connected to the lead 6 by stitching bonding 11 and then, the wire is cut. After wire bonding is performed at a space between the electrode 2 and the interchange range 5, time required for shaping balls newly is saved and connecting operations are repeated several times. Bonding time is thus reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はワイヤボンディングによる接続技術に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a connection technique by wire bonding.

〔従来の技術〕[Conventional technology]

従来、ＩＣチップのｆｆｉ＋３とリードフレームのイン
ナーリードとの間は、一本のワイヤボンディングによっ
て接続されており、ワイヤボンディングの方法としては
、ＩＣチップの電極でボールボンディングを、インナー
リード側ではステッチボンディングをおこなうボールボ
ンディング方式、およびＩＣチップ電極とインナーリー
ドともどもウエジボンディングをおこなうウェッジボン
ディング方式が多用されている。Conventionally, the ffi+3 of the IC chip and the inner lead of the lead frame have been connected by a single wire bonding method, and the wire bonding methods include ball bonding with the electrode of the IC chip and stitch bonding on the inner lead side. The ball bonding method, which performs this, and the wedge bonding method, which performs wedge bonding on both the IC chip electrode and the inner lead, are widely used.

近年、ｔＣチップの高集積化、多機能化により電極数や
フレーム側の端子数の増加が進んでいるわけであるが、
公知の通り、ＩＣチップ側は比較的容易に微細化が進め
られ、電極数の増加に対応できるものの、リードフレー
ムのインナーリードは、フレームの材厚に対するエツチ
ングやスタンピング加工技術の限界によって、ＩＣチッ
プの微細化に追従した対応ができず、ＩＣチップから遠
ざかった位置にインナーリードを配置しなければならな
くなった。In recent years, the number of electrodes and the number of terminals on the frame side have been increasing due to the high integration and multifunctionality of tC chips.
As is well known, the IC chip side can be miniaturized relatively easily and can accommodate an increase in the number of electrodes, but the inner leads of the lead frame cannot be processed easily due to the limits of etching and stamping processing technology for the frame material thickness. It was not possible to keep up with the miniaturization of IC chips, and the inner leads had to be placed far away from the IC chip.

したがって、従来のボンディング方法を用いた場合、Ｉ
Ｃチップの電極とインナーリード間を長いワイヤを用い
て接続しなければならず、ワイヤが長いことによる問題
点である、ワイヤの曲りやたるみ等が発生しやすく、満
足のいくワイヤボンディング品質を維持することは難か
しいものとなった。したがって、ワイヤの長さ制限から
ＩＣのチップサイズの縮少化に制限を与えることになっ
た。Therefore, when using conventional bonding methods, I
The electrodes of the C chip and the inner leads must be connected using long wires, and problems such as bending and sagging of the wires are likely to occur due to long wires, and satisfactory wire bonding quality cannot be maintained. It became difficult to do so. Therefore, the reduction in the chip size of an IC has been restricted due to the wire length restriction.

そこで、ＩＣチップの電極とインナーリードとの間に中
継範囲を設け、２本のワイヤボンディングによって接続
される中継ボンディング方式が考案され、採用されつつ
ある。Therefore, a relay bonding method has been devised and is being adopted, in which a relay range is provided between the electrodes of the IC chip and the inner leads, and the two wires are connected by bonding.

中継ボンディング方式は、既存の安定した品質を確保で
きるワイヤボンディング技術を用いて、前記した課題に
対応できるようになった。The relay bonding method has become able to address the above-mentioned problems by using existing wire bonding technology that can ensure stable quality.

第３図（ａ）（ｂ）を用いて、従来の中継ボンディング
方式について説明する。尚ここではボールボンディング
を用いた接続例について説明する。The conventional relay bonding method will be explained using FIGS. 3(a) and 3(b). Here, a connection example using ball bonding will be explained.

まず、リードフレーム３上に設置されたＩＣチップ１と
、前記ＩＣチップ１とインナーリード６との間に位置し
、同じくリードフレーム３上に設置された絶縁基板４が
用意される。前記絶縁基板４上には導電性を有する中継
範囲５が形成される。First, an IC chip 1 placed on a lead frame 3 and an insulating substrate 4 placed between the IC chip 1 and the inner leads 6 and also placed on the lead frame 3 are prepared. A conductive relay area 5 is formed on the insulating substrate 4. As shown in FIG.

次に、前記ＩＣチップ１上の電極２にてボールボンディ
ング１７が実施された後、ルーピング形状１８を形成し
、前記中継範囲５の５Ａ点に到達し、ステッチボンディ
ング１９によりワイヤと中継範囲とが接続され、かつワ
イヤは切断される。Next, after ball bonding 17 is performed on the electrode 2 on the IC chip 1, a looping shape 18 is formed and a point 5A of the relay range 5 is reached, and stitch bonding 19 connects the wire and the relay range. Connected and wires are disconnected.

切断後、再びボールが形成され、続いて前記Ａ点と電気
的に同電位にてつながる前記中継範囲５の５Ｂ点にてボ
ールボンディング２０が実施され、同様にルーピング形
状２１を形成し、インナーリード６に到達し、ステッチ
ボンディング２２によりワイヤとインナーリードとが接
続され、かつワイヤは切断され、次のＩＣ上の電極にボ
ールボンディングをおこなうためのボールが形成される
。After cutting, a ball is formed again, and then ball bonding 20 is performed at point 5B of the relay range 5, which is electrically connected to the point A at the same potential, and a looping shape 21 is similarly formed, and the inner lead 6, the wire and the inner lead are connected by stitch bonding 22, and the wire is cut, forming a ball for ball bonding to the electrode on the next IC.

以降、残りの接続数繰り返される。After that, the process is repeated for the remaining number of connections.

また、第４図（ａ）、（ｂ）に示すウェッジボンディン
グ方式も同様に、ｔＣチップ１上の電極２にてウェッジ
ボンディング２３が実施された後、ルーピング形状２４
を形成し、前記中継範囲５の５Ａ点に到達し、ウェッジ
ボンディング２５によりワイヤと中継範囲とが接続され
、かつワイヤは切断される。Similarly, in the wedge bonding method shown in FIGS. 4(a) and 4(b), after wedge bonding 23 is performed on the electrode 2 on the tC chip 1, the looping shape 24 is
is formed and reaches point 5A of the relay range 5, the wire and the relay range are connected by wedge bonding 25, and the wire is cut.

続いて前記５Ａ点と電気的に同電位にてつながる前記中
継範囲５の５Ｂ点にウェッジボンディング２５が実施さ
れ、同様にルーピング形状２７を形成し、インナーリー
ド６に到達し、ウェッジボンディング２８によりワイヤ
とインナーリードとが接続され、かつワイヤは切断され
る。Subsequently, wedge bonding 25 is performed at point 5B of the relay range 5 which is electrically connected to the point 5A at the same potential, similarly forming a looping shape 27, reaching the inner lead 6, and the wire is bonded by wedge bonding 28. and the inner lead are connected, and the wire is cut.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の中継ボンディング方式では、既存の安定した品質
を確保できるワイヤボンディング技術を用いて容易に電
極数や端子数の増加に対応し、当初の目的を達成するこ
とができた。With the conventional relay bonding method, we were able to easily accommodate an increase in the number of electrodes and terminals by using existing wire bonding technology that can ensure stable quality, and were able to achieve the original purpose.

しかしながらワイヤボンディングを２回にわけて実施し
なければならず、ワイヤボンディング時間が通常の２倍
必要となり、コストアップと生産性の低下が生じた。However, wire bonding had to be performed twice, requiring twice as much wire bonding time as usual, resulting in an increase in cost and a decrease in productivity.

したがって、少しでもボンディング時間を短縮するワイ
ヤボンディング方法が強く望まれた。Therefore, there has been a strong desire for a wire bonding method that shortens the bonding time as much as possible.

そこで、本発明は、このような課題を解決しようとする
もので、その目的とするところは、ボンディング面積が
少なくて済むと共にボンディング時間が短縮され、勝つ
高品質なボンディング強度の得られるワイヤボンディン
グ方法を提供するところにある。Therefore, the present invention aims to solve these problems, and its purpose is to provide a wire bonding method that requires less bonding area, shortens bonding time, and provides high quality bonding strength. It is in a place where we provide.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のワイヤボンディング方法は、 （１）すくなくとも、３ケ所の電極間をワイヤボンディ
ングにて接続するワイヤボンディング方法において、各
ボンディング点の中間に位置する電極（第二の電極）で
は、第一の電極からのワイヤと、第三の電極へのワイヤ
が同一筒所にてワイヤ側面を押圧されて接続されている
ことを特徴とする。The wire bonding method of the present invention is as follows: (1) In the wire bonding method in which at least three electrodes are connected by wire bonding, the electrode (second electrode) located in the middle of each bonding point is connected to the first electrode. It is characterized in that the wire from the electrode and the wire to the third electrode are connected at the same cylindrical location by pressing the wire side surface.

（２）また、前記第一の電極ではボールボンディングが
実施され、前記第二の電極ではワイヤを切断しないスイ
ッチボンディングが実施され、前記第三の電極ではステ
ッチボンディング後ワイヤが破断され、次の第一の電極
でのボールボンディングを実施するためのボール形成が
おこなわれ、第一〜第三の電極間を連続するワイヤにて
接続することを特徴とする。(2) Further, ball bonding is performed on the first electrode, switch bonding that does not cut the wire is performed on the second electrode, and the wire is broken after stitch bonding on the third electrode, and the next electrode is A ball is formed to perform ball bonding with one electrode, and the first to third electrodes are connected by a continuous wire.

（３）さらに前記第一の電極ではウェッジボンディング
が実施され、前記第二の電極ではワイヤを切断しないウ
ェッジボンディングが実施され、前記第三の電極ではウ
ェッジボンディング後ワイヤが切断され、第一〜第三の
電極間を連続するワイヤにて接続することを特徴とする
。(3) Further, the first electrode performs wedge bonding, the second electrode performs wedge bonding without cutting the wire, the third electrode cuts the wire after wedge bonding, and the first to third electrodes perform wedge bonding without cutting the wire. It is characterized by connecting the three electrodes with a continuous wire.

〔実　施　例］ 第１図（ａ）、（ｂ）は本発明の実施例をボールボンデ
ィング方式を用いた接続方法にて説明した模式図である
。リードフレーム３上に設置されたＩＣチップ１と、前
記ＩＣチップ１とインナーリード６との間に位置し、同
じくリードフレーム３上に設置された絶縁基板４が用意
される。[Embodiment] FIGS. 1(a) and 1(b) are schematic diagrams illustrating an embodiment of the present invention using a connection method using a ball bonding method. An IC chip 1 placed on a lead frame 3 and an insulating substrate 4 located between the IC chip 1 and the inner leads 6 and also placed on the lead frame 3 are prepared.

絶縁基板４上には導電性を有する中継範囲５が形成され
ている。A conductive relay area 5 is formed on the insulating substrate 4.

次に前記１ｃチツプ１上の電極２にてボールボンディン
グ７が実施された後、ルーピング形状８を形成し、前記
中継範囲５に到達する。Next, after ball bonding 7 is performed on the electrode 2 on the 1c chip 1, a looping shape 8 is formed and reaches the relay area 5.

ここで、ワイヤを切断せず、かつワイヤと中継範囲５と
が接続されるボンディング条件を用いてステッチボンデ
ィング９が実施される。Here, stitch bonding 9 is performed using bonding conditions in which the wire is not cut and the wire and relay range 5 are connected.

次に、ルーピング形状１０を形成し、インナーリード６
に到達し、ステッチボンディング１１によりワイヤとイ
ンナーリード６が接続され、かつワイヤが切断される。Next, a looping shape 10 is formed, and the inner lead 6
The wire and the inner lead 6 are connected by the stitch bonding 11, and the wire is cut.

そして、次のＩＣ上の電極にボールボンドするためのポ
ル形成がなされ、以降、残りの接続数繰り返えされる。Then, a pole is formed for ball bonding to an electrode on the next IC, and thereafter, connections are repeated for the remaining number of connections.

以上の方法により、電極２と中継範囲５の間をワイヤボ
ンディングした後、新たにボールを形成する時間を省く
ことが本発明の特徴である。A feature of the present invention is that the above method eliminates the time required to form a new ball after wire bonding between the electrode 2 and the relay area 5.

また、この方式を実施する上では、中継範囲５にて、ワ
イヤを切らずに接続するステッチボンディング９のボン
ディング条件と、ボール形成のためにワイヤを切断し、
かつ接続するステッチボンディング１１のボンディング
条件の２種のボンディング条件を用いることが特徴とな
る。In addition, in implementing this method, the bonding conditions for stitch bonding 9 in which the wire is connected without cutting it in the relay range 5, and the bonding condition in which the wire is cut to form a ball,
It is also characterized in that two types of bonding conditions are used: the bonding conditions for the stitch bonding 11 to be connected.

このことは、以降の実施例においても同様である。This also applies to the following embodiments.

第２図（ａ）　　・　（ｂ）にウェッジボンディング方
式を用いた、本発明の実施例の模式図を示す。FIGS. 2(a) and 2(b) show schematic diagrams of an embodiment of the present invention using the wedge bonding method.

まず、前記実施例と同様、リードフレーム３上に、ＩＣ
チップ１と導電性を有する中継範囲５を設けた絶縁基板
４が設置される。First, as in the above embodiment, an IC is placed on the lead frame 3.
An insulating substrate 4 provided with a chip 1 and a conductive relay area 5 is installed.

次に前記ＩＣチップ１上の電極２にてウェッジボンディ
ング１２が実施された後、ルーピング形状１３を形成し
、前記中継範囲５に到達する。Next, after wedge bonding 12 is performed on the electrode 2 on the IC chip 1, a looping shape 13 is formed and the looping shape 13 is formed to reach the relay range 5.

ここで、ワイヤを切断せず、かつワイヤと中継範囲５と
が接続されるボンディング条件を用いてウェッジボンデ
ィング１４が実施される。Here, wedge bonding 14 is performed using bonding conditions in which the wire is not cut and the wire and relay range 5 are connected.

次に、ルーピング形状１５を形成し、インナーリード６
に到達し、ウェッジボンティング１６によりワイヤとイ
ンナーリード６が接続され、かつワイヤが切断される。Next, a looping shape 15 is formed, and the inner lead 6
The wire is connected to the inner lead 6 by the wedge bonding 16, and the wire is cut.

以降、残りの接続数が繰り返えされる。After that, the process is repeated for the remaining number of connections.

実施例は以上であるが、説明の中で用いた各ボンディン
グ方式の計上について図示する。The embodiment has been described above, and the accounting of each bonding method used in the explanation will be illustrated.

第５図（ａ）（ｂ）はｂ−ルボンディング７．１７．２
０、第６図（ａ）（ｂ）はボンディング後ワイヤ切断し
たスラッチボンディング１１．１９．２２、第７図（ａ
）（ｂ）はワイヤを切断しないステッチボンディング９
、第８図（ａ）（ｂ）はウェッジボンディング１２．２
３．２６、第９図（ａ）（ｂ）はボンディング後ワイヤ
切断したウニエツジボンディング１６．２５．２８、第
１０図（ａ）（ｂ）はワイヤを切断しないステッチボン
ディング１４である。Figures 5(a) and 5(b) show b-le bonding 7.17.2.
0, Figures 6(a) and 6(b) show slatch bonding with wire cut after bonding 11.19.22, Figure 7(a)
)(b) is stitch bonding 9 without cutting the wire.
, Figures 8(a) and (b) show wedge bonding 12.2.
3.26, FIGS. 9(a) and 9(b) show sea urchin stitch bonding 16.25.28 in which the wire is cut after bonding, and FIGS. 10(a) and (b) are stitch bonding 14 in which the wire is not cut.

本発明を用いることにより、次の効果をもたらすことが
できる。By using the present invention, the following effects can be brought about.

１）ボンディング時間の短縮 通常、一本のワイヤボンディングをおこなうためには約
０．２秒の時間を要している。1) Shortening of bonding time Normally, it takes about 0.2 seconds to bond one wire.

従来の方式で製品の加工時間を算出してみる。Let's calculate the processing time of a product using the conventional method.

（前提として、中継範囲を１つ設け、１つの接続を２本
のワイヤを用い、３００本の接続をおこなう場合とした
。） ０．２秒／本×２本／接続×３００本−１２０秒を要し
ていた。(The assumption is that one relay range is provided, one connection uses two wires, and 300 connections are made.) 0.2 seconds/wire x 2 wires/connection x 300 wires - 120 seconds It required

本発明の方法を用いた場合、１回目のボンディング時間
のうち、ボール形成時間的０．０５秒を省くことができ
、１回目は０．１５秒、２回目は０．２秒となり、同様
な条件下では（０，１５秒＋０．２秒）Ｘ３００本−１
０５秒となる。When the method of the present invention is used, 0.05 seconds of the ball forming time can be omitted from the first bonding time, and the time for the first bonding is 0.15 seconds, and the second bonding time is 0.2 seconds. Under the conditions (0.15 seconds + 0.2 seconds) x 300 pieces - 1
05 seconds.

したがって、本発明により一製品あたり１５秒（８，８
％）の時間短縮が可能となる。Therefore, according to the present invention, 15 seconds (8,8
%) time can be reduced.

また、将来的に予想される製品形態として、５００本の
接続で、２ケの中継範囲を設け、−接続を３本のワイヤ
で接続することを想定した場合、従来方式では３００秒
を要したのに対し、本発明では２５０秒と５０秒（１６
，７％）の短縮が可能となり、中継筒所が増えるにつれ
、時間短縮率が向上するものである。In addition, if we assume that a product format expected in the future is to have 500 connections, two relay ranges, and three wires for - connections, the conventional method would take 300 seconds. In contrast, in the present invention, 250 seconds and 50 seconds (16
, 7%), and as the number of relay stations increases, the time reduction rate improves.

２）ボンディング位置補正時間の短縮 リードフレーム上に設置されたＩＣチップや中継範囲は
、ワイヤボンディング工程の前段で取り付けられるわけ
であるが、その取付精度にはバラツキをもっている。し
たがって、画像処理位置補正装置等を用いて、実施のボ
ンディング位置を算出してボンディングがおこなわれて
いる。2) Reducing bonding position correction time The IC chips and relay ranges installed on the lead frame are attached at the front stage of the wire bonding process, but there are variations in their attachment accuracy. Therefore, bonding is performed by calculating the actual bonding position using an image processing position correction device or the like.

このときの位置補正は、ＩＣチップ１、中継範囲５上の
ボンディング点５Ａおよび５Ｂ、インナーリード６の４
ケ所出実施されていたが、ボンディング点が１ケ所省か
れたことにより、補正する必要がなくなり、作業時間の
短縮がはかられた。At this time, the position correction is performed on the IC chip 1, the bonding points 5A and 5B on the relay range 5, and the inner lead 6.
However, since one bonding point was omitted, there was no need for correction, and the work time was shortened.

３）中継範囲の大きさを小さくできる。3) The size of the relay range can be reduced.

中継範囲上のボンディング点が１ケ所になったことによ
り、中継崎囲上のボンディングエリアを小さくすること
ができ、中継範囲部材のコストダウンをおこなうことが
できる。Since there is only one bonding point on the relay range, the bonding area on the relay area can be reduced, and the cost of the relay range members can be reduced.

４）接合品質の向上 製品の品質を確保するために、接続部の品質を確保する
ことが重要なことである。4) Improving joint quality In order to ensure the quality of the product, it is important to ensure the quality of the joints.

そこで、本発明を用いれば、従来、−接続において４ケ
所でワイヤと電極とが接合されていたのに対し３ケ所で
良く、前記事例とした３００本の接続においては、従来
方法で１２００ケ所に対して９００ケ所となり、接続部
における故障率を低減させることができる。Therefore, by using the present invention, the wire and electrode were joined at four places in the conventional - connection, but only three places are needed. In contrast, the number of connections is 900, and the failure rate at the connection parts can be reduced.

以上の説明の通り、本発明による方法により、生産性の
向上した中継ボンディング方式を提供できる、ＩＣチッ
プの微細化促進に寄与できるものである。As explained above, the method according to the present invention can provide a relay bonding method with improved productivity and contribute to the promotion of miniaturization of IC chips.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、３ケ所の電極間をワ
イヤボンディングにて接続するワイヤボンディング方法
において、各ボンディング点の中間に位置する第二の電
極で、第一の電極からのワイヤと、第三の電極へのワイ
ヤが同一筒所にてワイヤ側面を押圧され連続して接続さ
れるので、ボンディング時間が従来技術の中継ボンディ
ングと比較されば著しく短縮可能になると共にボンディ
ング筒所も一ケ所ですむことからその所要面積が著しく
少なくできるという効果を有する。As described above, according to the present invention, in a wire bonding method in which three electrodes are connected by wire bonding, the second electrode located in the middle of each bonding point connects the wire from the first electrode. Since the wire to the third electrode is connected continuously by pressing the wire side surface at the same cylindrical location, the bonding time can be significantly shortened compared to the relay bonding of the prior art, and the bonding cylindrical location is also reduced. This has the effect that the required area can be significantly reduced since only one place is required.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明実施例のボールボンディング方式模式図
であり、第２図は従来実施例のウェッジボンディング方
式模式図である。 第３図は従来実施例のボールボンディング方式模式図で
あり、第４図は従来実施例のウェッジボンディング方式
模式図である。 第５図〜第１０図は各ボンディング方式のボンディング
形状について示した図である。 それぞれの図において、（ａ）は平面図を、（ｂ）は側
面図を表わす。 １拳働番ＩＣチ・ノブ ２・・・電極 ３・・争リードフレーム ４・・・絶縁基板 ５・・・中継範囲 ６・・Ｑインナーリード 以上FIG. 1 is a schematic diagram of a ball bonding method according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a wedge bonding method of a conventional embodiment. FIG. 3 is a schematic diagram of a ball bonding method of a conventional embodiment, and FIG. 4 is a schematic diagram of a wedge bonding method of a conventional embodiment. FIGS. 5 to 10 are diagrams showing the bonding shapes of each bonding method. In each figure, (a) represents a plan view, and (b) represents a side view. 1st work number IC chip/knob 2... electrode 3... lead frame 4... insulation board 5... relay range 6... Q inner lead or more

Claims (3)

【特許請求の範囲】[Claims] （１）すくなくとも、３ヶ所の電極間をワイヤボンディ
ングにて接続するワイヤボンディング方法において、各
ボンディング点の中間に位置する電極（第二の電極）で
は、第一の電極か一らのワイヤと、第三の電極へのワイ
ヤが同一筒所にてワイヤ側面を押圧されて接続されてい
ることを特徴とすワイヤボンディング方法。(1) In a wire bonding method in which at least three electrodes are connected by wire bonding, the electrode (second electrode) located in the middle of each bonding point has a wire from the first electrode, A wire bonding method characterized in that the wire to the third electrode is connected by pressing the wire side surface at the same cylindrical location. （２）前記第一の電極ではボールボンディングが実施さ
れ、前記第二の電極ではワイヤを切断しないステッチボ
ンディングが実施され、前記第三の電極ではステッチボ
ンディング後ワイヤが破断され、次の第一の電極でのボ
ールボンディングを実施するためのボール形成がおこな
われ、第一〜第三の電極間を連続するワイヤにて接続す
ることを特徴とする請求項１記載のワイヤボンディング
方法。(2) The first electrode performs ball bonding, the second electrode performs stitch bonding without cutting the wire, and the third electrode breaks the wire after stitch bonding, and the next first electrode 2. The wire bonding method according to claim 1, wherein a ball is formed to perform ball bonding with an electrode, and the first to third electrodes are connected by a continuous wire. （３）前記第一の電極ではウェッジボンディングが実施
され、前記第二の電極ではワイヤを切断しないウェッジ
ボンディングが実施され、前記第三の電極ではウェッジ
ボンディング後ワイヤが切断され、第一〜第三の電極間
を連続するワイヤにて接続することを特徴とする請求項
１記載のワイヤボンディング方法。(3) The first electrode performs wedge bonding, the second electrode performs wedge bonding without cutting the wire, the third electrode cuts the wire after wedge bonding, and the first to third electrodes perform wedge bonding without cutting the wire. 2. The wire bonding method according to claim 1, wherein the electrodes are connected by a continuous wire.
JP1123813A 1989-05-17 1989-05-17 Wire bonding Pending JPH02303038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1123813A JPH02303038A (en) 1989-05-17 1989-05-17 Wire bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1123813A JPH02303038A (en) 1989-05-17 1989-05-17 Wire bonding

Publications (1)

Publication Number Publication Date
JPH02303038A true JPH02303038A (en) 1990-12-17

Family

ID=14869975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1123813A Pending JPH02303038A (en) 1989-05-17 1989-05-17 Wire bonding

Country Status (1)

Country Link
JP (1) JPH02303038A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065647A (en) * 1992-06-24 1994-01-14 Nec Kyushu Ltd Semiconductor device
JP2002208609A (en) * 2001-01-09 2002-07-26 Oki Electric Ind Co Ltd Method of bonding metal wire
JP2007208148A (en) * 2006-02-03 2007-08-16 Ail Kk Semiconductor chip mounted substrate
WO2008047665A1 (en) * 2006-10-16 2008-04-24 Kaijo Corporation Semiconductor device
JP2014513870A (en) * 2011-05-18 2014-06-05 サンディスク セミコンダクター （シャンハイ） カンパニー， リミテッド Waterfall wire bonding
JP2015018946A (en) * 2013-07-11 2015-01-29 カルソニックカンセイ株式会社 Structure and manufacturing method of plated circuit
CN112930590A (en) * 2018-12-12 2021-06-08 贺利氏材料新加坡有限公司 Method for electrically connecting contact surfaces of electronic components

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065647A (en) * 1992-06-24 1994-01-14 Nec Kyushu Ltd Semiconductor device
JP2002208609A (en) * 2001-01-09 2002-07-26 Oki Electric Ind Co Ltd Method of bonding metal wire
JP4674970B2 (en) * 2001-01-09 2011-04-20 Ｏｋｉセミコンダクタ株式会社 Metal wire bonding method
JP2007208148A (en) * 2006-02-03 2007-08-16 Ail Kk Semiconductor chip mounted substrate
WO2008047665A1 (en) * 2006-10-16 2008-04-24 Kaijo Corporation Semiconductor device
JP2008098549A (en) * 2006-10-16 2008-04-24 Kaijo Corp Semiconductor device
JP2014513870A (en) * 2011-05-18 2014-06-05 サンディスク セミコンダクター （シャンハイ） カンパニー， リミテッド Waterfall wire bonding
US9704797B2 (en) 2011-05-18 2017-07-11 Sandisk Information Technology (Shanghai) Co., Ltd. Waterfall wire bonding
JP2015018946A (en) * 2013-07-11 2015-01-29 カルソニックカンセイ株式会社 Structure and manufacturing method of plated circuit
CN112930590A (en) * 2018-12-12 2021-06-08 贺利氏材料新加坡有限公司 Method for electrically connecting contact surfaces of electronic components
CN112930590B (en) * 2018-12-12 2024-01-02 贺利氏材料新加坡有限公司 Method for electrically connecting contact surfaces of electronic components

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