JPS6113650A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS6113650A
JPS6113650A JP59133723A JP13372384A JPS6113650A JP S6113650 A JPS6113650 A JP S6113650A JP 59133723 A JP59133723 A JP 59133723A JP 13372384 A JP13372384 A JP 13372384A JP S6113650 A JPS6113650 A JP S6113650A
Authority
JP
Japan
Prior art keywords
island
integrated circuit
break
hybrid integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59133723A
Other languages
Japanese (ja)
Inventor
Naoharu Senba
仙波　直治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59133723A priority Critical patent/JPS6113650A/en
Publication of JPS6113650A publication Critical patent/JPS6113650A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To reduce strain generated in a large island in a base ribbon made of a metal, and to obtain a hybrid IC having stable quality by forming a hole- shaped break-off to the island. CONSTITUTION:A large number of break-offs 6 such as circular holes are shaped to an island in a base ribbon 1' made of a metal. A semiconductor element or a circuit substrate 2' is bonded with the island, connected to external leading-out terminals 4' by using metallic small-gage wires 3', and sealed by employing a sheathing resin 5'. Thermal expansion, shrinkage and strain generated in the island are eliminated by the formation of the break-off sections, and stress to the circuit substrate or the element is reduced, thus shaping an LSI having stable quality.

Description

【発明の詳細な説明】 （技術分野） 本発明はペースリボンを用いた混成集積回路装置に関す
るものである。TECHNICAL FIELD The present invention relates to a hybrid integrated circuit device using a pace ribbon.

（従来技術） 従来のこの種の混成集積回路装置は第１図に示すように
金属製ベースリボ／１のアイランド部に回路基板または
半導体素子２を接着し必要に応じ、金属細線３を用いて
外部引出端子４に接続を行ない、外装樹脂５により封止
している。しかしながらこの様な構造では、混成集積回
路装置の規模が大きくなればなるほどアイランド部は大
きくなる。(Prior Art) In the conventional hybrid integrated circuit device of this type, as shown in FIG. It is connected to the lead terminal 4 and sealed with an exterior resin 5. However, in such a structure, the island portion becomes larger as the scale of the hybrid integrated circuit device becomes larger.

これに伴い、当然、アイランドの熱膨張収縮及び歪みは
大きくなり１回路基板及び半導体素子にクラック、断線
及び熱変形等による特性変動が発生し、品質が不安定と
なる。Naturally, as a result, the thermal expansion/contraction and distortion of the island become large, causing characteristic fluctuations in the circuit board and the semiconductor element due to cracks, disconnections, thermal deformation, etc., resulting in unstable quality.

（発明の目的） 本発明は従来技術の問題点をなくし、品質の向上及び大
規模な混成縦積回路提供を目的としたものである。(Objective of the Invention) The present invention aims to eliminate the problems of the prior art, improve quality, and provide a large-scale hybrid vertical product circuit.

（発明の構成及び実施例） 本発明は金属製ベースリボンのアイランド部に丸穴、角
穴等の欠損部を設けたことを特徴とする混成集積回路装
置に関するものである。(Structure and Embodiments of the Invention) The present invention relates to a hybrid integrated circuit device characterized in that a missing portion such as a round hole or a square hole is provided in an island portion of a metal base ribbon.

本発明を図面に基づき詳細に説明すると第２図は本発明
の一実施例を示す平面図である。金属製ベースリボン１
′のアイランドには丸穴、角穴等の欠損部６が多数ある
。このアイランド部に回路基板または半導体素子２′を
接着し、必要に応じ金属細線３′を用いて外部引出し端
子４′に接続を行ない。The present invention will be explained in detail based on the drawings. FIG. 2 is a plan view showing one embodiment of the present invention. Metal base ribbon 1
The island ' has many missing parts 6 such as round holes and square holes. A circuit board or semiconductor element 2' is adhered to this island portion, and connections are made to external lead terminals 4' using thin metal wires 3' as required.

外装樹脂５′を用いて封止する。本構造（フイランド部
に丸穴、角穴等の欠損部を設けた）を取ることによりア
イランドに発生する熱膨張、収縮及び歪みが欠損部によ
り消去され回路基板あるいは半導体素子に対するストレ
スが軽減される。It is sealed using an exterior resin 5'. By adopting this structure (having a defect such as a round hole or a square hole in the fillet part), the thermal expansion, contraction, and distortion generated in the island are eliminated by the defect, reducing stress on the circuit board or semiconductor element. .

（発明の効果） 本発明によれば金属製ベースリボンのアイラントド部に
丸穴、角穴等の欠損部を設けることによりアイランド部
に発生するストレス金軽減し品質の安定した大規模で高
品質の混成集積回路の提供を可能とするものである。(Effects of the Invention) According to the present invention, by providing a missing part such as a round hole or a square hole in the islanded part of a metal base ribbon, the stress generated in the island part can be reduced, and a large-scale and high-quality product with stable quality can be produced. This makes it possible to provide a hybrid integrated circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の混成集積回路装置の平面図である。第２
図は本発明による一実施例を示す平面図である。 １．１′・・・・・・金属ペースリボン、２．　２’・
・・・・・回路基板あるいは半導体素子、３，３／・・
・・・・金属細線、４．４１・・・・−・外部引出し端
子、５．５′・・・・・・外装樹脂。 ６・・・・・・欠損部。 第　１　図 第２　図FIG. 1 is a plan view of a conventional hybrid integrated circuit device. Second
The figure is a plan view showing an embodiment according to the present invention. 1.1'...metal paste ribbon, 2. 2'・
...Circuit board or semiconductor element, 3,3/...
...Fine metal wire, 4.41...--external lead-out terminal, 5.5'...exterior resin. 6... Defect part. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 金属製ベースリボンのアイランド部に穴状の欠損部を設
けたことを特徴とする混成集積回路装置。A hybrid integrated circuit device characterized in that a hole-shaped cutout is provided in an island portion of a metal base ribbon.
JP59133723A 1984-06-28 1984-06-28 Hybrid integrated circuit device Pending JPS6113650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59133723A JPS6113650A (en) 1984-06-28 1984-06-28 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59133723A JPS6113650A (en) 1984-06-28 1984-06-28 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6113650A true JPS6113650A (en) 1986-01-21

Family

ID=15111401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59133723A Pending JPS6113650A (en) 1984-06-28 1984-06-28 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6113650A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0293970A2 (en) * 1987-06-03 1988-12-07 SGS-THOMSON MICROELECTRONICS S.p.A. Pad for supporting a chip of an integrated-circuit electronic component
DE102014008587B4 (en) 2014-06-10 2022-01-05 Vitesco Technologies GmbH Power semiconductor circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0293970A2 (en) * 1987-06-03 1988-12-07 SGS-THOMSON MICROELECTRONICS S.p.A. Pad for supporting a chip of an integrated-circuit electronic component
EP0293970A3 (en) * 1987-06-03 1989-04-26 SGS-THOMSON MICROELECTRONICS S.p.A. Pad for supporting a chip of an integrated-circuit electronic component
DE102014008587B4 (en) 2014-06-10 2022-01-05 Vitesco Technologies GmbH Power semiconductor circuit

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