JP3067560B2 - Electronic component manufacturing method - Google Patents
Electronic component manufacturing methodInfo
- Publication number
- JP3067560B2 JP3067560B2 JP6299531A JP29953194A JP3067560B2 JP 3067560 B2 JP3067560 B2 JP 3067560B2 JP 6299531 A JP6299531 A JP 6299531A JP 29953194 A JP29953194 A JP 29953194A JP 3067560 B2 JP3067560 B2 JP 3067560B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- electronic component
- chip
- lead frame
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＬＯＣ（Ｌｅａｄ Ｏ
ｎ Ｃｈｉｐ）方式の電子部品製造方法に関するもので
ある。The present invention relates to a LOC (Lead O)
The present invention relates to an electronic component manufacturing method of the (n Chip) type.
【０００２】[0002]
【従来の技術】近年、ＬＯＣ方式の電子部品が使用され
るようになってきている。このＬＯＣ方式の電子部品
は、できるだけ平面的なサイズを小さくするため、チッ
プの電極とワイヤで接続されるインナーリードをチップ
と同一平面上に位置させるのではなく、インナーリード
をチップの上方にしかもチップ上にオーバーハングする
ように位置させるものである。即ち、インナーリードを
できるだけ内側（チップ側）に寄せて幅寸法を小さくし
ようとするものである。2. Description of the Related Art In recent years, LOC type electronic components have been used. In order to reduce the planar size of the LOC electronic component as much as possible, the inner leads connected to the chip electrodes and wires are not located on the same plane as the chip, but the inner leads are placed above the chip. It is positioned so as to overhang on the chip. That is, the width of the inner lead is reduced by moving the inner lead as far as possible inward (on the chip side).
【０００３】[0003]
【発明が解決しようとする課題】このＬＯＣ方式の電子
部品の製造方法としては、次の２つの技術が知られてい
る。第１に、リードフレームをチップがボンディングさ
れるアイランド部と、インナーリード及びアウターリー
ドを含むリード部とに分離し、リード部の先端（即ちイ
ンナーリード）の部分を、アイランド部の内側上方に交
差するように寄せ、交差したアイランド部の上面とリー
ド部の下面とをポリイミドテープで接着する方法があ
る。第２に、同様にリードフレームを分離し、２つのリ
ードフレームを溶接により連結する方法がある。The following two techniques are known as methods for manufacturing the LOC type electronic component. First, the lead frame is separated into an island portion to which a chip is bonded and a lead portion including inner leads and outer leads, and the tip of the lead portion (that is, the inner lead) intersects above the inside of the island portion. Then, there is a method in which the upper surface of the intersecting island portion and the lower surface of the lead portion are bonded with a polyimide tape. Second, there is a method of similarly separating the lead frames and connecting the two lead frames by welding.
【０００４】しかしながら、上記いずれの電子部品製造
方法によっても、別々のリードフレームを準備する必要
があるし、高価なポリイミドテープを用いたり、余分の
溶接工程が必要となるなど、ＬＯＣ方式でない電子部品
製造方法に対して非常に製造コストが高くなるという問
題点があった。However, according to any of the above electronic component manufacturing methods, it is necessary to prepare a separate lead frame, use an expensive polyimide tape, or require an extra welding step. There is a problem that the manufacturing cost is extremely high with respect to the manufacturing method.
【０００５】そこで本発明は、単一のリードフレームの
みで安価にＬＯＣ方式の電子部品を製造できる電子部品
製造方法を提供することを目的とする。Accordingly, an object of the present invention is to provide an electronic component manufacturing method capable of manufacturing an LOC type electronic component at low cost using only a single lead frame.
【０００６】[0006]
【課題を解決するための手段】本発明の電子部品製造方
法は、リードフレームのアイランドにチップをボンディ
ングする工程と、リードフレームを折曲げて、リードフ
レームのインナーリードをチップの上方に位置させる工
程と、チップの電極とインナーリードをワイヤで接続す
る工程と、インナーリード、ワイヤ及びチップをモール
ド体で封止する工程と、リードフレームをフォーミング
する工程とを含み、前記リードフレームの折曲げは、前
記リードフレームのバーよりもやや前記アイランド側に
設定される第１折曲線と、前記第１折曲線よりも前記ア
イランド側に設定される第２折曲線とのそれぞれに沿っ
て行われる。According to the present invention, there is provided a method of manufacturing an electronic component, comprising: bonding a chip to an island of a lead frame; and bending the lead frame so that inner leads of the lead frame are positioned above the chip. And, the step of connecting the electrode of the chip and the inner lead with a wire, the step of sealing the inner lead, the wire and the chip with a mold, and the step of forming a lead frame, the bending of the lead frame, Previous
Slightly above the island side of the lead frame bar
A first folding curve to be set, and
Along each of the second folding curves set on the Irland side
Ru is done Te.
【０００７】[0007]
【作用】上記構成において、単一のリードフレームを折
曲げることのみにより、リードフレームのインナーリー
ドをチップの上方にオーバーハングさせることができ、
ＬＯＣ方式の電子部品を得ることができる。したがっ
て、リードフレームを分離して準備したり、これらを結
合するためのコストを削減でき、安価にＬＯＣ方式の電
子部品を得ることができる。In the above construction, the inner lead of the lead frame can be overhanged above the chip only by bending a single lead frame.
LOC electronic components can be obtained. Therefore, it is possible to reduce the cost for separately preparing and connecting the lead frames and to join them, and it is possible to obtain the LOC type electronic component at low cost.
【０００８】[0008]
【実施例】次に図面を参照しながら本発明の実施例を説
明する。Next, an embodiment of the present invention will be described with reference to the drawings.
【０００９】図１は本発明の一実施例におけるリードフ
レームの平面図、図２（ａ）〜（ｄ）及び図３（ａ）〜
（ｄ）は、本発明の一実施例における電子部品製造方法
の工程説明図、図４は本発明の一実施例におけるワイヤ
の接続が完了した状態のリードフレームを示す斜視図で
ある。FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) and 3 (a) to 3 (a).
(D) is an explanatory view of a process in a method of manufacturing an electronic component according to an embodiment of the present invention. FIG. 4 is a perspective view showing a lead frame in a state where wire connection is completed according to an embodiment of the present invention.
【００１０】図１に示すように、本実施例の電子部品製
造方法では、単一のリードフレーム１のみによりＬＯＣ
方式の電子部品を製造できる。さてリードフレーム１の
うち、２は中央部に設けられ、チップ１０（図２参照）
が搭載されるアイランド、３はリードフレーム１の外側
を囲む外周部、４は外周部３からアイランド２に向けて
連設されるアウターリード、５は先端部が自由端であっ
てアイランド２に臨み、基端部がアウターリード４に連
設されるインナーリード、６はインナーリード５、アウ
ターリード４を幅方向に保持するバーである。As shown in FIG. 1, in the electronic component manufacturing method of the present embodiment, the LOC is
Electronic components can be manufactured. Now, of the lead frame 1, 2 is provided at the center, and a chip 10 (see FIG. 2)
3 is an outer peripheral portion surrounding the outside of the lead frame 1, 4 is an outer lead continuously provided from the outer peripheral portion 3 toward the island 2, and 5 is a free end having a front end facing the island 2. An inner lead 6 whose base end is connected to the outer lead 4 is a bar for holding the inner lead 5 and the outer lead 4 in the width direction.
【００１１】そして本実施例の電子部品製造方法では、
次に述べる２つの折曲線を設定する。その１つは、イン
ナーリード５の両脇にインナーリード５を外して設定さ
れる第１折曲線７である。この第１折曲線７は、バー６
よりややアイランド２側に位置する。もう１つは、第１
折曲線７よりもアイランド２側（インナーリード５より
もアイランド２側）に設定される第２折曲線８である。
なお第１折曲線７と第２折曲線８との間隔は、後述する
段差Ｄ（図３参照）を規定するものであり、第１折曲線
７、第２折曲線８のいずれに沿って折曲加工を行っても
インナーリード５自体がその途中から折曲ることはな
い。In the electronic component manufacturing method of the embodiment,
The following two curves are set. One of them is a first folding curve 7 set on both sides of the inner lead 5 with the inner lead 5 removed. This first fold curve 7 corresponds to the bar 6
It is located slightly closer to the island 2 side. The other is the first
The second folding curve 8 is set on the island 2 side (the island 2 side with respect to the inner lead 5) with respect to the folding curve 7.
The distance between the first folding curve 7 and the second folding curve 8 defines a step D (see FIG. 3) described later, and the folding is performed along any of the first folding curve 7 and the second folding curve 8. Even if the bending process is performed, the inner lead 5 itself does not bend from the middle.
【００１２】次に本実施例の電子部品製造方法の各工程
について、図２〜図４を参照しながら具体的に説明す
る。まず図２（ａ）に示すように、図１のリードフレー
ム１を位置決めする。次に図２（ｂ）に示すように、ア
イランド２に接着剤９を塗布し、接着剤９上にチップ１
０をダイボンディングする。Next, each step of the electronic component manufacturing method of the present embodiment will be specifically described with reference to FIGS. First, as shown in FIG. 2A, the lead frame 1 of FIG. 1 is positioned. Next, as shown in FIG. 2B, an adhesive 9 is applied to the island 2 and the chip 1 is placed on the adhesive 9.
0 is die-bonded.
【００１３】次に、図２（ｃ）に示すように、第１折曲
線７に符合する角部を備えた下受ツール１１上に、アイ
ランド２を載置し、上方から内側の角部が第１折曲線７
上に位置する２つの押圧ツール１２を矢印Ｎ１方向に下
降させ、第１折曲線７に沿った折曲加工を行う。Next, as shown in FIG. 2 (c), the island 2 is placed on the lower receiving tool 11 having a corner corresponding to the first folding curve 7, and the inner corner from above is formed. First folding curve 7
The two upper pressing tools 12 are lowered in the direction of the arrow N <b> 1 to perform bending along the first bending curve 7.
【００１４】その結果、図２（ｄ）に示すように、第１
折曲線７を境にして、リードフレーム１の外側が９０度
下方に折曲る。なお上述したように、第１折曲線７はイ
ンナーリード５を外れて設定されているので、インナー
リード５は折曲らず、インナーリード５の先端は鉛直上
方を向くことになる。As a result, as shown in FIG.
The outer side of the lead frame 1 is bent downward by 90 degrees with respect to the bending curve 7. As described above, since the first folding curve 7 is set outside the inner lead 5, the inner lead 5 does not bend, and the tip of the inner lead 5 faces vertically upward.
【００１５】次に図２（ｄ）に示すように、第２折曲線
８に内側の角部が一致する２つの下受ツール１３をリー
ドフレーム１の下面に当接させ、上方からチップ１０用
の逃げ（凹部）が設けられた押圧ツール１４であって、
その下面角部が第２折曲線８に一致するものを、矢印Ｎ
２方向に下降させ、第２折曲線８に沿った折曲加工を行
う。Next, as shown in FIG. 2D, two lower receiving tools 13 whose inner corners coincide with the second folding curve 8 are brought into contact with the lower surface of the lead frame 1, and the chip 10 Press tool 14 provided with a relief (recess) of
The one whose bottom corner coincides with the second folding curve 8 is indicated by an arrow N
It is lowered in two directions and bent along the second folding curve 8.
【００１６】その結果、図３（ａ）に示すように、リー
ドフレーム１の外側は、内側に９０度折曲られ、インナ
ーリード５の先端部はチップ１０の上方にオーバーハン
グする。またこのときアイランド２とインナーリード５
との間に段差Ｄが形成され、外周部３のうち第１折曲線
７と第２折曲線８の間にある部分は、垂直な上部１５と
なる。勿論このとき図示しているように、インナーリー
ド５、アウターリード４はアイランド２と平行になる。As a result, as shown in FIG. 3A, the outside of the lead frame 1 is bent inward by 90 degrees, and the tip of the inner lead 5 overhangs above the chip 10. At this time, Island 2 and Inner lead 5
Between the first folding curve 7 and the second folding curve 8 of the outer peripheral portion 3 becomes a vertical upper portion 15. Of course, at this time, the inner lead 5 and the outer lead 4 are parallel to the island 2 as shown.
【００１７】次に図３（ｂ）に示すように、インナーリ
ード５と、チップ１０の電極１０ａとをワイヤ１６で接
続する。このときの位置関係は図４に示すとおりであ
る。これによりＬＯＣ方式のとおり、インナーリード５
がチップ１０の上方にオーバーハングする形態を形成で
きた。Next, as shown in FIG. 3B, the inner leads 5 are connected to the electrodes 10a of the chip 10 by wires 16. The positional relationship at this time is as shown in FIG. As a result, the inner lead 5
Could overhang above the chip 10.
【００１８】以下、図３（ｃ）に示すように、インナー
リード５、チップ１０、ワイヤ１６及びアイランド２
を、モールド体１７で封止し、図３（ｄ）に示すよう
に、外周部３のバー６の切断などのフォーミングを施す
ことにより、ＬＯＣ方式の電子部品を得ることができ
る。なお、フォーミング時にアウターリード４の先端部
をモールド体１７側に折曲てもよい。Hereinafter, as shown in FIG. 3C, the inner lead 5, the chip 10, the wire 16, and the island 2
Is sealed with a mold body 17 and subjected to forming such as cutting of the bar 6 of the outer peripheral portion 3 as shown in FIG. 3D, whereby an LOC-type electronic component can be obtained. Note that the tip of the outer lead 4 may be bent toward the mold body 17 during forming.
【００１９】[0019]
【発明の効果】本発明の電子部品製造方法は、リードフ
レームのアイランドにチップをボンディングする工程
と、リードフレームを折曲げて、リードフレームのイン
ナーリードをチップの上方に位置させる工程と、チップ
の電極とインナーリードをワイヤで接続する工程と、イ
ンナーリード、ワイヤ及びチップをモールド体で封止す
る工程と、リードフレームをフォーミングする工程とを
含み、前記リードフレームの折曲げは、前記リードフレ
ームのバーよりもやや前記アイランド側に設定される第
１折曲線と、前記第１折曲線よりも前記アイランド側に
設定される第２折曲線とのそれぞれに沿って行われるの
で、単一のリードフレームにより安価にＬＯＣ方式の電
子部品を製造することができる。According to the method of manufacturing an electronic component of the present invention, a step of bonding a chip to an island of a lead frame, a step of bending the lead frame to position inner leads of the lead frame above the chip, A step of connecting the electrode and the inner lead with a wire, a step of sealing the inner lead, the wire and the chip with a mold, and a step of forming the lead frame.
The lead frame is bent by the lead frame.
The bar set slightly closer to the island than the bar
One fold curve and on the island side than the first fold curve
Runode performed along each of the second folding line to be set, it is possible to manufacture the electronic components inexpensively LOC schemes with a single lead frame.
【図１】本発明の一実施例におけるリードフレームの平
面図FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention.
【図２】（ａ）本発明の一実施例における電子部品製造
方法の工程説明図 （ｂ）本発明の一実施例における電子部品製造方法の工
程説明図 （ｃ）本発明の一実施例における電子部品製造方法の工
程説明図 （ｄ）本発明の一実施例における電子部品製造方法の工
程説明図FIG. 2A is an explanatory view of a process of an electronic component manufacturing method according to an embodiment of the present invention. FIG. 2B is an explanatory view of a process of an electronic component manufacturing method according to an embodiment of the present invention. Process description diagram of electronic component manufacturing method (d) Process description diagram of electronic component manufacturing method in one embodiment of the present invention
【図３】（ａ）本発明の一実施例における電子部品製造
方法の工程説明図 （ｂ）本発明の一実施例における電子部品製造方法の工
程説明図 （ｃ）本発明の一実施例における電子部品製造方法の工
程説明図 （ｄ）本発明の一実施例における電子部品製造方法の工
程説明図FIG. 3A is an explanatory view of a process of an electronic component manufacturing method according to an embodiment of the present invention. FIG. 3B is an explanatory view of a process of an electronic component manufacturing method according to an embodiment of the present invention. Process description diagram of electronic component manufacturing method (d) Process description diagram of electronic component manufacturing method in one embodiment of the present invention
【図４】本発明の一実施例におけるワイヤの接続が完了
した状態のリードフレームを示す斜視図FIG. 4 is a perspective view showing a lead frame in a state where connection of wires is completed according to an embodiment of the present invention.
１ リードフレーム ２ アイランド ５ インナーリード ７ 第１折曲線 ８ 第２折曲線 １０ チップ １０ａ 電極 １６ ワイヤ １７ モールド体 DESCRIPTION OF SYMBOLS 1 Lead frame 2 Island 5 Inner lead 7 First bend curve 8 Second bend curve 10 Chip 10a Electrode 16 Wire 17 Mold body
Claims (2)
ンディングする工程と、前記リードフレームを折曲げ
て、前記リードフレームのインナーリードを前記チップ
の上方に位置させる工程と、前記チップの電極と前記イ
ンナーリードをワイヤで接続する工程と、前記インナー
リード、前記ワイヤ及び前記チップをモールド体で封止
する工程と、前記リードフレームをフォーミングする工
程とを含み、前記リードフレームの折曲げは、前記リー
ドフレームのバーよりもやや前記アイランド側に設定さ
れる第１折曲線と、前記第１折曲線よりも前記アイラン
ド側に設定される第２折曲線とのそれぞれに沿って行わ
れることを特徴とする電子部品製造方法。A step of bonding a chip to an island of a lead frame, a step of bending the lead frame to position an inner lead of the lead frame above the chip, and an electrode of the chip and the inner lead. And a step of sealing the inner lead, the wire and the chip with a molded body, and a step of forming the lead frame.
Set slightly above the island than the
A first fold curve, and the island more than the first fold curve.
Along each of the second folding curves set on the side
Electronic component manufacturing method comprising Rukoto Re.
て設定されることを特徴とする請求項１記載の電子部品
製造方法。Wherein said first folding line, the electronic component manufacturing method according to claim 1, characterized in that it is set off the islands.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6299531A JP3067560B2 (en) | 1994-12-02 | 1994-12-02 | Electronic component manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6299531A JP3067560B2 (en) | 1994-12-02 | 1994-12-02 | Electronic component manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08162488A JPH08162488A (en) | 1996-06-21 |
| JP3067560B2 true JP3067560B2 (en) | 2000-07-17 |
Family
ID=17873814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6299531A Expired - Fee Related JP3067560B2 (en) | 1994-12-02 | 1994-12-02 | Electronic component manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3067560B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5676413B2 (en) * | 2011-10-28 | 2015-02-25 | 三菱電機株式会社 | Power semiconductor device |
-
1994
- 1994-12-02 JP JP6299531A patent/JP3067560B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08162488A (en) | 1996-06-21 |
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