KR100721280B1 - A method of forming semiconductor chip assembly and an apparatus for forming wire bonds from circuitry on a substrate to a semiconductor chip - Google Patents
A method of forming semiconductor chip assembly and an apparatus for forming wire bonds from circuitry on a substrate to a semiconductor chip Download PDFInfo
- Publication number
- KR100721280B1 KR100721280B1 KR1020067024582A KR20067024582A KR100721280B1 KR 100721280 B1 KR100721280 B1 KR 100721280B1 KR 1020067024582 A KR1020067024582 A KR 1020067024582A KR 20067024582 A KR20067024582 A KR 20067024582A KR 100721280 B1 KR100721280 B1 KR 100721280B1
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- South Korea
- Prior art keywords
- wire
- substrate
- semiconductor chip
- slit
- tool
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- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 42
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- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 239000004593 Epoxy Substances 0.000 abstract description 3
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- 239000008393 encapsulating agent Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 239000002184 metal Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
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- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
본 발명은 반도체 칩 조립체를 형성하는 방법을 포함한다. 기판(12)은 한 쌍의 대향 면(12, 13)과, 이 대향 면 중의 하나에 형성되는 회로(16)를 포함한다. 반도체 칩(14)은 기판에 결합된다. 다수의 와이어(28)가 회로에 결합되고 반도체 칩 상에 형성된 본딩 패드(25) 위로 연장한다. 와이어는 공구(106)로 반도체 칩의 접합부 부근에서 눌려진다. 공구는 와이어로부터 들어올려지고, 와이어가 반도체 칩의 본딩 패드에 접착된다. 또한, 본 발명은 기판(12)과 반도체 칩(14)을 지지하는 지지부(102)와, 기판에 대해 움직일 수 있게 장착된 가압 공구(106)를 포함하며, 상기 가압 공구가 기판을 향해 이동하였을 때 기판의 슬릿(18)으로 와이어를 누르도록 형성된 편향 면(120)을 갖는 장치를 포함한다. 편향 면은 실질적으로 편평하고, 슬릿의 주요 부분 내에서 연장하기 충분한 길이를 갖는다. The present invention includes a method of forming a semiconductor chip assembly. The substrate 12 includes a pair of opposing faces 12 and 13 and a circuit 16 formed on one of the opposing faces. The semiconductor chip 14 is coupled to the substrate. A number of wires 28 are coupled to the circuitry and extend over the bonding pads 25 formed on the semiconductor chip. The wire is pressed with the tool 106 near the junction of the semiconductor chip. The tool is lifted from the wire and the wire is bonded to the bonding pad of the semiconductor chip. In addition, the present invention includes a support portion 102 for supporting the substrate 12 and the semiconductor chip 14, and a pressing tool 106 movably mounted to the substrate, wherein the pressing tool has moved toward the substrate. And a deflection face 120 formed to press the wire into the slit 18 of the substrate. The deflection face is substantially flat and has a length sufficient to extend within the main portion of the slit.
반도체, 와이어 본드, 본딩 패드, 슬릿, 전도성 에폭시 Semiconductor, Wire Bond, Bonding Pad, Slit, Conductive Epoxy
Description
도 1은 종래 기술의 다이 패키지 형성 공정 준비 단계에서의 반도체 조립체의 부분 개략도.1 is a partial schematic view of a semiconductor assembly in a prior art die package forming process preparation step.
도 2는 도 1의 조립체의 일부분의 확대도.2 is an enlarged view of a portion of the assembly of FIG. 1.
도 3은 도 2의 선 3-3에 따른 단면도.3 is a cross-sectional view taken along line 3-3 of FIG.
도 4는 도 3의 선 4-4에 따른 단면도.4 is a cross-sectional view taken along line 4-4 of FIG.
도 5는 도 1 내지 도 4의 가공단계 이후의 종래 기술의 처리단계를 받는 것을 도시하는 도 1의 조립체의 일부분의 도면.5 is a view of a portion of the assembly of FIG. 1 showing receiving prior art processing steps after the processing steps of FIGS.
도 6은 반도체 칩 조립체를 처리하는데 사용되는 본 발명의 장치의 개략 부분 사시도.6 is a schematic partial perspective view of an apparatus of the present invention used to process a semiconductor chip assembly.
도 7은 본 발명의 장치에 포함되는 공구의 개략 상면도.7 is a schematic top view of a tool included in the apparatus of the present invention.
도 8은 도 6의 처리 단계 이후의 처리 단계일 때를 나타내며 도 6의 선 8-8을 따라 도시된 도 6의 장치의 부분 단면도.8 is a partial cross-sectional view of the apparatus of FIG. 6, shown along the line 8-8 of FIG. 6, showing when it is a processing step after the processing step of FIG.
도 9는 선 8-8을 따라 도시되며, 도 8의 처리 단계 이후의 처리 단계를 나타내는 도 6의 장치의 도면, 9 is a view of the apparatus of FIG. 6, shown along lines 8-8 and showing a processing step after the processing step of FIG. 8;
본 발명은 반도체 칩 조립체를 형성하는 방법 및 장치에 관한 것이다. 보다 상세하게는, 본 발명은 보드-온-칩 패키지(board-on-chip package)에 와이어 본드부를 형성하기 위한 방법 및 장치에 관한 것이다.The present invention relates to a method and apparatus for forming a semiconductor chip assembly. More particularly, the present invention relates to a method and apparatus for forming a wire bond portion in a board-on-chip package.
종래 기술의 보드-온-칩 패키지[일반적으로 다이 패키지(die package)로도 불림] 형성 방법은 도 1 내지 도 5를 참조하여 설명된다. 먼저 도 1을 참조하면, 절연 재료로 이루어진 기판(12)을 포함하는 조립체(10)의 일부분이 예시되어 있다. 기판(12)은 예를 들어 회로 보드(circuit board)를 포함할 수 있다. Prior art board-on-chip package (commonly referred to as die package) formation methods are described with reference to FIGS. Referring first to FIG. 1, a portion of an
기판(12)은 상면(13; top surface)과, 이 상면을 통과하여 연장하는 슬릿(18)을 포함한다. 회로(16; circuitry)가 상면(13)에 형성된다. 회로(16)와 슬릿(18)은 상면(13)에 걸쳐 반복적인 패턴을 형성한다. 이 반복적인 패턴은 개개의 유닛(19, 21, 23)을 형성하며, 각각의 유닛은 최종적으로 개개의 보드-온-칩 패키지를 형성한다. The
도 2 내지 도 4를 참조하면, 유닛(21)에 대응하는 기판(12)의 확대된 일부가 3개의 상이한 관점으로 도시되어 있다. 도 2는 도 1과 유사한 평면도(top view)이 고, 도 3은 도 2의 선 3-3에 따른 도면이고, 도 4는 도 3의 선 4-4에 따른 도면이다. 기판(12)은 도 1 및 도 2의 관점에 대해 도 3의 관점에서 거꾸로 도시되어 있다. 따라서 면(13; 도 1 및 도 2에서 상면으로 언급함)은 도 3에서는 하면이다. 도 3에서, 면(13)은 제 1 면으로 언급될 것이다. 2 to 4, an enlarged portion of the
기판(12)은 제 1 면(13)에 대해 반대쪽인 제 2 면(15)을 포함한다. 반도체 재료를 포함하는 칩 또는 다이(14)가 한 쌍의 접착성 스트립(20)을 통해 면(15)에 부착된다. 접착성 스트립(20)은 예를 들어, 한 쌍의 대향 면(22, 24)을 갖는 테이프를 포함할 수 있고, 상기 대향 면 양쪽에는 접착제가 가해진다. 접착성 스트립(20)은 일반적으로 절연성 재료로 이루어진다. 와이어 본드부(28; 도 2에서 일부만이 도면부호가 표기됨)가 회로(16)로부터 슬릿(18)을 통해 연장하여 회로(16)를 칩(14)과 관련한 본딩 패드(25; 도 2에서 일부만이 도면부호가 표기됨)에 전기접속시키고, 따라서 회로(16)를 칩(14)으로 이루어진 회로와 전기접속시킨다. 칩(14)은 기판(12)의 면(15)과 마주하는 면(17)을 포함한다. 본딩 패드들은 면(17) 상에 있다(와이어 본드부와 본딩 패드는 간결하게 예시하기 위해 도 4에는 도시되지 않았다).The
도 5는 조립체(10)의 다른 처리 과정을 예시한다. 상세하게는, 도 5는 제 1 인캡슐런트(40; encapsulant)가 와이어 본드부(28) 상에 제공되고, 제 2 인캡슐런트(42)는 유닛(19, 21)과 관련한 칩(14) 상에 제공된 후의 도 1의 유닛(19, 21)을 예시한다. 제 1 및 제 2 인캡슐런트(40, 42)는 동일한 재료로 이루어질 수 있고, 일반적으로 예를 들어 경화 에폭시(cured epoxy)와 같은 절연성 재료로 이루어진 다. 5 illustrates another process of
전도성 볼(conductive ball;31)이 회로(16)의 일부분(도 1 및 도 2 참조)에 걸쳐 형성되어 회로(16)에 대해 볼 그리드 어레이(ball grid array)를 형성한다. 이러한 어레이는 차후에 회로(16)로부터 다른 회로(도시되지 않음)로의 다수의 상호 연결부를 형성하기 위해 사용될 수 있다. 전도성 볼(31)은 예를 들어, 주석, 구리 또는 금으로 형성될 수 있다.
기판(12)은 유닛(19, 21)을 각각 분리시키는 싱귤레이션(singulation) 공정을 거쳐 유닛(19, 21)으로부터 개개의 보드-온-칩을 형성한다. 싱귤레이션 공정은 예를 들어 인캡슐런트(42)와 기판(12)을 절단하는 것을 포함할 수 있다. The
보드-칩-패키지와 관련하여 와이어 본드부를 형성하는데 어려움이 발생할 수 있다. 이러한 와이어 본드부를 형성하는데 일반적으로 사용되는 방법 중에는, TESSERATM 공정과 소위 탭 본딩(tab bonding) 공정이 있다. 이러한 공정 중에서, 와이어-본딩에 사용되는 와이어는 처음에 일단부가 회로(16)에 접합된다. 와이어는 적어도 부분적으로 슬릿(18)에 걸쳐 연장하여 [회로(16)에 접합되지 않은] 제 2 단부가 슬릿(18) 상에 또는 슬릿을 지나 연장하도록 제공된다. 다음에, 로드(rod)를 사용하여 와이어를 슬릿(18) 안으로 누르고 초음파 용접 공정 중에 와이어를 칩(14)에 대해 고정한다. 초음파 용접 공정은 와이어의 제 2 단부를 본딩 패드(25) 에 접합시킨다. Difficulties may arise in forming the wire bond portion with respect to the board-chip-package. Among the methods generally used for forming such wire bond portions are the TESSERA ™ process and the so-called tab bonding process. In this process, the wire used for wire-bonding is first joined to the
와이어 본드부를 형성하는 다른 방법을 개발하는 것이 바람직할 수 있다.It may be desirable to develop other methods of forming wire bond portions.
본 발명의 일 특징은 반도체 칩 조립체를 형성하는 방법을 포함한다. 기판이 구비된다. 이러한 기판은 한 쌍의 대향면과, 이 대향면 중의 하나에 형성되는 회로를 갖는다. 반도체 칩이 기판에 결합된다. 반도체 칩은 그 위에 접합 영역을 갖는다. 다수의 와이어가 회로에 접합되고, 반도체 칩의 접합 영역 위로 연장한다. 와이어는 공구에 의해 반도체 칩의 접합 영역 주위로 눌려진다. 공구가 와이어로부터 들어올려진 다음에, 와이어가 반도체 칩의 접합 영역에 접합된다.One feature of the invention includes a method of forming a semiconductor chip assembly. A substrate is provided. Such a substrate has a pair of opposing faces and a circuit formed on one of the opposing faces. The semiconductor chip is coupled to the substrate. The semiconductor chip has a junction region thereon. A number of wires are bonded to the circuit and extend over the junction area of the semiconductor chip. The wire is pressed around the junction area of the semiconductor chip by the tool. After the tool is lifted from the wire, the wire is joined to the bonding region of the semiconductor chip.
본 발명의 다른 특징은 기판 상의 회로로부터 기판에 결합된 반도체 칩으로의 와이어 본드부를 형성하는 장치를 포함한다. 이러한 장치는 기판과 반도체 칩을 지지하기 위한 지지부를 포함한다. 상기 장치는 기판에 대해 움직일 수 있게 장착된 가압 공구를 더 포함하며, 가압 공구는 이 가압 공구가 기판을 향해 움직일 때 기판의 슬릿에 와이어를 누르도록 형성된 편향 면(deflecting surface)을 갖는다. 이 편향 면은 실질적으로 편평하고, 슬릿의 주요 부분 내에서 연장하기 충분한 길이를 갖는다. Another feature of the invention includes an apparatus for forming a wire bond portion from a circuit on a substrate to a semiconductor chip coupled to the substrate. Such an apparatus includes a support for supporting a substrate and a semiconductor chip. The apparatus further includes a pressing tool movably mounted relative to the substrate, the pressing tool having a deflecting surface configured to press the wire into the slit of the substrate when the pressing tool moves toward the substrate. This deflection face is substantially flat and has a length sufficient to extend within the main portion of the slit.
본원은 미국 특허법의 "과학과 유용한 기술의 발전을 촉진시키는(1조 8항)" 기본 목적을 촉진하기 위해 제출된 것이다. This application is submitted to promote the basic purpose of "promoting the development of science and useful technology" (art. 1, 8).
본 발명은 와이어 본드부를 형성하는 방법 및 장치를 포함한다. 도 6을 참조 하면, 본 발명의 장치(100)가 부분 사시도로 도시되어 있다. 본 발명의 장치(100)는 반도체 칩 조립체(104)를 지지하도록 구성된 지지부(102)와, 반도체 칩 조립체(104)와 관련하여 와이어를 이동시켜 와이어 본드부를 형성하는 공구(106)를 포함한다. The present invention includes a method and apparatus for forming a wire bond portion. Referring to FIG. 6, a
도시된 실시예에서, 반도체 칩 조립체(104)는 도 1 내지 도 5를 참조하여 본원의 배경기술 부분에서 설명한 타입의 종래 기술의 보드-온-칩 조립체의 일부분을 포함한다. 따라서, 조립체(104)는 기판(12), 반도체 재료 칩(14), 칩(14)을 기판(12)에 접합시키는 접착성 스트립(20)을 포함한다. 또한, 기판(12)은 회로(16)가 그 위에 형성되는 상면(13)과, 반도체 재료 칩(14)이 접합되는 하면(15)을 포함한다. 칩(14)은 그 위에서 본딩 패드(25)를 갖는 상면(17)을 갖는다[본딩 패드(25)는 간결하게 예시하기 위해 도 6에서는 도시하지 않았으나, 예를 들어 도 2에서 볼 수 있음]. 본딩 패드(25)는 일반적으로 예를 들어 본딩 와이어에 초음파로 용접될 수 있는 알루미늄과 같은 금속으로 이루어진다. 본딩 패드(25)는 영역(25)이 단순히 와이어 본드부가 칩(14)과 연결되는 영역이고 "패드"를 접합하는 것과 관련한 구조를 포함할 필요가 없음을 나타내기 위해, 본원에서 일반적으로 접합 영역으로 기술될 수 있다. In the illustrated embodiment, the
슬릿(18)은 기판(12)을 관통하여 연장되며, 특히 기판(12)의 상면(13)으로부터 기판(12)의 하면(15)으로 연장된다. 본딩 패드(25; 도 6에서 도시되지 않음)는 슬릿(18)을 통해 노출되어 있다. 다수의 본딩 와이어(28)(일부분만이 도면부호가 표시됨)는 회로(16)와 전기접속되고 적어도 부분적으로 슬릿(18)에 대해 연장된다. 와이어(28)의 회로(16)로의 전기접속은 양호하게는 와이어(28)를 회로(16)에 접합하는 형태로 이루어져, 각각의 와이어의 일단부가 회로(16)에 접합되고, 따라서 기판(12)의 상면(13) 상에서 접합된다. 각각의 와이어(28)는 고정되지 않은 제 2 단부를 가지며, 이러한 제 2 단부는 패드(25)에 접합되도록 형성된다. 도시된 실시예에서, 와이어(28)의 일부는 슬릿(18)에 대해 전체적으로 연장되고, 와이어(28)의 일부는 슬릿(18)을 가로질러 단지 부분적으로 연장된다. 본 발명의 특정한 실시예에서, 모든 와이어(28)가 슬릿(18)을 가로질러 전체적으로 연장되거나 또는 어떠한 와이어(28)도 슬릿(18)을 가로질러 전체적으로 연장되지 않을 수 있다. The
슬릿(18)은 직사각형 형상이고, 길이 "x"와 폭 "y"로 이루어진다. 또한, 슬릿(18)은 길이"x"만큼 서로 이격된 한 쌍의 단부(107, 109)를 포함한다. The
와이어(28) 중의 하나가 제 1 와이어(110)로 표시되어 있고, 단부(107)에 가장 가까운 와이어로 이루어진다. 와이어(28) 중 다른 하나가 제 2 와이어(112)로 표시되어 있고, 단부(109)에 가장 가까운 와이어로 이루어진다. 제 1 와이어(110)는 단부(107)로부터 소정의 갭(114)만큼 이격되어 있고, 제 2 와이어(112)는 단부(109)로부터 소정의 갭(116)만큼 이격되어 있다.One of the
공구(106)는 갭(18) 내에 들어가고 와이어(28)를 본딩 패드(25) 부근으로 누르도록 구성된 편향 면(120)을 포함한다["부근(about)"이라는 용어는 와이어가 본딩 패드(25)와 접촉하는 방식으로 완전히 눌려지거나 또는 와이어(28)가 패드(25) 위로 들어올려지는 거리 만큼 슬릿(18) 안으로 눌려질 수 있다는 것을 나타낸다]. 공구(106)는 도 6에 도시된 것과 거꾸로 도시된 도 7에 도시되어 있고, 도 7에서 편향 면(120)이 보다 명확하게 도시된다. 도 7은 편향 면(120)이 실질적으로 편평하며, 공구(106)가 각각 측벽(126, 128)을 통해 편향 면(120)에 연결되어 있는 다른 실질적으로 편평한 면(122, 124)을 포함한다는 것을 도시한다. 편평한 면(122, 124)은 바람직하게는 편향 면(120)이 슬릿(18) 내로 삽입될 때 면(13)[또는, 보다 상세하게는 상면(13) 상의 회로] 상에서 안착되도록 구성된다. 도시된 양호한 실시예에서, 측벽(126, 128)은 편평한 면(120, 122, 124)에 대해 비수직으로 연장된다. 이렇게 편평한 면에 대해 측벽(126, 128)이 비수직으로 연장되면, 와이어가 공구(106)에 의해 슬릿(18)으로 휘어질 때 와이어(28)에 타이트 코너(tight corner)가 형성되는 것을 피할 수 있다. 상기 용어 "타이트 코너"는 약 90°이하인 모서리를 언급하는데 사용된다. 타이트 코너는 와이어를 지나는 전류의 흐름을 감소시킬 수 있고, 와이어를 약화시켜 와이어가 파단되게 할 수 있다는 점에서 바람직하지 않을 수 있다.The
편향 면(120)은 바람직하게는 슬릿(18)의 길이 "x"와 거의 같은 길이인 길이 "z"를 갖는다. 길이 "z"는 바람직하게는 적어도 슬릿(18)의 주요 부분에 걸쳐 연장하기에 충분할 만큼 길며, 보다 바람직하게는 제 1 와이어(110)로부터 제 2 와이어(112)로 연장하기 충분할 만큼 길어서 공구가 슬릿(18)으로 이동할 때 다수의 와이어(28) 전체가 공구(106)에 의해 동시에 휘어진다. 특정한 실시예에서, 길이 "z"는 두 와이어(110, 112)[즉, 갭(114, 116)] 모두를 지나도록 연장하기에 충분할 만큼 길어서 슬릿(18)에 대한 면(120)의 사소한 오정렬(misalignment)을 보상해준다.The deflection face 120 preferably has a length "z" which is about the same length as the length "x" of the
도 6 및 도 7의 도면은 본 발명의 장치(100)를 분해도로 도시한다는 것을 주 의해야 한다. 양호한 실시예에서, 본 발명의 장치(100)는 기판으로부터 개개의 칩 패키지로 싱귤레이션하기 전에(싱귤레이션은 종래기술의 도 5와 관련하여 설명하였음) 사용된다. 본 발명의 장치(100)는 양호하게는 반복적인 다수의 공구(106)를 포함하며, 이 때 공구는 기판(12)에 걸쳐 반복적인 각각의 슬릿(18)에 대응하여(반복적인 슬릿은 종래기술의 도 1과 관련하여 설명하였음), 다수의 공구(106)를 다수의 슬릿(18)으로 이동시켜 전체 기판의 패널이 동시에 처리될 수 있다. 다른 실시예에서, 본 발명의 장치(100)는 기판 내의 슬릿(18)보다 적은 수의 공구(106)를 포함할 수 있고, 공구(106)는 기판 패널에 걸쳐 한 슬릿(18)에서 다른 슬릿으로 점차적으로 이동할 수 있다.It should be noted that the figures of FIGS. 6 and 7 show the
도 8을 참조하면, 도 6의 처리 단계 이후의 처리단계에서의 본 발명의 장치(100)가 도 6의 선 8-8에 따른 단면도로 도시된다. 공구(106)는 이제 슬릿(18)으로 이동되어 있어 편향 면(120)이 와이어(28)의 일단부를 칩(14)의 면, 상세하게는 본딩 패드(25) 상으로 누르고 있다[와이어(28)를 보다 명확히 예시하기 위해 공구(106)와 와이어(28) 사이에 소정의 갭이 있는 것으로 도시됨, 실제로는 공구(106)는 와이어(28)에 대해 눌리게 됨]. 비록 단 하나의 와이어(28)만이 휘어 있는 것이 도시되어 있으나, 바람직하게는 도 6의 모든 와이어(28)가 공구(106)를 슬릿(18)에 삽입함으로써 동시에 휘어진다. 도 8에는 편평한 면(122, 124)은 편향 면(120)이 와이어(28)를 패드(25)에 대해 휘게 할 때 회로(16) 상에 안착되도록 형성된다는 것을 또한 도시한다. 따라서, 면(122, 124)은 편향 면(120)에 의해 와이어(28)를 휘게할 때 와이어(28)의 회로(16)에 접합된 단부들을 고정하는 것을 돕는 다. 도 8은 측벽(126, 128)이 칩(14)의 실질적으로 편평한 면(17)에 대해 비수직으로 연장되는 것을 또한 도시한다. Referring to FIG. 8, the
도 9를 참조하면, 본 발명의 장치(100)가 도 8과 동일한 관점에서 도 8의 이후의 처리 단계 상태에서 도시된다. 상세하게는, 공구(106)가 들어올려져 슬릿(18) 내에서 편향 면(120)이 제거되고, 와이어(28)가 패드(25)에 접합된다. 도시된 실시예에서, 초음파 에너지(150)가 공급되어 와이어(28)를 패드(25)에 접합한다. 특정한 실시예에서, 패드(25)는 예를 들어 알루미늄 면으로 이루어질 수 있다; 와이어(28)는 예를 들어 금 또는 구리로 이루어질 수 있고; 초음파 에너지가 효과적으로 패드(25)와 와이어(28)에 방산(放散)되어 와이어(28)를 패드(25)에 용접시킬 수 있다. Referring to FIG. 9, the
양호한 실시예에서, 공구(106)는 와이어(28)를 패드(25)에 용접하기 위해 초음파 에너지를 공급하기 전에 슬릿(18)으로부터 완전히 제거된다. 이는 예를 들어 초음파 에너지를 공급하는 중에 와이어가 제위치에서 유지되는 TesseraTM 공정과 대조적이다. 또한, 본 발명은 슬릿에 걸쳐 연장하는 대부분, 바람직하게는 모든 와이어 본드부가 본 발명의 방법에 의해 동시에 휘게 된다는 점에서 탭 본딩 공정 및 TesseraTM 공정과는 상이하다. 대조적으로 TesseraTM 공정 및 탭 본딩 공정에서는, 와이어가 슬릿으로 순차적으로 휘어진다. In a preferred embodiment, the
비록 본 발명은 지금까지 보드-온-칩 반도체 제조 공정과 관련하여 설명되었 지만, 본 발명은 와이어가 반도체 칩을 회로에 와이어 본딩하는데 사용되는 다른 적용분야 뿐 아니라 와이어가 휘어지게 되는 다른 공정에도 적용될 수 있다. 비록 초음파 용접이 와이어(28)를 패드(25)에 접합시키는 방법으로 설명되었지만, 본 발명은 예를 들어 전도성 에폭시(conductive epoxy)를 사용하는 것을 포함하는, 와이어를 반도체 기판에 접합하는 다른 방법과도 함께 사용될 수 있다.Although the present invention has been described so far with respect to a board-on-chip semiconductor manufacturing process, the present invention is applicable to other processes where the wire is bent as well as other applications where the wire is used to bond the semiconductor chip to a circuit. Can be. Although ultrasonic welding has been described as a method of bonding the
법규에 따라, 본 발명은 구조적 및 방법적인 특징에 다소 한정된 용어로 설명되었다. 그러나, 본원에 공개된 수단은 본 발명을 실시하기에 양호한 형태를 포함하는 것이므로, 본 발명은 도시 및 설명된 특정적인 특징에 제한되지 않는다. 그러므로, 본 발명은 본원의 진의를 적절히 표현하는 첨부된 청구범위 내에서 임의의 형태로 수정될 수 있다.In accordance with legislation, the present invention has been described in terms that are somewhat limited in structural and methodological features. However, since the means disclosed herein are inclusive of the preferred forms for practicing the invention, the invention is not limited to the specific features shown and described. Therefore, the present invention may be modified in any form within the scope of the appended claims as appropriate to express the spirit of the application.
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- 1999-08-19 US US09/378,552 patent/US6199743B1/en not_active Expired - Lifetime
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2000
- 2000-08-18 KR KR1020067024581A patent/KR100721279B1/en not_active IP Right Cessation
- 2000-08-18 KR KR1020067024582A patent/KR100721280B1/en not_active IP Right Cessation
-
2001
- 2001-03-02 US US09/797,725 patent/US6454153B2/en not_active Expired - Fee Related
- 2001-03-02 US US09/797,790 patent/US6474532B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
KR20070009721A (en) | 2007-01-18 |
US6454153B2 (en) | 2002-09-24 |
US20010008247A1 (en) | 2001-07-19 |
US20010035451A1 (en) | 2001-11-01 |
KR100721279B1 (en) | 2007-05-28 |
KR20070007194A (en) | 2007-01-12 |
US6199743B1 (en) | 2001-03-13 |
US6474532B2 (en) | 2002-11-05 |
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