JP2003031605A - Semiconductor module manufacturing method - Google Patents

Semiconductor module manufacturing method

Info

Publication number
JP2003031605A
JP2003031605A JP2001218156A JP2001218156A JP2003031605A JP 2003031605 A JP2003031605 A JP 2003031605A JP 2001218156 A JP2001218156 A JP 2001218156A JP 2001218156 A JP2001218156 A JP 2001218156A JP 2003031605 A JP2003031605 A JP 2003031605A
Authority
JP
Japan
Prior art keywords
wire loop
wire
loop
semiconductor module
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001218156A
Other languages
Japanese (ja)
Inventor
Koichi Tsurusako
浩一 鶴迫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2001218156A priority Critical patent/JP2003031605A/en
Publication of JP2003031605A publication Critical patent/JP2003031605A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/4556—Disposition, e.g. coating on a part of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a wire loop which is formed in a high position does not suit with the downsizing of a product and the wire loop which is formed in a low position may cause insulation failure due to the contact or deterioration of quality caused by an increase in bending stress. SOLUTION: When a semiconductor module is manufactured by wire-bonding a semiconductor chip (1) or the like, another wire loop (4) for supporting the wire loop (2) is previously formed for avoiding the contact between the wire loop (2) and components near the loop (2) and for ensuring the desirable height of the wire loop (2).

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】この発明は、半導体モジュー
ルの製造方法に関し、特に信頼性の高いワイヤボンディ
ングを行える半導体モジュール製造方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor module, and more particularly to a method for manufacturing a semiconductor module capable of highly reliable wire bonding.

【０００２】[0002]

【従来の技術】図１に半導体モジュール１の側面図およ
び平面図を示している。２はこの半導体モジュール１内
での回路配線のためにワイヤボンドにより形成したワイ
ヤループであり、両接続点の間で段差があるため、その
エッジ部３のあたりでワイヤループ２と接触したり、規
定以上に離隔できないため、絶縁不良を引き起こす懸念
がある。2. Description of the Related Art FIG. 1 shows a side view and a plan view of a semiconductor module 1. Reference numeral 2 is a wire loop formed by wire bonding for circuit wiring in the semiconductor module 1. Since there is a step between both connection points, the wire loop 2 contacts the wire loop 2 around the edge portion 3, There is a concern that insulation failure may occur because the distance cannot exceed the specified value.

【０００３】[0003]

【発明が解決しようとする課題】そのような絶縁不良の
発生を避けるためには、接触が懸念される個所からワイ
ヤループを十分に高くして形成するのが有効となる。し
かし、この手法は製品小型化の観点から好ましくなく、
また、後工程で何らかの力が作用してワイヤループが押
し込まれた場合には、結局部品との接触が起こることに
なり、根本的な解決にはなっていない。In order to avoid the occurrence of such insulation failure, it is effective to form the wire loop at a sufficiently high position from the point where contact is a concern. However, this method is not preferable from the viewpoint of product miniaturization,
Further, when some force acts on the wire loop in the subsequent process, the wire loop eventually comes into contact with the component, which is not a fundamental solution.

【０００４】一方、製品小型化の観点からワイヤループ
の低い方が有利ではあるが、その場合には、部品との接
触が懸念されるだけでなく、ワイヤループに大きな曲げ
応力が作用するため、製品の温度サイクル寿命や耐振強
度などで不利となり、ワイヤボンドのネック強度に問題
が生じた。このようにいずれの場合でも課題があった。On the other hand, it is advantageous to have a low wire loop from the viewpoint of product miniaturization, but in that case, not only is there concern about contact with parts, but also a large bending stress acts on the wire loop, It was disadvantageous in terms of temperature cycle life and vibration resistance of the product, causing problems in the wire bond neck strength. Thus, there were problems in both cases.

【０００５】この発明は、信頼性の高いワイヤボンデン
グを行える半導体モジュールの製造方法を提供するもの
である。The present invention provides a method of manufacturing a semiconductor module capable of performing highly reliable wire bonding.

【０００６】[0006]

【課題を解決するための手段】請求項１に係わる半導体
モジュール製造方法は、半導体チップ等にワイヤボンド
を施して半導体モジュールを製造する際、ワイヤループ
とループ近傍にある部品との接触を回避し、望ましいワ
イヤループ高さを確保するために、ワイヤループを下支
えする別のワイヤループを先行して形成しておくことを
特徴とする。A semiconductor module manufacturing method according to a first aspect of the present invention avoids contact between a wire loop and a component near the loop when manufacturing a semiconductor module by wire-bonding a semiconductor chip or the like. In order to secure a desired wire loop height, another wire loop that supports the wire loop is formed in advance.

【０００７】請求項２に係わる半導体モジュール製造方
法は、半導体チップ等にワイヤボンドを施して半導体モ
ジュールを製造する際、ワイヤループの高さを低く制御
するために、ワイヤループ形成後に、そのワイヤループ
を押さえ込むための別のワイヤループを形成することを
特徴とする。According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor module, wherein when a semiconductor module is manufactured by wire bonding to a semiconductor chip or the like, the height of the wire loop is controlled to be low so that the wire loop is formed and then the wire loop is formed. Another wire loop for holding down is formed.

【０００８】請求項５に係わる半導体モジュール製造方
法は、半導体チップ等にワイヤボンドを施して半導体モ
ジュールを製造する際、ワイヤループの高さを低く制御
するために、ワイヤループ形成後に、そのワイヤループ
を治具を用いて押さえ込むことを特徴とする。According to a fifth aspect of the present invention, there is provided a semiconductor module manufacturing method, wherein when a semiconductor module is manufactured by wire-bonding a semiconductor chip or the like, in order to control the height of the wire loop to be low, the wire loop is formed and then the wire loop is formed. It is characterized by pressing down with a jig.

【０００９】[0009]

【発明の実施の形態】実施形態１ 図１のように段差のある個所にワイヤループ２を形成す
るとき、本実施形態１では図２に示すように、ワイヤル
ープ２を形成する前に、半導体モジュール１の構成部品
とワイヤループ２との接触が懸念される個所の近傍に、
ワイヤループ２を下方から支持するためのワイヤループ
(以下、枕木ワイヤと称する)４を形成しておく。これに
より、ワイヤループ２の変形が防止され、構成部品との
接触を回避できる。この枕木ワイヤ４を図２の下図に示
したように複数本形成すれば、ワイヤループ２の高さを
より忠実に保持することができ、構成部品との接触を確
実に回避できる。BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment When forming a wire loop 2 at a stepped portion as shown in FIG. 1, in the first embodiment, as shown in FIG. In the vicinity of the place where the contact between the component parts of the module 1 and the wire loop 2 is concerned,
Wire loop for supporting the wire loop 2 from below
(Hereinafter, referred to as sleeper wire) 4 is formed. As a result, the wire loop 2 is prevented from being deformed, and contact with the component parts can be avoided. If a plurality of the sleeper wires 4 are formed as shown in the lower diagram of FIG. 2, the height of the wire loop 2 can be more faithfully maintained and contact with the constituent parts can be reliably avoided.

【００１０】尚、特開平7-142523 および特開平10-2943
27 では、本発明と同じ課題を解決すべく、前者では、
２本の円柱による支持体を設け、後者ではお椀形状の網
状体を形成しているが、この場合には、それのために別
に設計して製作しておく必要があり、製作コストがかか
り、又、あらゆる製品にフレキシブルに対応させようと
した場合にそれらの支持体が別の構造物と干渉してしま
うなどからその支持体を再設計しなければならない必要
性が高く、汎用性の面で問題がある。Incidentally, JP-A-74-2523 and JP-A-10-2943
Then, in order to solve the same problem as the present invention, in the former,
A support body consisting of two cylinders is provided, and in the latter case, a bowl-shaped net-like body is formed, but in this case, it is necessary to separately design and manufacture for that, which is costly to manufacture. In addition, since it is necessary to redesign the support because it will interfere with other structures when trying to flexibly support all products, it is highly versatile. There's a problem.

【００１１】一方、本発明では、製品の配線に使用する
ワイヤをそのまま支持体として使用するため、同一のワ
イヤボンド装置で一連のワイヤボンド作業中に実施で
き、かつ、ワイヤボンド位置や寸法もワイヤボンドプロ
グラム次第で自由に設計できる。On the other hand, in the present invention, since the wire used for the wiring of the product is used as it is as a support, it can be carried out during a series of wire bonding operations with the same wire bonding apparatus, and the wire bonding position and size can also be determined. You can design freely depending on the bond program.

【００１２】実施形態２ 既述したように、接触が懸念される部分から十分に高く
してワイヤループを形成すれば、接触による絶縁不良が
回避され、曲げ応力の低減により製品の信頼性が高まる
が、その反面、製品小型化で不利となる。そこで本実施
形態２では、図３に示すように、ワイヤループ２のトッ
プ部に対し、押さえワイヤ７により、ワイヤループ２を
上方から押し込んでワイヤループ２のトップ部の高さを
抑制しており、接触が懸念される個所では、その個所で
の高さをそのまま維持している。この手法であれば、ワ
イヤループ高さを低くでき、かつ、曲げ応力も大きくな
らないため、製品信頼性が確保される。押さえワイヤ７
を複数設置することにより、ワイヤループ２の高さをよ
り的確に抑制することができ、又、上述の枕木ワイヤ４
や枕木治具６を併用すれば更に抑制効果が期待できる。Embodiment 2 As described above, if the wire loop is formed sufficiently high from the portion where contact is concerned, insulation failure due to contact can be avoided, and bending stress can be reduced to improve product reliability. However, on the other hand, there is a disadvantage in product miniaturization. Therefore, in the second embodiment, as shown in FIG. 3, the top portion of the wire loop 2 is pressed down from above by the pressing wire 7 to suppress the height of the top portion of the wire loop 2. At locations where contact is a concern, the height at that location is maintained. With this method, the wire loop height can be reduced and the bending stress does not increase, so that the product reliability is ensured. Presser wire 7
By installing a plurality of wires, the height of the wire loop 2 can be suppressed more accurately, and the above-mentioned sleeper wire 4
Further suppression effect can be expected if the sleeper jig 6 is used together.

【００１３】実施形態３ 実施形態２では、ワイヤループ２の押さえ込みに押さえ
ワイヤ７を用いたが、本実施形態３では、図４に示すよ
うに、押さえ治具８を用いて形成済みのワイヤループ２
を上方から押さ込んで変形させている。又、上述の枕木
ワイヤ４や枕木治具６を併用すれば更に抑制効果が期待
できる。Third Embodiment In the second embodiment, the holding wire 7 is used to hold the wire loop 2, but in the third embodiment, as shown in FIG. 4, the wire loop already formed by using the holding jig 8 is formed. Two
Is deformed by pushing in from above. Further, if the sleeper wire 4 and the sleeper jig 6 described above are used together, a further suppressing effect can be expected.

【００１４】[0014]

【発明の効果】請求項１に係わる発明は、ワイヤループ
を下支えする別のワイヤループを形成したので、ワイヤ
ループとループ近傍にある部品との接触を回避し、望ま
しいワイヤループ高さを確保できる。According to the invention of claim 1, since another wire loop for supporting the wire loop is formed, contact between the wire loop and a part in the vicinity of the loop can be avoided, and a desired wire loop height can be secured. .

【００１５】請求項２に係わる発明は、形成したワイヤ
ループのトップ部を別のワイヤループで押さえ込むた
め、ワイヤループを所望の高さに制御でき、ワイヤルー
プとループ近傍にある部品との接触を回避できる。According to the second aspect of the present invention, since the top portion of the formed wire loop is pressed by another wire loop, the wire loop can be controlled to a desired height and the contact between the wire loop and a part in the vicinity of the loop can be controlled. It can be avoided.

【００１６】これらの別のワイヤループは、本来のワイ
ヤループを形成するのと同一のワイヤボンド装置を用い
て形成でき、また、この形成を一連のワイヤボンド作業
中に行なえるため、特別な工程を設定する必要はなく、
汎用性も高い。These additional wire loops can be formed using the same wirebonding equipment that forms the original wire loops, and this formation can be performed during a series of wirebonding operations, thus requiring a special process. You don't have to set
High versatility.

【００１７】請求項５に係わる発明は、形成したワイヤ
ループを治具を用いてトップ部を押さえ込むようにした
ものであり、ワイヤループを所望の高さに制御でき、ワ
イヤループとループ近傍にある部品との接触を回避でき
る。According to a fifth aspect of the present invention, the formed wire loop is pressed down on the top portion by using a jig, the wire loop can be controlled to a desired height, and the wire loop is located in the vicinity of the loop. It is possible to avoid contact with parts.

【００１８】ワイヤループを高い目に形成し(つまり曲
げ応力を低くし)、そのトップ部を別のワイヤループ(請
求項２)または治具(請求項５)を用いて押さえ込む場合
には、その曲げ応力を殆ど変化させることなく、ワイヤ
ループの高さを抑制できるため、製品小型化および製品
の信頼性向上を達成できる。When the wire loop is formed in a high eye (that is, the bending stress is made low) and the top portion is pressed by another wire loop (Claim 2) or a jig (Claim 5), the Since the height of the wire loop can be suppressed with almost no change in bending stress, product miniaturization and product reliability improvement can be achieved.

【図面の簡単な説明】[Brief description of drawings]

【図１】 従来のワイヤボンドで生じる不具合を示した
図FIG. 1 is a diagram showing a problem caused by a conventional wire bond.

【図２】 本発明の第１実施形態を示した図FIG. 2 is a diagram showing a first embodiment of the present invention.

【図３】 本発明の第２実施形態を示した図FIG. 3 is a diagram showing a second embodiment of the present invention.

【図４】 本発明の第３実施形態を示した図FIG. 4 is a diagram showing a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体モジュール、２ ワイヤループ、４ 枕木ワ
イヤ、７ 押さえワイヤ、８ 押さえ治具1 semiconductor module, 2 wire loop, 4 sleeper wire, 7 retaining wire, 8 retaining jig

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップ等にワイヤボンドを施して
半導体モジュールを製造する際、ワイヤループとループ
近傍にある部品との接触を回避し、望ましいワイヤルー
プ高さを確保するために、ワイヤループを下支えする別
のワイヤループを先行して形成しておくことを特徴とす
る半導体モジュール製造方法。1. When manufacturing a semiconductor module by wire-bonding a semiconductor chip or the like, a wire loop is formed in order to avoid contact between the wire loop and parts in the vicinity of the loop and to secure a desired wire loop height. A method of manufacturing a semiconductor module, characterized in that another wire loop that supports the semiconductor device is formed in advance. 【請求項２】 半導体チップ等にワイヤボンドを施して
半導体モジュールを製造する際、ワイヤループの高さを
低く制御するために、ワイヤループ形成後に、そのワイ
ヤループを押さえ込むための別のワイヤループを形成す
ることを特徴とする半導体モジュール製造方法。2. When manufacturing a semiconductor module by wire-bonding a semiconductor chip or the like, another wire loop for pressing down the wire loop is formed after the wire loop is formed in order to control the height of the wire loop to be low. A method of manufacturing a semiconductor module, which comprises: 【請求項３】 上記別のワイヤループは、本来のワイヤ
ループを形成するのと同一のワイヤボンド装置を用いて
形成する請求項１または２に記載の半導体モジュール製
造方法。3. The method of manufacturing a semiconductor module according to claim 1, wherein the another wire loop is formed by using the same wire bonding apparatus as that used to form the original wire loop. 【請求項４】 上記別のワイヤループは、本来のワイヤ
ループを形成するのと同一のワイヤボンド装置を用い、
一連のワイヤボンド作業中に行う請求項１〜３のいずれ
かに記載の半導体モジュール製造方法。4. The other wire loop uses the same wire bonding device as the original wire loop,
The semiconductor module manufacturing method according to claim 1, which is performed during a series of wire bonding operations. 【請求項５】 半導体チップ等にワイヤボンドを施して
半導体モジュールを製造する際、ワイヤループの高さを
低く制御するために、ワイヤループ形成後に、そのワイ
ヤループを治具を用いて押さえ込むことを特徴とする半
導体モジュール製造方法。5. When manufacturing a semiconductor module by wire-bonding a semiconductor chip or the like, in order to control the height of the wire loop to be low, it is necessary to press the wire loop with a jig after forming the wire loop. A method for manufacturing a semiconductor module, which is characterized.
JP2001218156A 2001-07-18 2001-07-18 Semiconductor module manufacturing method Pending JP2003031605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001218156A JP2003031605A (en) 2001-07-18 2001-07-18 Semiconductor module manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001218156A JP2003031605A (en) 2001-07-18 2001-07-18 Semiconductor module manufacturing method

Publications (1)

Publication Number Publication Date
JP2003031605A true JP2003031605A (en) 2003-01-31

Family

ID=19052379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001218156A Pending JP2003031605A (en) 2001-07-18 2001-07-18 Semiconductor module manufacturing method

Country Status (1)

Country Link
JP (1) JP2003031605A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015204878A1 (en) 2014-03-20 2015-09-24 Mitsubishi Electric Corporation Power semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015204878A1 (en) 2014-03-20 2015-09-24 Mitsubishi Electric Corporation Power semiconductor device

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