JPH0229560U - - Google Patents

Info

Publication number
JPH0229560U
JPH0229560U JP10803488U JP10803488U JPH0229560U JP H0229560 U JPH0229560 U JP H0229560U JP 10803488 U JP10803488 U JP 10803488U JP 10803488 U JP10803488 U JP 10803488U JP H0229560 U JPH0229560 U JP H0229560U
Authority
JP
Japan
Prior art keywords
rows
mounting
mini
flat
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10803488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10803488U priority Critical patent/JPH0229560U/ja
Publication of JPH0229560U publication Critical patent/JPH0229560U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す部品取付け面
の平面図、第2図は従来の印刷配線板の部品取付
け面の平面図である。 1…プリント板、2…ミニフラツトICの取付
ランド、3,4,6…スルーホール、5…配線。
FIG. 1 is a plan view of a component mounting surface showing an embodiment of the present invention, and FIG. 2 is a plan view of a component mounting surface of a conventional printed wiring board. 1... Printed board, 2... Mini flat IC mounting land, 3, 4, 6... Through hole, 5... Wiring.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数列に配列されるミニフラツト型ICを取り
つける複数個の取付ランドと、前記取付けランド
の複数列の列と列との間および前記複数列の最外
列の外側に配置された所定単位長の整数倍の間隔
を有するベアボードテストおよびインサーキツト
テスト用の複数個のスルーホールとを備え、前記
ミニフラツト型ICの取付け面と反対の面を被覆
した絶縁膜のうち前記複数個のスルーホールの位
置する個所の前記絶縁膜のみを取り除いたことを
特徴とする印刷配線板。
a plurality of mounting lands for mounting mini-flat ICs arranged in a plurality of rows, and an integer of a predetermined unit length arranged between the plurality of rows of the mounting lands and outside the outermost row of the plurality of rows. A plurality of through holes for bare board testing and in-circuit testing are provided with twice the spacing, and the portions of the insulating film covering the surface opposite to the mounting surface of the mini-flat IC are located where the plurality of through holes are located. A printed wiring board characterized in that only the insulating film is removed.
JP10803488U 1988-08-16 1988-08-16 Pending JPH0229560U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10803488U JPH0229560U (en) 1988-08-16 1988-08-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10803488U JPH0229560U (en) 1988-08-16 1988-08-16

Publications (1)

Publication Number Publication Date
JPH0229560U true JPH0229560U (en) 1990-02-26

Family

ID=31342989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10803488U Pending JPH0229560U (en) 1988-08-16 1988-08-16

Country Status (1)

Country Link
JP (1) JPH0229560U (en)

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