JPH0229553U - - Google Patents
Info
- Publication number
- JPH0229553U JPH0229553U JP10755588U JP10755588U JPH0229553U JP H0229553 U JPH0229553 U JP H0229553U JP 10755588 U JP10755588 U JP 10755588U JP 10755588 U JP10755588 U JP 10755588U JP H0229553 U JPH0229553 U JP H0229553U
- Authority
- JP
- Japan
- Prior art keywords
- board
- back side
- utility
- scope
- registration request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Structure Of Printed Boards (AREA)
Description
第１図ａ〜ｃは本考案による第１の実施例を示
す図であり、第１図ａは概略斜視図、第１図ｂは
基板裏面の配線図、第１図ｃは第１図ａのＡ―Ａ
′線に沿つて切断し矢印の方向に見た断面図、第
２図は本考案による第２の実施例を示す断面図、
第３図ａ，ｂは従来例を示す図であり、第３図ａ
は基板配線裏面図、第３図ｂは第３図ａのＢ―Ｂ
′線に沿つて切断し矢印の方向に見た断面図であ
る。
１…ソケツト、２…セラミツク基板Ａ、３…ガ
ラス、４…セラミツク基板Ｂ、５…基板電極、６
…薄膜抵抗、７…金属配線、８…スルーホール、
９…ソケツト電極、１０…基板、１１…抵抗、１
２…導線、１３…半田。
1A to 1C are views showing a first embodiment of the present invention, FIG. 1A is a schematic perspective view, FIG. 1B is a wiring diagram of the back side of the board, and FIG. A-A of
2 is a sectional view showing a second embodiment of the present invention,
Figures 3a and 3b are diagrams showing a conventional example, and Figure 3a
Figure 3b is the back view of the board wiring, and Figure 3b is B-B of Figure 3a.
FIG. DESCRIPTION OF SYMBOLS 1...Socket, 2...Ceramic substrate A, 3...Glass, 4...Ceramic substrate B, 5...Substrate electrode, 6
...Thin film resistor, 7...Metal wiring, 8...Through hole,
9... Socket electrode, 10... Substrate, 11... Resistor, 1
2...Conducting wire, 13...Solder.
Claims (1)
を特徴とするバイアス試験基板。 A bias test board characterized by having a hermetically sealed wiring section on the back side of the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10755588U JPH0229553U (en) | 1988-08-15 | 1988-08-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10755588U JPH0229553U (en) | 1988-08-15 | 1988-08-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0229553U true JPH0229553U (en) | 1990-02-26 |
Family
ID=31342076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10755588U Pending JPH0229553U (en) | 1988-08-15 | 1988-08-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0229553U (en) |
-
1988
- 1988-08-15 JP JP10755588U patent/JPH0229553U/ja active Pending