JPH02292858A - Formation of complementary thin film transistor - Google Patents

Abstract

PURPOSE:To enable the formation of a complementary thin film transistor provided with a source and a drain region of high concentration on a single substrate of large area without using an ion implantation method by a method wherein a P-type Si film and an N-type Si film are deposited in lamination, the upper N-type Si film is removed from the source and the drain forming region of a P channel TFT, and other processes are executed. CONSTITUTION:A P-type silicon thin film 102 and an N-type silicon thin film 103 are formed in lamination on an insulating substrate 101, and the two-layered film is removed keeping source or drain forming sections 105 of an N channel thin film transistor and a P channel transistor thin film transistor unremoved by the use of a resist 104 as a mask. Then, the N-type silicon thin film 103 on the patterned P-type silicon thin film 102 of the source or the drain forming section of the P channel thin film transistor is removed through etching, resist patterns 104 and 106 are removed, then the N-type and the P-type silicon thin film, 102 and 103, are thermally treated to be polycrystallized, an active silicon thin film region 107 are deposited on the whole face and patterned, and a gate insulating film 108 is formed thereon. Next, a gate electrode 109 is formed and an interlaminar insulating film 110 is formed on the whole face.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a thin film transistor formed on an insulating substrate, and particularly to a method for forming a complementary thin film transistor.

[Conventional technology]

In recent years, with the aim of achieving high display quality, thin film transistors have been developed.
o r, hereinafter referred to as TPT. ) is currently being researched and developed for each pixel. In order to realize a large-area, high-definition active matrix type liquid crystal display at low cost, it is necessary to increase the cost of peripheral circuits and mounting, so that a peripheral drive circuit that drives the active matrix and a transistor (pixel transistor) provided for each pixel must be used. It is desired to simultaneously form both on a single substrate. On the other hand, peripheral drive circuits are required to operate at high speed. TPT using amorphous silicon, which has been widely used in active matrix pixel transistors, has low mobility and therefore requires high-speed operation.
This was insufficient for peripheral drive circuits. Therefore, development of TPTs using polycrystalline silicon, which has high mobility, has been actively conducted.

Regarding peripheral drive circuits, complementary concave circuits (Compβementar) have a large operating margin and low operating power.
yMetaff Oxide Semicon
ductor: Hereinafter referred to as CMOS.

) configuration is preferred. The CMOS configuration is a circuit that combines an n-channel TPT and a p-channel TPT, and in order to realize this, it is necessary to simultaneously form the n-channel TPT and the p-channel TPT on a single substrate.

For example, as a conventional prior art, there is a document (A. Clpri
“A 600-650゜CPonysi l” by others
icon CMOS Process
For Fabricating Ful. 1y
Scanned Active-Matrix
LCD's Proceeding o
f thesID vof. 29/2.1988, it is reported that a peripheral drive circuit for matrix drive is formed using CMOS trenches.

Here, an impurity doping method using ion implantation is used to form the source and drain regions of the TPT. Immediately introduce impurities through ion implantation to create a high concentration of n.
The method of forming source and drain regions by forming p-type or p-type regions is a method widely used in the manufacturing process of integrated circuits using silicon substrates. However, currently available ion implanters cannot use the large-area substrates required for practical liquid crystal displays, and even if it were possible to develop an ion implanter for such large-area substrates, the equipment cost would be high. Therefore, the method of adding impurities by ion implantation has the disadvantage that it cannot be practically applied to active matrix fabrication.

On the other hand, as a method that does not use ion implantation, there is a method that uses a silicon film containing a high concentration of impurities in the source and drain regions of the TPT. For example, literature is an example of conventional prior art. Y. ``Growdischa'' written by I-1irai et al.
rge PolycrysLaj26ine Si
licon ThinFilm Transist
ors, App/. Phys, Lett. 42f8
). 15 April 1983 reports an n-channel TPT using an n-type silicon film for the source and drain regions. However, there have been no reports of realizing a CMOS configuration.

[Problem to be solved by the invention]

It is an object of the present invention to provide a method for forming complementary thin film transistors with highly doped source and drain regions on a single large area substrate without using ion implantation techniques. More specifically, it is an object of the present invention to provide a method for forming source and drain regions of a sum-complementary thin film transistor using a silicon film containing a high concentration of impurities.

[Means to solve the problem]

In order to apply the formation method in which source and drain regions are made of silicon films doped with high concentrations of impurities to a CMOS structure, a region in which an RL-type silicon film is formed and a region in which a p-type silicon film is formed are separated on a substrate. It is necessary to provide

One of the important points of the present invention is that the impurities contained in
This method takes advantage of the fact that the etch rate of the silicon film differs depending on the I. For example, literature, K. H. NichoAs
``Fabrication of subrn'' by other authors
icron po#ysi I! icon
j2ines by conventtona
A technique”, AppliedPh
ysics Letters, voff, 26 No.
7, p. 398-399, I Aprif1 9
7 5. Boron (B) as an impurity as seen in
The etching and notching speed of p-type silicon films containing a high concentration of phosphorus (P) can be improved by using an etching solution such as an aqueous solution of ethylamine and pyrocatechol. is known to be extremely small compared to

The present invention makes use of the above etching characteristics to stack and deposit a p-type silicon film with a low etching/notching rate and an n-type silicon film with a high etching rate, thereby forming a source and drain region in a region where a p-channel TPT is formed. In some parts, the upper n-type silicon film is removed and only the p-type silicon film is used as the source and drain regions, and in the region where the n-channel TPT is formed, the two-layer film is used as the source and drain regions.

Further features of the invention will become apparent in the following description of the examples.

[Embodiment] FIGS. 1(a), (b), (C) and (d) illustrate schematic cross-sectional views of a method for forming a complementary thin film transistor according to an embodiment of the present invention.

As shown in FIG. 1 ta), a glass insulating substrate 101
For example, plasma vapor deposition (Pffasrna)
Chemical Vapor Deposit
ion, hereinafter referred to as PCVD. ) p-type amorphous silicon doped with boron (B) using the method
102 to a thickness of approximately 150 nm, followed by the same PCV
N-type amorphous silicon [103] doped with phosphorus (P) was deposited to a thickness of about 150 nm using method D. Next, as shown in FIG. 1 (bl), a source and drain pattern is formed by patterning using a resist 104, and then the two-layer film is patterned into the shape of the source and drain using CC1zF2 gas or an active ion etching method. 105. Here, 105 is a two-layer film of the p-type amorphous silicon film 102 and the n-type amorphous silicon film 103, and is the source and drain region of the complementary thin film transistor. Next, as shown in FIG. As shown in FIG.
The n-type silicon film on the regions to be formed as the source and drain regions of the p-channel TPT was removed using an aqueous solution containing 17 mj of ethylenediamine, 3 ml of water F, and 3 g of pyrocatechol kept at 50°C. Here, as shown in FIG. 1(C), the register 1
- One mask is required for patterning pattern 106. This is only one extra mask compared to the number of masks required when manufacturing a conventional n-channel or p-channel TPT as a single device. Hereinafter, in the same way as the conventional TPT manufacturing method, the p-type and n-type amorphous silicon films were heat-treated at a temperature of 600°C to polycrystallize them to lower their resistance, as shown in FIG. A polycrystalline silicon film of about 150 nm that does not contain impurities is deposited and processed into an island shape to form a TPT to form an active region 107 by patterning.
8 is deposited, a gate electrode 109 is formed by patterning with a polycrystalline silicon film of about 400 nm, an interlayer insulating film 110 is deposited, a through hole is formed, and an electrode wiring 111 in the source or drain region is formed of aluminum. .

The method of forming a complementary iHlff transistor according to the present invention has been explained by the combination of steps illustrated in FIGS. 1(al, (b).(Cl) and (di). This is a schematic cross-sectional view of a completed device formed by the complementary thin film transistor formation method.

In the n-channel T F"T of the complementary thin film transistor formed in this way, the source and drain regions are formed of a two-layer film of a p-type silicon film and an n-type silicon film, but the impurity concentration of the n-type silicon film is By forming the impurity concentration higher than that of the p-type silicon film, n-type impurities are mixed into the p-type silicon film during annealing at 600°C to lower the resistance of the source and drain regions, resulting in secondary p-channel formation. It has also been found that the film can be prevented from moving.For this reason, the
It has also been found that the characteristics of channel and n-channel TPTs are the same as those of TPTs made solely using p-type silicon films and n-type silicon films as sources and drains.

In one embodiment of the present invention as described above, the n-type and p-type silicon films are formed by polycrystallizing amorphous silicon by the PCVD method.
w Pressure Chemica IV
apour Deposition, LPCVD)
A similar effect has been obtained using a polycrystalline silicon film produced by the LPCVD method, and therefore, it goes without saying that n-type and p-type polycrystalline silicon produced by the LPCVD method may also be used.

According to the forming method of the present invention, it is possible to manufacture a phase-type thin film I transistor extremely easily, and the number of masks can be reduced by a single TPT.
Only one additional sheet is required compared to . Therefore, the method for forming complementary thin film transistors of the present invention is very useful for application to thin film integrated circuits such as low power consumption and high speed large area active matrix liquid crystal displays. In addition, the method of depositing the silicon film is not limited to the above-mentioned PCVD method and LPCVD method, and other deposition methods such as photo-CVD may be used.
) Of course it's a good thing.

〔Effect of the invention〕

According to the present invention, complementary thin film transistors can be formed without using ion implantation, so the peripheral drive circuit that drives the matrix and the transistors provided for each pixel are not limited to the basic size that can be handled by an ion implantation device. , can be simultaneously formed on a single large-area substrate, and p
Complementary thin film by adding just one photomask to the photomask for channel or n-channel single TPT fabrication! - It has the advantage of being able to form a transistor, and has the characteristic of being able to realize peripheral drive circuits that require low power consumption and high-speed operation.

Therefore, according to the present invention, a large-area, high-definition active matrix liquid crystal display with high display quality and its high-speed, low-power consumption peripheral drive circuit can be simultaneously formed on a single substrate at low cost, which is extremely industrially possible. It is of high value.

[Brief explanation of drawings]

1(a) to (dl) illustrate a method for forming a complementary thin film transistor of the present invention. 101...Glass insulating substrate, 102...P-type silicon film, 103...N-type silicon film, 104 . . . Resist for source and drain/in patterns, 105 . . Patterned 2M film for source or drain formation portion, 106 . . Resist pattern, 107 . . . Active polycrystalline silicon region, . . Gate Insulating film, ...gate electrode, ...interlayer insulating film, ...source and drain wiring Patent applicant Kuchiki Telegraph and Telephone Co., Ltd. Patent attorney Kugoro Tamamushi

Claims (1)

[Claims] 1. A method for forming a complementary thin film transistor consisting of an n-channel thin film transistor and a p-channel thin film transistor formed on an insulating substrate, the method comprising: forming a p-type silicon thin film on the insulating substrate; a first step; a second step of forming an n-type silicon thin film on the p-type silicon thin film; and a second step of forming the p-type silicon thin film and the n-type silicon thin film.
a third step of removing the layer film using a resist as a mask, leaving only the source or drain forming portions of the predetermined n-channel thin film transistors and the p-channel thin film transistors; a fourth step of etching away the n-type silicon thin film on the silicon thin film, and after removing the resist pattern, heat-treating the n-type and p-type silicon thin films to polycrystallize and lower the resistance, and then removing the active silicon thin film region. After the entire surface is deposited and patterned, a fifth step of forming a gate insulating film on the active silicon thin film region, and forming a gate insulating film on the active silicon thin film regions of the p-channel thin film transistor and the n-channel thin film transistor by patterning through the insulating film. a sixth step of forming a gate electrode; a seventh step of forming an interlayer insulating film on the entire surface after the sixth step; and a seventh step of forming an interlayer insulating film on the entire surface after the sixth step; an eighth step of forming a window in the p-type silicon thin film and forming a window in the polycrystallized n-type silicon thin film that will become the source and drain forming portions of the n-channel thin film transistor; and the sources of the two transistors. Alternatively, a complementary thin film transistor forming method characterized in that the thin film transistor is formed in combination with a ninth step of forming an electrode wiring in a drain region. 2. In a method for forming a complementary thin film transistor formed on an insulating substrate, a two-layer film consisting of a p-type silicon thin film and an n-type silicon thin film is formed, and only the region that will become the source or drain of the p-channel transistor is 2. The method of forming a complementary thin film transistor according to claim 1, further comprising the step of removing a shaped silicon film to form source and drain regions. 3. After sequentially depositing a p-type silicon film and an n-type silicon film on an insulating substrate, and then processing the two-layer film into the shape of the source and drain of a transistor, the regions that will become the source and drain of an n-channel transistor are formed. 2. The method of forming a complementary thin film transistor according to claim 1, further comprising the step of covering with photoresist and removing the n-type silicon film overlying the source and drain of the p-channel transistor. 4. Complementary thin film transistor formation according to any one of claim 1, claim 2, and claim 3, wherein an aqueous solution of ethylenediamine and pyrocatechol is used to remove the n-type silicon film. Law. 5. The complementary thin film transistor according to claim 1, wherein the impurity concentration of the n-type silicon film is higher than the impurity concentration of the p-type silicon film. Formation method.