JPH10223906A - Manufacture of thin-film transistor and thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high performance thin-film transistor capable of reducing the number of photoresist processes and lowering a manufacturing cost. SOLUTION: A p-Si(polycrystalline silicon) film 22 obtained by polycrystallizing a gate insulation film 14 and a-Si(amorphous silicon) film 20 is formed on a gate electrode 12 formed on a substrate 10. A SiN(silicon nitride) film 28 is formed on the p-Si film 22 at a substrate temperature, about 200 deg.C-300 deg.C, and a difference in etch rate characteristics of wet etching between a gate electrode region and the other region is given to the SiN film 28. The SiN film selectively remains on the gate electrode region by etching SiN film 28 through wet etching. A channel stopper film becoming a mask for impurity doping is precisely formed in the area becoming a channel region of TFT(thin- film transistor) without applying a photo resist process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (TFT) used for a liquid crystal display device or the like.
More particularly, the present invention relates to a configuration and a manufacturing method of a TFT having a channel stopper film serving as a mask when doping a silicon film with an impurity.

[0002]

2. Description of the Related Art In recent years, high definition and high image quality display has been demanded as a display device. For a liquid crystal display, an active matrix type liquid crystal display (AMLCD) using a thin film transistor as a switching element for driving a liquid crystal is used for this purpose. Liquid Crystal Dis
play).

In an AMLCD using a TFT, T
As an active layer of the FT, that is, a channel region, an amorphous silicon TFT using amorphous silicon (hereinafter, referred to as a-Si) and a polycrystalline silicon TFT using polycrystalline silicon (hereinafter, referred to as p-Si) are known. Have been.

[0004] Among them, the amorphous silicon TFT is a-
Since a Si film can be formed at a low temperature (for example, 300 ° C.),
Since it is easy to form on an inexpensive glass substrate having a low melting point and it is easy to form a uniform a-Si film over a wide area, it is advantageous for increasing the size of the panel. LCDs.

One polycrystalline silicon TFT is a-Si TFT.
The mobility of the p-Si film is higher than that of the film, and when a TFT is used, the on-state current is large and the sheet resistance (on-resistance) is low.

Therefore, it is regarded as useful as a switching element of a high-definition and high-quality LCD. In addition, since the selection period (duty ratio) becomes shorter as the size increases,
Its usefulness has also been pointed out as a liquid crystal driving element for a large LCD.

Further, a polycrystalline silicon TFT has a TFT channel region, a source region, and a p-Si film formed by self-alignment.
Since a drain region can be formed, a margin for mask alignment can be small, so that a small TFT can be formed.
Is also easy to form. Furthermore, polycrystalline silicon TFT
Can be used not only as a liquid crystal driving element in the pixel section, but also as a switching element forming a logic circuit of a driving circuit,
Further, both elements can be formed on the same substrate in the same step.

FIGS. 3 and 4 show a method of manufacturing such a polycrystalline silicon TFT.

A polycrystalline silicon TFT having a bottom gate structure
In the manufacture of the device, first, a Cr film is formed on a glass substrate 10 and is patterned into a predetermined shape.
(A) As shown in FIG.
Create Next, as shown in FIG. 3B, the gate insulating film 14 and the a-Si film 20 are formed by plasma CVD (PE-PE).
CVD: Plasma Enhanced Chemical Vapor Depositio
Continuously formed by n). The formed a-Si film 20 is subjected to an annealing treatment (for example, ELA:
Excimer Laser Annealing).
The p-Si film 22 is obtained by polycrystallizing the i film 20.

After the p-Si film 22 has been formed by polycrystallization, a channel stopper film serving as a mask for ion doping of the p-Si film 22 is formed.

In forming the channel stopper film,
First, as shown in FIG.
An SiO ₂ film 31 is formed, and a resist film 33 is further formed thereon.
To form Next, the resist film 33 is exposed from above the substrate using the mask 35 (FIG. 3D) and developed to form the resist film 33 into a desired pattern (FIG. 3E).

After the resist development, as shown in FIG. 3F, the SiO ₂ film 31 is etched using the resist film 33 as a mask, and after the etching, the resist film 33 is peeled off to obtain a channel stopper film 32 (FIG. 3G )).

As a method of forming the channel stopper film 32, in addition to the procedure of FIGS. 3D and 3E, FIG.
Is known. In the back surface exposure, the SiO ₂ film 31 and the resist film 33 are used.
After the formation of the resist film 33, the resist film 33 is exposed from the back surface of the substrate using the gate electrode 12 as a mask as shown in FIG.
Then, as shown in FIG. 4B, a resist film 33 having a desired pattern is formed, and thereafter, the SiO ₂ film 31 is etched using the resist film 33 as a mask to form a channel stopper, as in FIG. 3F. The film 32 is formed at a position corresponding to the gate electrode 12.

After the channel stopper film 32 is formed by the above-described method, the p-Si film 22 is doped with impurities using the channel stopper film 32 as a mask (FIG. 3 (h)), followed by annealing. To activate the doped impurities to form the source / drain regions 40S and 40D of the TFT and the channel region 44 which is the active layer of the TFT.
When 40D is used as a corresponding source / drain electrode or a TFT for driving liquid crystal in a pixel portion of a liquid crystal display device, ITO (Indium Tin Oxi) which is a transparent conductive film is used as a pixel electrode in the source or drain regions 40S and 40D.
de) to obtain one substrate of the LCD.

[0015]

As described above, in the polycrystalline silicon TFT having the bottom gate structure, the channel stopper film 32 formed on the p-Si film on the gate electrode is formed.
Is used as a mask when forming a channel region of a TFT. For this reason, the channel stopper film 3 is formed by a photoresist process as shown in FIGS.
In forming 2, the position accuracy is strongly required.

On the other hand, the polycrystalline silicon TF as described above
In manufacturing T, it is required to form these TFTs with a smaller number of steps and with higher accuracy in order to further reduce costs and improve yield. Under such circumstances, the photoresist process used for forming the channel stopper film 32 is more costly than other film forming processes and the like, and the photoresist process used for forming the channel stopper film 32 is more expensive. The alignment accuracy of the mask is greatly affected by the film quality, the unevenness of the film or the substrate, and the like. Therefore, for such a photoresist process, in particular,
It is desired to reduce the number of steps.

The present invention has been made to solve such a problem, and in a TFT having a bottom gate structure, a channel stopper film used as a mask when doping impurities into a silicon film of the TFT can be more easily and accurately formed. It is an object of the present invention to provide a manufacturing method that can be formed well.

[0018]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned object, and has the following features.

According to the present invention, a gate electrode is formed on a substrate, a gate insulating film and a silicon film are formed above the gate electrode, and the silicon film is formed on a region of the silicon film which overlaps the gate electrode. This is a method for manufacturing a thin film transistor having a bottom gate structure in which a channel stopper film used as a mask for doping impurities is formed. A step of forming a silicon nitride film on the silicon film at a substrate temperature of about 200 ° C. to 300 ° C., and a step of etching the silicon nitride film by wet etching, the channel stopper film having a pattern corresponding to the gate electrode. , Is formed.

Further, in the above method, in the present invention,
The silicon nitride film is formed by low-temperature CVD.

Furthermore, the present invention provides the method of manufacturing a thin film transistor, wherein the etch rate of the silicon nitride on the gate electrode pattern, and the etch rate of the silicon nitride in a region other than on the gate electrode pattern,
The silicon nitride film formed on the silicon film is etched by utilizing the difference between the two, and the channel stopper film is formed in a pattern corresponding to the gate electrode.

Further, the thin film transistor of the present invention is formed so that a gate electrode patterned on a substrate, a gate insulating film formed on the gate electrode, and straddles the gate electrode via the gate insulating film. A silicon film, a channel stopper film formed in a region on the silicon film overlapping the gate electrode, and used as a mask when doping impurities into the silicon film;
And using silicon nitride as the channel stopper film.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention (hereinafter, referred to as embodiments) will be described with reference to the drawings. In the following description, the same parts as those in the drawings already described are denoted by the same reference numerals, and description thereof will be omitted.

Polycrystalline silicon TFT according to the present embodiment
Is a TF used for driving a liquid crystal of an LCD, for example.
T, and has a bottom gate structure in which a channel region and source / drain regions of the TFT are formed above the gate electrode.

In the manufacture of such a polycrystalline silicon TFT having a bottom gate structure, in the present embodiment, silicon nitride (Si) is used as a channel stopper film used as a mask when doping impurities into the polycrystalline silicon film.
N) is used. Then, at the time of SiN film formation, a channel stopper film is selectively formed on the gate electrode by utilizing the difference in the etch rate of SiN between the gate electrode pattern and the glass substrate which is generated depending on the film formation substrate temperature. I do. By employing such a method, in the present embodiment, it is possible to accurately form the channel stopper film at a position corresponding to the gate electrode without using a photoresist process.

The polycrystalline silicon TFT having the bottom gate structure according to the present embodiment is formed by a manufacturing process as shown in FIG.

First, as shown in FIG. 1A, Cr (W, Ta) is formed on an insulating substrate 10 made of glass or the like as a gate electrode and a gate wiring integrated with the gate electrode (hereinafter, simply referred to as a gate electrode 12). , TaMo) may be formed by sputtering and patterned into a desired shape.
After the formation of the gate electrode 12, a two-layered gate insulating film 14 (SiN, SiO ₂ ) and an a-Si film 20 are formed on the gate electrode 12, specifically, on the entire surface of the substrate 10 including the gate electrode surface.
Is continuously formed by PE-CVD. After the formation of the a-Si film 20, as shown in FIG.
A annealing is performed by A, and the a-Si film 20 is polycrystallized to form a p-Si film 22.

After polycrystallizing a-Si, in order to obtain a channel stopper film, first, as shown in FIG. 1C, the substrate temperature is set to 200 ° C. or lower by plasma CVD (PE-CVD) or the like.
An SiN film 28 is formed on the p-Si film 22 by using a low-temperature CVD method in a range of about 300 ° C. (for example, a substrate temperature of 250 ° C.). Other conditions of the plasma CVD for forming the SiN film are, for example, as shown in the table below.

[0029]

[Table 1] After forming the SiN film 28 by plasma CVD at a substrate temperature of 200 ° C. to 300 ° C., the SiN film 28 is etched for a predetermined time by wet etching. Then, a SiN film 28 having a desired thickness remains in the region above the gate electrode 12 as shown in FIG. 1D, and is formed in the other region, that is, on the substrate 10 via the gate insulating film. The SiN film 28 in the region is removed, and the channel stopper film 30 is selectively obtained in the region above the gate electrode.

As described above, only in the region above the gate electrode, S
The iN film remains because the wet etch rate of SiN has a dependency on the substrate temperature at the time of SiN film formation, as shown in FIG. In FIG. 2, the horizontal axis represents the temperature of the SiN film forming substrate, the right vertical axis represents the wet etch rate, and the left vertical axis represents the SiN film forming rate.

As shown in FIG. 2, the plasma CV
When SiN is formed by D, when the substrate temperature during the film formation is in the range of 200 ° C. to 350 ° C., the wet etch rate changes from 700 nm / min to 40 nm / min, almost seven times. On the other hand, the film forming rate hardly changes.

The change in the etch rate is considered to be for the following reason.

That is, when an SiN film is formed by plasma CVD, SiH ₄ gas is used as a reaction gas as shown in the above table, and the formed SiN film contains hydrogen. .

On the other hand, since the present embodiment has a bottom gate structure, even if the substrate temperature is set at 200 ° C. to 300 ° C. during plasma CVD, the gate electrode patterned on the substrate is actually There is a temperature difference between the existing region and the region on the glass substrate without the gate electrode,
The temperature of the gate electrode region becomes higher (the temperature difference Δ is, for example, about 25 ° C.).

For this reason, as shown in FIG.
When a SiN film containing hydrogen is formed on the film 22, the amount of hydrogen released from the SiN film in the high-temperature gate electrode formation region becomes larger than that in the other glass substrate region at a lower temperature. Since the SiN film contains less hydrogen, the film becomes denser. Therefore, when wet etching is performed, the etch rate of the dense region of the film is higher than the etch rate of other regions having a higher hydrogen content. Become slow.

As described above, S by plasma CVD
When forming the iN film, if the substrate temperature (200 ° C. to 300 ° C.) is set such that there is a sufficient difference in the amount of hydrogen desorbed from the SiN film between the gate electrode region and other regions. It is possible to form the channel stopper film 30 by selectively leaving the SiN film in the region on the gate electrode having a low etch rate by the wet etching.

As a specific example, the substrate temperature during SiN film formation is set to 250 ° C. (the actual temperature on the gate electrode is 270 ° C.).
℃, 250 ℃ on the substrate), NH buffer solution
When wet etching is performed using an etching solution having a ratio of xF to HF of 7: 1, the etch rate Vn of SiN in the region above the gate electrode and the etch rate Vm of SiN in the other regions are: A difference as shown in FIG. 2 occurs.

More specifically, (i) the etch rate Vn in the region above the gate electrode 15
(Ii) Etch rate Vm in other areas 225
A difference of about 0 ° / min occurs.

Therefore, assuming that an SiN film is formed by plasma CVD at 6000.degree. And the etching time is set to 2 minutes and 40 seconds, after the etching is completed, the SiN film having a thickness of about 2000.degree. Become.

Assuming that the film thickness of SiN to be formed first is L and the film thickness of SiN remaining after the wet etching, that is, the target film thickness is 1, the film thickness L to be formed is, for example, expressed by the following formula: As shown in 1), it may be set based on Vn, Vm and the target film thickness l. However, since other conditions must be taken into account in actuality, it is not always necessary to satisfy Expression (1).

[0041]

L ≧ {Vm / (Vm−Vn)} × 1 (1) In plasma CVD, a susceptor for heating the substrate is provided. To heat the substrate to about 200 ° C. to 300 ° C. Therefore, even if the channel stopper film is formed of SiN as in the present embodiment, it is not necessary to add a special function to the plasma CVD apparatus. Further, the method of forming a SiN film is not limited to the above-described plasma CVD, and a low-temperature CVD method for forming a film at a substrate temperature of about 200 to 300 ° C.
, It is possible to give a difference in the etch rate of SiN depending on the region.

As described above, the p-S on the gate electrode
After the channel stopper film 30 made of SiN is formed in the i region, as shown in FIG. 1E, the p-Si film 22 is doped with an impurity (P or B) using the channel stopper film 30 as a mask. . As a result, an impurity-doped region is formed in a region immediately below the channel stopper film 30, that is, in a region other than the gate electrode formation region (channel region). When a TFT having an LDD structure is formed, first, a low concentration impurity is doped using the channel stopper film 30 as a mask, and then a certain region near the channel is masked, and the same conductivity as the low concentration impurity is doped. High-concentration doping of the type impurity.

After the impurity doping is completed, as shown in FIG. 1F, ELA is activated to activate the doped impurities.
Activation anneal treatment (RTA: Rapi:
d Thermal Annealing). Then, the source / drain regions 44S and 44D of the TFT are formed in the p-Si film 22 by this annealing process.

After the activation of the impurities, the p-Si film 24 is patterned into a desired shape, and as shown in FIG.
Forming an interlayer insulating film 50 by laminating SiO ₂ and SiN;
A contact hole is opened at the position of the source region 44S in the interlayer insulating film 50. Then, a source electrode 70 made of Al or the like is formed thereon and connected to the source region 44S. Further, the liquid crystal driving TF in the pixel portion of the LCD
In the case of forming T, a flattening film 52 is formed using these upper acrylic resins, contact holes are opened in the flattening film 52 and the interlayer insulating film 50, and an ITO 60 serving as a pixel electrode is formed thereon. Then, the ITO 60 and the drain region 44D are connected.

Through the above manufacturing steps, for example, L
A TFT as shown in FIG. 1G is formed for each pixel in a matrix on the image display section of the CD panel, and one substrate of the LCD is obtained. An LCD device is obtained by bonding this substrate to an opposing substrate on which a common electrode and a color filter are formed and sealing liquid crystal between them. Then, by controlling the potential of the ITO 60 using each pixel unit TFT, a desired voltage is applied to the liquid crystal to perform display. Although the source region 44S is connected to the source electrode 70 and the drain region 44D is connected to the ITO 60, the present invention is not limited to this, and the source region 44S may be connected to the ITO 60. Note that the TFT obtained in the above-described process is not used for driving a liquid crystal, but is used for a device such as a driving circuit of a display device, for example, a complementary metal oxide semiconductor (CMOS).
When used as r), the ITO 60 is unnecessary.
In this case, at the same time as the formation of the source electrode 70, a drain electrode is formed in the same manner and connected to the drain region 44D. After the source / drain electrodes are formed, they are connected to the corresponding source / drain wirings. However, when the electrode and the wiring are formed integrally,
A necessary wiring pattern is formed simultaneously with the formation of the source / drain electrodes.

[0046]

As described above, in the present invention, in manufacturing a polycrystalline silicon TFT having a bottom gate structure, a silicon nitride film is formed on a silicon film at a substrate temperature of about 200 ° C. to 300 ° C. The film has a difference in the etch rate characteristics with respect to wet etching between the region above the gate electrode and the other regions. Therefore, by subsequently etching the silicon nitride film by wet etching, the SiN film can be selectively left in the region above the gate electrode. Therefore, without performing the photoresist process, the p-Si
A channel stopper film can be accurately formed in a portion to be a channel region of the film.

As described above, according to the present invention, compared with the conventional method of manufacturing a polycrystalline silicon TFT having a bottom gate structure, one photoresist step can be omitted, and alignment accuracy is most required. Since a photoresist step for forming a channel stopper film, which is one of the steps, can be omitted, throughput and yield can be improved, and a higher-performance TFT can be manufactured more easily and at lower cost. .

Even when the channel stopper film is formed of SiN, usually, in low-temperature CVD, for example, plasma CVD, the substrate is kept at 200 ° C.
Heat to about 300 ° C. Therefore, it is not necessary to add a special function to the CVD apparatus. From this point as well, it is possible to reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a polycrystalline silicon TFT having a bottom gate structure according to a first embodiment of the present invention.

FIG. 2 shows a polycrystalline silicon T according to the first embodiment of the present invention.
It is a figure showing the manufacturing process of FT.

FIG. 3 is a view showing a conventional manufacturing process of a polycrystalline silicon TFT having a bottom gate structure.

FIG. 4 shows a polycrystalline silicon T different from the manufacturing process of FIG.
It is a figure showing the conventional manufacturing process of FT.

[Explanation of symbols]

10 Substrate, 12, 18, 21, 23 Gate electrode, 1
4 gate insulating film, 20 a-Si film, 22 p-Si
Film, 28 SiN film, 30 channel stopper film, 44
Channel region, 44S source region, 44D drain region, 60 ITO.

Claims (4)

[Claims] 1. A gate electrode is formed on a substrate, a gate insulating film and a silicon film are formed above the gate electrode, and a region of the silicon film overlapping the gate electrode is doped with impurities. A method of manufacturing a bottom-gate thin film transistor in which a channel stopper film used as a mask is formed, wherein the channel stopper film having a pattern corresponding to the gate electrode has a substrate temperature of 200 ° C. to 300 ° C. on the silicon film. A method of forming a silicon nitride film by the following steps: and a step of etching the silicon nitride film by wet etching. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the silicon nitride film is formed by low-temperature CVD. 3. The method for manufacturing a thin film transistor according to claim 2, wherein a difference between an etch rate of the silicon nitride on the gate electrode pattern and an etch rate of the silicon nitride in a region other than on the gate electrode pattern. And etching the silicon nitride film formed on the silicon film by using the silicon nitride film to form the channel stopper film in a pattern corresponding to the gate electrode. A gate electrode patterned on a substrate; a gate insulating film formed on the gate electrode; a silicon film formed so as to straddle the gate electrode via the gate insulating film; A channel stopper film formed in a region on the silicon film that overlaps the gate electrode and used as a mask when doping impurities into the silicon film, wherein silicon nitride is used as the channel stopper film. Thin film transistor.