JPH02285678A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of the troubles of Al wirings, such as clock signal lines, constant-potential lines and the like in a TFT, a CMOSFET and the like, which is accompanied by an increase in the area of a device, and to obtain the semiconductor device having a high reliability in respect to its wirings by a method wherein transfer clock wirings, which have an antiphase to each other, and constantpotential wirings are formed in such a way that they are partially formed into a two-layer structure. CONSTITUTION:In a semiconductor device, which is constituted using thin film transistors 101 to 103 and 111 to 113 to be formed on an insulating substrate, transfer clock wirings 121' and 122', which have an antiphase to each other, and constant- potential wirings 123' and 124' are formed in such a way that they are partially formed into a two-layer structure. For example, a part shown by crosshatchings is formed into a two-layer structure in a part in the diagram on the clock signal lines 121' and 122' of a CMOS dynamic shift register constituted by a TFT and a part shown by mere hathcings is formed into a one-layer structure consisting of Al only. In that case, the above two-layer structure is deposited simultaneously with a polycrystalline silicon film, which is used as the material for a gate electrode of the TFT, and is constituted of the silicon film having reduced resistance and an Al film 18 deposited on the silicon film.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a T F formed on an insulating substrate such as quartz glass.
The present invention relates to a semiconductor device configured using an r-CMO5FET.

[Prior art]

Thin film transistors (TPTs) have the advantage that they can be formed on inexpensive glass substrates, require fewer steps, and have lower process costs than semiconductor elements formed on expensive silicon substrates. Furthermore, by incorporating the functional elements into the same substrate, it is possible to achieve so-called lightness, thinness, and shortness. Therefore, in recent years, TPT has been applied to various devices, especially large-area devices for driving sensors or liquid crystal displays.

The configuration of a conventional TPT is shown in FIG. This TPT is manufactured as follows. First, an island 2 of a polycrystalline silicon film is formed on a glass substrate 1, and then the surface is oxidized to form a polycrystalline silicon film 4 that will become a gate electrode. Next, a soft drain diffusion layer 5 is formed by ion implantation, an interlayer insulating film 6 is formed, a contact hole is opened, and an aluminum alloy wiring 7 is formed.

FIG. 3 shows a circuit diagram of an example of a CMOS dynamic shift register constructed using TPT.

Figure 3 shows the configuration of 1 bit of a CMOS dynamic shift register, in which P-type MO3FET 101
, 102, a clocked inverter 131 consisting of N-type MO3FET 111 and 112, and P-type MO5FET1.
03, an inverter 132 consisting of an N-type MO3FET 113 constitutes a shift register.

Further, in the same figure, 121 and 122 are clock terminals that provide transfer lock signals with opposite phases to each other,
123 and 124 are a positive power supply terminal and a negative power supply terminal, respectively. As shown in FIG. 3, by incorporating the TPT in the same manner as the functional element, the area ratio increases, and as a result, the AΩ wiring 121' in the shift register in FIG.
.

The lengths of 122', 123', and 124' (that is, clock signal lines and constant potential lines) are becoming approximately equal to the length of the glass substrate.

In general, failures that occur in AQ and wiring include electromigration failure and stress migration failure, and their occurrence depends on defects in the film. The probability of a failure occurring increases. Furthermore, with regard to stress migration failure, the pressure applied from the outside becomes more severe as the substrate size increases.

On the other hand, JP-A-61-35564 discloses an invention in which the AQ wiring section of the TFT section has a two-layer structure.
CMO5FET using TPT as contemplated by the present invention
Regarding clock wiring, constant potential wiring, etc., there have been no proposals to avoid the above-mentioned failures caused by increasing the area.

〔the purpose〕

The present invention improves the AQ of clock signal lines and constant potential lines in TFT-CMO5FETs etc. due to the increase in area.
The purpose of this invention is to prevent wiring failures and provide a semiconductor device with higher wiring reliability.

〔composition〕

The present invention is a semiconductor device formed using TPT formed on an insulating substrate, characterized in that transfer lock wiring and constant potential wiring, which are in opposite phases to each other, partially have a two-layer structure. It is something.

FIG. 1 is an enlarged view of the circled portion of the CMOS dynamic shift register shown in FIG. 3 in the semiconductor device according to the present invention. The portion indicated by simple hatching is formed of a single layer structure of only AQ.

Note that 14 in the figure is a polycrystalline silicon film 121'.

122' indicates a clock signal line.

Note that the CMO shown in FIG. 3 in a conventional semiconductor device
FIG. 4 shows an enlarged view of the circled portion of the S dynamic shift register. When the device of the present invention shown in FIG. 1 and the conventional device shown in FIG. 4 were compared under the stress conditions shown in FIG. It showed a lifespan 10 times longer than that of the previous one.

An example of a method for manufacturing the device shown in FIG. 1 will be described below with reference to the flow sheet shown in FIG.

After thoroughly cleaning the transparent quartz glass 11 whose surface has been sufficiently polished, a silicon film 12 serving as an active layer is deposited to a thickness of 2000 nm by low-pressure CVD, and photolithographically etched into an island shape. Dry thermal oxidation is performed on this island-shaped polycrystalline silicon film at 1000° C. to form a thermal oxide film 13 that will become a gate insulating film (FIG. 6(a)).

Next, a polycrystalline silicon film 14 is used as a gate electrode material.
is deposited by low pressure CVD to reduce the resistance so that it can act as an electrode.

This reduction in resistance can be achieved by depositing a film containing a diffusing agent and by thermal diffusion, or by ion implantation. After that, patterning is performed by photolithography and etching. At this time, this polycrystalline silicon film 14' is also left in the portions corresponding to the clock signal line and the constant potential line in the AΩ wiring pattern (FIGS. 6(b) and 6(c)).

Source/drain regions 15 are formed by the ion implantation method, and phosphorus-doped silica glass, non-doped silica glass, or boron-doped silica glass is deposited as the interlayer insulating film 16 by the low-pressure CVD method, and the ions implanted by the previous ion implantation method are activated. 900℃ to
Perform annealing. Also, due to this thermal history, the interlayer insulating film 16 described above is densified and the surface state is further flattened (FIG. 6(d)). Next, a contact hole 17 is formed by photolithography and etching to make contact with the source/drain region and the gate portion. At this time, the polycrystalline silicon film was left in places corresponding to the clock signal line and the constant potential line, but in order to make contact with Afl, the upper interlayer insulating film 17' was cut into contact holes. At the same time, etching is removed (Fig. 6(e)).

Finally, AQ or Al1-1wt% Si alloy 18 is deposited by sputtering and formed by photolithography and etching. In this way, the clock signal line and the constant potential line can have a two-layer structure. In the two-layer structure, the first layer is a low-resistance polycrystalline silicon layer, and the second layer is A, fl (FIG. 6(f)).

According to such a manufacturing method, there is no need to newly deposit a polycrystalline silicon film or add a photolithography/etching process, and the process is simple and does not result in an increase in cost.

〔effect〕

As explained above, according to the present invention, the clock wiring and constant potential wiring of a semiconductor device configured using TFT-CMσ5FET formed on an insulating substrate such as quartz glass have a partially two-layer structure. Therefore, resistance to electromigration and stress migration is improved, and a highly reliable semiconductor device can be obtained even when a large-area device is manufactured.

[Brief explanation of drawings]

FIG. 1 is an enlarged explanatory diagram of a clock wiring portion of a semiconductor device according to the present invention. FIG. 2 is a sectional view of a conventional semiconductor device. FIG. 3 is a circuit diagram of an example of a CMOS dynamic shift register constructed using TPT. FIG. 4 is an enlarged explanatory diagram of a clock wiring portion in a conventional device. FIG. 5 is an explanatory diagram showing an accelerated test means used to measure the failure time of a semiconductor device. FIG. 6 is a flow sheet showing steps for manufacturing a semiconductor device according to the present invention. 11... Transparent quartz glass 12... Polycrystalline silicon film 13... Thermal oxide film 14... Polycrystalline silicon film 15... Source/drain region 16... Interlayer insulating film 17... Contact Hall 18...AQ wiring 121, 121', 122, 122'...Clock signal line 123, 123', 124, 124'...
・Constant potential line section 2-layer structure decoy] 1-layer AI only location

Claims (1)

[Claims] 1. A semiconductor device configured using thin film transistors formed on an insulating substrate, characterized in that transfer lock wiring and constant potential wiring that are in opposite phases to each other partially have a two-layer structure. .