JPS63218926A - Thin film transistor array and its manufacture - Google Patents
Thin film transistor array and its manufactureInfo
- Publication number
- JPS63218926A JPS63218926A JP62052531A JP5253187A JPS63218926A JP S63218926 A JPS63218926 A JP S63218926A JP 62052531 A JP62052531 A JP 62052531A JP 5253187 A JP5253187 A JP 5253187A JP S63218926 A JPS63218926 A JP S63218926A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- transparent conductive
- conductive film
- picture element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000010408 film Substances 0.000 claims abstract description 116
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000011159 matrix material Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims 2
- 238000000034 method Methods 0.000 description 14
- 239000011521 glass Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は薄膜トランジスタアレイ及びその製造方法に関
する。特にアクティブマトリクス型液晶ディスプレイに
用いる断線不良及びゲートバスラインーソースパスライ
ン間短絡が少な(かつ工程の少ない二重ゲート電極構造
を有するa(アモルファス)−8i半導体トランジスタ
アレイ及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film transistor array and a method of manufacturing the same. In particular, the present invention relates to an a-8i semiconductor transistor array having a double gate electrode structure with fewer disconnection defects and short circuits between gate bus lines and source path lines (and fewer steps) used in active matrix liquid crystal displays, and a method for manufacturing the same.
従来の技術
従来、薄膜トランジスターアレイにおいては第2図に示
すように透明基板、例えばガラス基板21上に例えば透
明導電膜としてITO膜からなる絵素電極22をパター
ン形成し、次に例えばCr膜からなるゲート電極23を
ガラス基板21上に形成し、以上のプロセスの後にゲー
ト絶縁膜として例えば膜厚400nmのSiN膜24、
膜厚1100nのi(真性)−a−8i膜25を順次積
層し、次に1−a−3i膜とのオーミック接触を得るた
めに、1−a−8i膜25上に高不純物濃度を有するn
+−a−8i膜26を積層後、絵素電極上のn+−a−
Si膜、1−a−3i膜、5iNl!Iを窓あけエツチ
ングし、導電膜27を設けてソース電極27aとドレイ
ン電極27bを形成し、更にソース電極27aとドレイ
ン電極27bをエツチングマスクとしn+−a−8i膜
26をエツチングし形成していた。この導電膜材料には
、Cr、Au、Ni、Ni/Cr、AI、ITOなどが
用いられている。一般に、薄膜トランジスタを集積する
場合、浮遊容量による信号遅延を防ぐため配線抵抗の低
いAIを主として用いている。Conventionally, in a thin film transistor array, as shown in FIG. 2, a pixel electrode 22 made of, for example, an ITO film is formed as a transparent conductive film on a transparent substrate, for example, a glass substrate 21, and then a pixel electrode 22 made of, for example, a Cr film is patterned. A gate electrode 23 is formed on the glass substrate 21, and after the above process, a SiN film 24 with a thickness of 400 nm, for example, is formed as a gate insulating film.
An i (intrinsic)-a-8i film 25 with a film thickness of 1100 nm is sequentially laminated, and then a high impurity concentration is formed on the 1-a-8i film 25 in order to obtain ohmic contact with the 1-a-3i film. n
After laminating +-a-8i film 26, n+-a- on the picture element electrode
Si film, 1-a-3i film, 5iNl! A conductive film 27 is provided to form a source electrode 27a and a drain electrode 27b, and then an n+-a-8i film 26 is etched using the source electrode 27a and drain electrode 27b as an etching mask. . Cr, Au, Ni, Ni/Cr, AI, ITO, etc. are used as the conductive film material. Generally, when integrating thin film transistors, AI with low wiring resistance is mainly used to prevent signal delay due to stray capacitance.
発明が解決しようとする問題点
以上のような薄膜トランジスタアレイのゲート電極構造
に於てはゲートパスラインの断線が発生する確率は低い
と言えるものではない。例えばゲート電極膜材料として
Crなとの金属材料を使用した場合、ゲート絶縁膜を構
成するSiN膜にピンホールがあるとゲート電極膜が電
界腐食しゲートパスラインに断線が発生すると言う問題
を有していた。Problems to be Solved by the Invention In the gate electrode structure of a thin film transistor array as described above, it cannot be said that the probability of occurrence of disconnection of the gate pass line is low. For example, when a metal material such as Cr is used as the gate electrode film material, if there is a pinhole in the SiN film that constitutes the gate insulating film, there is a problem that the gate electrode film will undergo electric field corrosion and disconnection will occur in the gate pass line. was.
この問題を解決する方法として第3図に示すように透明
導電膜、例えば膜厚1100nのITO膜31と金属薄
膜、例えば膜厚1100nのCr膜32を順次積層しゲ
ート電極パターンをフォトレジストにて形成しCr膜、
ITO膜を連続してエツチングし、ITO/Cr二重ゲ
ート電極33を形成する。後工程の絵素電極上のゲート
絶縁膜の窓あけ工程時にCrを除去し、絵素電極34を
ITO−重電径、ゲート電極35をLTO/Cr二重層
とする方法が考えられる。しかしITO/Cr二重層の
ためITO/Crの膜厚200nmとなりゲート絶縁膜
を構成するSiN膜24のゲート二重層に対するカバレ
ッジが厳しくなりゲートパスラインとソースパスライン
との短絡不良の確率が増加すると言う問題を有していた
。また、絵素電極34上のCrのサイドエツチングによ
りSiN膜24のオーバーハングが発生するため、Si
N膜からなるフレークの発生による工程の汚れおよびド
レイン電極と絵素電極とのコンタクト不良による絵素欠
陥が発生すると言う問題を有していた。同図に於て、2
1.24.25.26.27.27a、27bは第2図
と同一である。As a method to solve this problem, as shown in FIG. 3, a transparent conductive film, for example, an ITO film 31 with a thickness of 1100 nm, and a thin metal film, such as a Cr film 32 with a thickness of 1100 nm, are successively laminated, and the gate electrode pattern is formed using photoresist. Formed Cr film,
The ITO film is continuously etched to form an ITO/Cr double gate electrode 33. A conceivable method is to remove Cr during the window opening process of the gate insulating film on the picture element electrode in the subsequent process, and make the picture element electrode 34 an ITO-heavy conductor and the gate electrode 35 an LTO/Cr double layer. However, since the ITO/Cr double layer is 200 nm thick, the coverage of the SiN film 24 constituting the gate insulating film with respect to the gate double layer becomes difficult, increasing the probability of short-circuit failure between the gate pass line and the source pass line. I had a problem. In addition, side etching of Cr on the picture element electrode 34 causes an overhang of the SiN film 24.
There have been problems in that the process is contaminated due to the generation of flakes made of the N film, and pixel defects occur due to poor contact between the drain electrode and the pixel electrode. In the same figure, 2
1.24.25.26.27.27a and 27b are the same as in FIG.
即ち、従来のゲート電極構造では例えば金属膜の電界腐
食によるゲートパスライン断線、二重膜ゲート電極構造
ではゲートパスラインとソースパスラインとの短絡不良
、及び工程の汚染と絵素欠陥の発生という問題を有して
いた。That is, the conventional gate electrode structure has problems such as disconnection of the gate pass line due to electric field corrosion of the metal film, and the double film gate electrode structure has problems such as short-circuiting between the gate pass line and the source pass line, as well as process contamination and pixel defects. had.
本発明はゲートパスライン断線のない、しかむ工程を増
加させない薄膜トランジスタアレイの構造及びその製造
方法を提供するものである。The present invention provides a structure of a thin film transistor array and a method for manufacturing the same, which does not cause disconnection of gate pass lines and does not increase the number of manufacturing steps.
問題点を解決するための手段
そこで、本発明は、上記した目的に鑑みなされたもので
ある。即ち、透明基板上に透明導電膜と上記透明導電膜
より幅員が狭く且つ上記透明導電膜に自己整合的に設け
た電極膜とからなるゲート電極と透明導電膜からなる絵
素電極とを設け、絵素電極上に開口部を有するゲート絶
縁膜と半導体層を設け、ソース電極及び電気的に絵素電
極と結合したドレイン電極を具備する薄膜トランジスタ
をマトリックス状に配列させて構成している。Means for Solving the Problems The present invention has been made in view of the above-mentioned objectives. That is, a gate electrode made of a transparent conductive film and an electrode film narrower in width than the transparent conductive film and provided in self-alignment with the transparent conductive film, and a pixel electrode made of the transparent conductive film are provided on a transparent substrate, A gate insulating film and a semiconductor layer having an opening are provided on a picture element electrode, and thin film transistors each having a source electrode and a drain electrode electrically coupled to the picture element electrode are arranged in a matrix.
この構成を実現するには、透明基板上に透明導電膜と電
極膜を蒸着する工程と、ネガ型感光材料を塗布パターン
ニングし電極膜を過食刻する工程と、上記ネガ型感光材
料をベーキングする工程と、透明導電膜を食刻しゲート
電極と絵素電極を形成する工程と、上記絵素電極の電極
膜を食刻し透明導電膜のみからなる絵素電極を形成する
工程と、ゲート絶縁膜と半導体層を蒸着する工程と、上
記絵素電極の窓あけを行い透明導電膜上に開口部を設け
る工程と、電極膜を蒸着しソース電極およびドレイン電
極を形成する工程とからなる。To realize this configuration, there are a process of vapor depositing a transparent conductive film and an electrode film on a transparent substrate, a process of applying and patterning a negative photosensitive material and over-etching the electrode film, and a process of baking the negative photosensitive material. a process of etching the transparent conductive film to form a gate electrode and a picture element electrode; a process of etching the electrode film of the picture element electrode to form a picture element electrode consisting only of the transparent conductive film; It consists of a step of vapor depositing a film and a semiconductor layer, a step of opening the picture element electrode to provide an opening on the transparent conductive film, and a step of vapor depositing an electrode film to form a source electrode and a drain electrode.
作用
以上のような本発明による薄膜トランジスタアレイの電
極構造は、ゲートパスラインを透明導電m/電極膜の二
重構造からなるためゲートパスラインの断線がな(また
ゲート電極の二重構造を自己整合的に形成しているため
ゲートバスラインーソースパスライン間短絡の発生確率
を増やすことがない。加えて、フォトリソグラフに使用
するマスク枚数は従来と変化しない。それ故、本発明に
よる電極構造はゲートパスラインの断線がな(且つゲー
トバスラインーソースパスライン間短絡の発生確率の低
い薄膜トランジスタアレイを実現することが出来る。In the electrode structure of the thin film transistor array according to the present invention as described above, the gate pass line is made of a double structure of transparent conductive m/electrode film, so that there is no disconnection of the gate pass line (also, the double structure of the gate electrode can be formed in a self-aligned manner). The electrode structure according to the present invention does not increase the probability of short circuit between the gate bus line and the source path line.In addition, the number of masks used for photolithography does not change from the conventional one.Therefore, the electrode structure according to the present invention It is possible to realize a thin film transistor array that is free from disconnections (and has a low probability of short circuits occurring between gate bus lines and source path lines).
実施例
以下、添付図面を参照して本発明による薄膜トランジス
タの実施例を説明する。Embodiments Hereinafter, embodiments of a thin film transistor according to the present invention will be described with reference to the accompanying drawings.
第1図は、本発明によるゲート電極構造を有する薄膜ト
ランジスタアレイの実施例を示す要部断面図である。す
なわち、透明基板、例えばガラス基板11上に透明導電
膜、例えばITOIIIMIと透明導電膜M1より幅員
が狭く且つ透明導電膜M1に自己整合的に設けた電極膜
M1とからなるゲート電極12と透明導電膜M1からな
る絵素電極13とを設け、絵素電極13上に開口部14
を有するゲート絶縁膜、例えばSiN膜15と半導体層
、例えば1−a−8i膜16を設け、導電体膜例えば、
A11]IM3からなるソース電極17a及び電気的に
絵素電極13と結合したドレイン電極17bを具備する
薄膜トランジスタをマトリックス状に配列させた。FIG. 1 is a sectional view of a main part showing an embodiment of a thin film transistor array having a gate electrode structure according to the present invention. That is, a gate electrode 12 and a transparent conductive film are formed of a transparent conductive film, for example, ITOIIIMI, on a transparent substrate, for example, a glass substrate 11, and an electrode film M1 that is narrower in width than the transparent conductive film M1 and is provided in self-alignment with the transparent conductive film M1. A picture element electrode 13 made of a film M1 is provided, and an opening 14 is formed on the picture element electrode 13.
A gate insulating film, e.g., a SiN film 15, and a semiconductor layer, e.g., a 1-a-8i film 16, are provided, and a conductive film, e.g.,
A11] Thin film transistors each having a source electrode 17a made of IM3 and a drain electrode 17b electrically coupled to the picture element electrode 13 were arranged in a matrix.
本発明による構成を実現するには、以下のごとく行う。To realize the configuration according to the present invention, the following steps are performed.
以下においては薄膜トランジスタアレイ内の1つの薄膜
トランジスタを代表させて説明する。すなはちガラス基
板11上に例えば膜厚1100nのITO膜M1と膜厚
1100nのCr膜M2を順次蒸着し、ネガ型感光材料
、例えば環化ゴム系レジストを塗布パターンニングしC
r膜M2をエツチングし、さらにレジスト下のCr膜を
例えば2μmサイドエツチングさせした後、上記レジス
トを160℃で20分間ベーキングさせると上記レジス
トは塑性変形しITO膜と密着させることが出来る。次
にITO膜M1をエツチングし自己整合的な二重膜から
なるゲート電極12と絵素電極13を形成させた。絵素
電極13のCr膜をエツチングし、I TOIIIIM
1のみからなる絵素電極を形成させた。更に例えば膜
厚400nmのSiN膜15と膜厚1100nの1−a
−8i膜16と膜厚50nmのn+−a−8i膜18を
蒸着し、絵素電極13の窓あけをIT○膜周辺を残して
行いITO膜上に開口部14を設ける。例えば膜厚70
0nmのAI膜17を蒸着しソース電極17aおよびド
レイン電極17bを形成した後、AI膜をエツチングマ
スクとしてn+−a−8i膜をエツチングし、薄膜トラ
ンジスタアレイを形成した。In the following, one thin film transistor in the thin film transistor array will be representatively explained. In other words, an ITO film M1 with a thickness of 1100 nm and a Cr film M2 with a thickness of 1100 nm are sequentially deposited on a glass substrate 11, and a negative photosensitive material such as a cyclized rubber resist is applied and patterned.
After etching the r film M2 and side etching the Cr film under the resist by, for example, 2 μm, the resist is baked at 160° C. for 20 minutes, whereby the resist is plastically deformed and can be brought into close contact with the ITO film. Next, the ITO film M1 was etched to form a gate electrode 12 and a picture element electrode 13 made of a self-aligned double film. Etching the Cr film of the picture element electrode 13
A picture element electrode consisting of only 1 was formed. Furthermore, for example, a SiN film 15 with a film thickness of 400 nm and a film 1-a with a film thickness of 1100 nm
A -8i film 16 and an n+-a-8i film 18 having a film thickness of 50 nm are deposited, and the picture element electrode 13 is opened leaving the periphery of the IT○ film to form an opening 14 on the ITO film. For example, film thickness 70
After depositing a 0 nm AI film 17 to form a source electrode 17a and a drain electrode 17b, the n+-a-8i film was etched using the AI film as an etching mask to form a thin film transistor array.
発明の効果
以上の説明から明らかなように、本発明による薄膜トラ
ンジスタアレイのゲート電極構造は、透明導電膜/電極
膜2重膜構造からなるので、ゲートパスラインの断線が
なく、シかもこの2重膜構造は自己整合的に形成できる
のでゲートバスラインーソースパスライン間短絡の発生
確率を増加させることがなく且つ絵素の開口率を低下さ
せることかない。また、従来の構成と同数のマスク枚数
で形成できる。従って、本発明によれば、従来の構成と
同数のマスク枚数でゲートパスライン断線のない薄膜ト
ランジスタアレイを実現できる。Effects of the Invention As is clear from the above explanation, the gate electrode structure of the thin film transistor array according to the present invention consists of a double film structure of a transparent conductive film/electrode film, so there is no disconnection of the gate pass line, and this double film Since the structure can be formed in a self-aligned manner, the probability of short circuit between the gate bus line and the source path line does not increase, and the aperture ratio of the picture element does not decrease. Further, it can be formed using the same number of masks as the conventional configuration. Therefore, according to the present invention, a thin film transistor array without gate pass line disconnection can be realized with the same number of masks as in the conventional configuration.
第1図は本発明による実施例にかかる薄膜トランジスタ
アレイの要部断面構造を示す図、第2図は第1の従来の
薄膜トランジスタアレイの要部断面構造を示す図、第3
図は第2の従来の薄膜トランジスタアレイの要部断面構
造を示す図である。
11・・・・ガラス基板、12・・・・ゲート電極、1
3・・・・絵素電極、14・・・・開口部、15・・・
・ゲート絶縁膜、16・・・・半導体層、17a・・・
・ソース電極膜、17b・・・・ゲート電極膜、18・
・・・n+−a−8i膜、Ml・・・・透明導電膜、M
2・・・・電極膜、M3・・・・導電膜。FIG. 1 is a diagram showing a cross-sectional structure of a main part of a thin film transistor array according to an embodiment of the present invention, FIG. 2 is a diagram showing a cross-sectional structure of a main part of a first conventional thin film transistor array, and FIG.
The figure is a diagram showing a cross-sectional structure of a main part of a second conventional thin film transistor array. 11...Glass substrate, 12...Gate electrode, 1
3...Picture element electrode, 14...Opening, 15...
- Gate insulating film, 16... semiconductor layer, 17a...
- Source electrode film, 17b... Gate electrode film, 18.
...n+-a-8i film, Ml...transparent conductive film, M
2... Electrode film, M3... Conductive film.
Claims (2)
員が狭く且つ上記透明導電膜に自己整合的に設けた電極
膜とからなるゲート電極と、透明導電膜からなる絵素電
極とを設け、上記絵素電極上に開口部を有するゲート絶
縁膜と半導体層を設け、ソース電極及び電気的に上記絵
素電極と結合したドレイン電極を具備する薄膜トランジ
スタをマトリックス状に配列させたことを特徴とする薄
膜トランジスタアレイ。(1) A gate electrode consisting of a transparent conductive film and an electrode film narrower in width than the transparent conductive film and provided in self-alignment with the transparent conductive film on a transparent substrate, and a pixel electrode consisting of the transparent conductive film. A gate insulating film and a semiconductor layer having an opening are provided on the picture element electrode, and thin film transistors each having a source electrode and a drain electrode electrically coupled to the picture element electrode are arranged in a matrix. Thin film transistor array.
と、ネガ型感光材料を塗布パターンニングし電極膜を過
食刻する工程と、上記ネガ型感光材料をベーキングする
工程と、上記透明導電膜を食刻しゲート電極と絵素電極
を形成する工程と、上記絵素電極の電極膜を食刻し透明
導電膜のみからなる絵素電極を形成する工程と、ゲート
絶縁膜と半導体層を蒸着する工程と、上記絵素電極の窓
あけを行い透明導電膜上に開口部を設ける工程と、導電
膜を蒸着しソース電極およびドレイン電極を形成する工
程とからなることを特徴とする薄膜トランジスタアレイ
の製造方法。(2) A step of vapor depositing a transparent conductive film and an electrode film on a transparent substrate, a step of applying and patterning a negative photosensitive material and over-etching the electrode film, a step of baking the negative photosensitive material, and a step of baking the negative photosensitive material; A step of etching the conductive film to form a gate electrode and a picture element electrode, a step of etching the electrode film of the picture element electrode to form a picture element electrode consisting only of a transparent conductive film, and a gate insulating film and a semiconductor layer. A thin film transistor comprising the following steps: evaporating the pixel electrode, forming an opening on the transparent conductive film, and evaporating a conductive film to form a source electrode and a drain electrode. Array manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62052531A JPS63218926A (en) | 1987-03-06 | 1987-03-06 | Thin film transistor array and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62052531A JPS63218926A (en) | 1987-03-06 | 1987-03-06 | Thin film transistor array and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63218926A true JPS63218926A (en) | 1988-09-12 |
Family
ID=12917340
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62052531A Pending JPS63218926A (en) | 1987-03-06 | 1987-03-06 | Thin film transistor array and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63218926A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0407168A2 (en) * | 1989-07-04 | 1991-01-09 | Sharp Kabushiki Kaisha | A thin film semiconductor array device |
US5402254A (en) * | 1990-10-17 | 1995-03-28 | Hitachi, Ltd. | Liquid crystal display device with TFTS in which pixel electrodes are formed in the same plane as the gate electrodes with anodized oxide films before the deposition of silicon |
US5528396A (en) * | 1987-06-10 | 1996-06-18 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices with a holding capacitance between the pixel electrode and a scanning signal line |
-
1987
- 1987-03-06 JP JP62052531A patent/JPS63218926A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5708484A (en) * | 1987-06-10 | 1998-01-13 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices with two layer gate lines, the first being the same level and material as gate electrodes |
US6184963B1 (en) | 1987-06-10 | 2001-02-06 | Hitachi, Ltd. | TFT active matrix LCD devices employing two superposed conductive films having different dimensions for the scanning signal lines |
US5528396A (en) * | 1987-06-10 | 1996-06-18 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices with a holding capacitance between the pixel electrode and a scanning signal line |
US5532850A (en) * | 1987-06-10 | 1996-07-02 | Hitachi, Ltd. | TFT active matrix liquid crystal display with gate lines having two layers, the gate electrode connected to the wider layer only |
US7450210B2 (en) | 1987-06-10 | 2008-11-11 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
US7196762B2 (en) | 1987-06-10 | 2007-03-27 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
US6992744B2 (en) | 1987-06-10 | 2006-01-31 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
US5838399A (en) * | 1987-06-10 | 1998-11-17 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices with two layer gate lines, the first being the same level as gate electrodes. |
US6839098B2 (en) | 1987-06-10 | 2005-01-04 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
US6384879B2 (en) | 1987-06-10 | 2002-05-07 | Hitachi, Ltd. | Liquid crystal display device including thin film transistors having gate electrodes completely covering the semiconductor |
EP0407168A2 (en) * | 1989-07-04 | 1991-01-09 | Sharp Kabushiki Kaisha | A thin film semiconductor array device |
US5402254A (en) * | 1990-10-17 | 1995-03-28 | Hitachi, Ltd. | Liquid crystal display device with TFTS in which pixel electrodes are formed in the same plane as the gate electrodes with anodized oxide films before the deposition of silicon |
US5671027A (en) * | 1990-10-17 | 1997-09-23 | Hitachi, Ltd. | LCD device with TFTs in which pixel electrodes are formed in the same plane as the gate electrodes with anodized oxide films and before the deposition of the silicon gate insulator |
US5610738A (en) * | 1990-10-17 | 1997-03-11 | Hitachi, Ltd. | Method for making LCD device in which gate insulator of TFT is formed after the pixel electrode but before the video signal line |
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