JPH0228319A - Method of forming narrow aperture on solid surface - Google Patents

Abstract

PURPOSE: To form a short length gate by removing a part of a second layer consisting of an insulating material to define an area having a length substantially equal to a predetermined length on the surface at the position selected for a gate, and by applying a gate material to an area where the gate is defined. CONSTITUTION: A semiconductor body (main body) 20 is provided and a first layer 21 of an insulating material is applied to the surface of the body to which a gate 28 is to be applied, and a part of a first layer 21 of an insulator material is removed at a position where the gate 28 is to be formed to expose an area having a length larger than a predetermined length on the surface. Then, a second layer 24 is applied within an area where the gate 28 is to be formed and a part of the second layer 24 of the insulator is removed to define an area having a length substantially equal to the predetermined length on the surface at the position selected for the gate, and a gate material is applied to the gate defining area. Thus, a short length gate can be formed with a smaller initial investment and higher throughput without necessitating the use of contact printing, and an opening having a narrow width length can be formed in the coating on the surface of a solid.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming a gate for a semiconductor device, and more particularly to a method for forming a gate for a semiconductor device, and more particularly for use in a microwave monolithic integrated circuit device such as a gallium arsenide FET. The present invention further relates to a method of forming narrow length openings in a coating on a solid surface.

The most important factor in extending the frequency limit of a conventional IL GaAs field effect transistor is to shorten its gate length. Up to 40GHz with 1/4 micron gate length
It is possible to realize a cutoff frequency of
It is highly desirable to incorporate field effect transistors with 1/4 micron gate lengths into MMICs, even if they are required to function below 5 GHz. MMIC wideband amplifiers with responsive characteristics require matching circuits or other mechanisms to compensate for the roll-off in the gain curve of the field effect transistors used within the MMIC. The higher the cutoff frequency of the FET, the smaller the roll-off and the easier the compensation. Current MMICs covering frequency ranges up to 18 GHz typically use field effect transistors with gate lengths of 0.5 microns. This type of equipment is H,Q, Tserng
, H.M., Macksey, S., Nelson
Co-author, “Monolithic Microwave GaAs Power FET
Amplifier design, manufacturing and characterization
abr 1cation, and Character
Rization of Monolithic
Microwave GaAs Power
FETA Amplifiers) J, IEEE Transactions Electronic Devices, Vol, E
D-28, pages 183-190, 1981. A device with such a 0.5 micron gate length has a cutoff frequency barely above 18 GHz and therefore has a relatively fast roll-off in gain over the 6-18 GHz range. This poses a problem that makes it difficult to compensate for roll-off, causing these MMICs to have poor performance and low functional yield in frequency response flatness. Traditionally, the selection of 0,5 micron gates over l/4 micron gates is due to low cost, high yield, and
This was because they lacked a reproducible technology to manufacture micron-long gates. The use of 1/4 micron gate field effect transistors in broadband MMICs
This is highly desirable as it eases the problem of compensating for roll-off and provides a flatter frequency response than devices using longer gates.

Prior art attempts to manufacture short gate lengths fall into three major categories. namely, electron beam lithography, deep UV lithography, and conventional lithography with angular deposition. Each of these techniques has certain drawbacks, as discussed below. i! In the case of child beam lithography, it is possible to use such a process to write patterns of 1/4 micron or smaller. However, the high cost and low throughput of electron beam lithography equipment makes it uninteresting for use in MMIC production. Also, when using e-beam lithography, it must be combined with optical lithography, and using these lithography together introduces additional alignment air between different mask levels, reducing yield. let Also, electron beam lithography requires a different resist than that used in optical lithography, and thus requires additional material processing in processes that use both optical and electron beam lithography.

Deep UV light (wavelength between 206 and 220 nm) is 0.5
It is used to form geometries for submicron gate lengths. However, quarter-micron geometries are approaching the resolution limits of deep U lithography, and pushing deep U lithography to its resolution limits degrades critical dimensional control and correspondingly reduces yield. decrease. Furthermore, deep UV lithography for gate lengths below 0.5 microns
It is necessary to use contact printing to generate these small gate lengths, and contact printing processes are known to produce more defects than step-and-repeat projection lithography.

In either of the two processes described above for forming the gate, the gate length is defined by the process of patterning a mask with an aperture equal in length to the ultimately desired gate length. For example, with reference to FIG. 1, a typical conventional process will be described using a diagram shown in highly simplified form and significantly enlarged in size for illustrative purposes. At the starting point, for example Ga
An insulating layer 2 is applied onto the body l, which can be made of As, to cover the surface 3. Insulation N2 is typically comprised of silicon dioxide material. An opening 4 is established in the silicon dioxide layer 2 with a length shown as . The length is equal to the ultimate desired gate length for the gate material to be subsequently deposited. After forming the opening 4, a photoresist 5 is applied. The step of applying photoresist 5 is, of course, carried out so that the photoresist covers the entire surface and is then selectively removed to provide the configuration as shown in FIG. Following the procedure described above, the gate material is deposited by a typical process of Mogan deposition. FIG. 2 shows a commonly encountered configuration resulting from the application of a gate material, and because of the difficulties encountered in this process, the gate material 6 is deposited on the surface 3 within the opening 4. Not only is the opening 4
It is shown that there is also a tendency to deposit in the upper region of the opening 4 and to block the upper part of the opening 4. This, of course, creates a void in the area 4 and a gate metal with a small cross-sectional area, which creates undesirable microwave losses.

A third category of prior art, conventional lithography with angular deposition, is illustrated in FIGS. 3-5. Referring to FIG. 3, for a conventional lithographic angle deposition process, a 1/4 micron gate can also be formed by printing a 1 micron long opening and then depositing the gate material from a non-perpendicular direction. be. Referring to FIG. 3, in this process a first insulating material 7, typically silicon dioxide, is applied to the surface 8 of the semiconductor body 9, and for example 1 micron (at the edge of the silicon dioxide material 7 on the left) The gate material is deposited at an angle, with the dotted line 11 extending to the surface of the semiconductor body 9. The angle of the deposition source, which is an impinging point source, is shown. As can be seen with reference to FIG. 3, by using the angular technique, the gate material 12 is deposited less than the entire length of the aperture 10, so that the surface 8 spans a length less than the initial 1 micron aperture. Covered with gate material. The space indicated by reference numeral 13 is generated by this technique for the same reason that the space is created in FIG. The gate length produced by this technique is very sensitive to the angle of incidence of deposition and is therefore inherently non-uniform on a single wafer with a large number of devices on which the gate is deposited;
Additionally, due to the angular sensitivity characteristics of this process, the formed gate lengths are non-uniform from wafer to wafer. For example, for a 1 micron thick resist, the variation in gate length due to angle of incidence variation is 0.03 microns/degree. An angular variation of ±4 degrees produces a 50% variation in the target gate length. Furthermore, even assuming that the atoms are emitted isotropically from a point source, the metal vapor does not have a single "angle of incidence" since the atoms have a transmission angle of . To obtain a condition of one "angle of incidence", the wafer is positioned far away from the point source such that the wafer extends over a small solid angle with respect to the point source.

This is illustrated in FIG. 4, where the solid angle denoted ω indicates the angle of projection of the vapor as metal atoms from the point source 14. As is known to those skilled in the art, a dome is positioned above the point source and has an aperture through which atoms can pass.6 Note that in FIG. Such a dome is designated at 15, and the opening is designated at 16. As mentioned above, the body 9 is
It is positioned at an angle, as indicated by .theta. in FIG. It is assumed that the metal atoms remain directed towards the wafer during their flight. However, this assumption becomes invalid when the spacing between the wafer and the point source becomes significant compared to the mean free path of the vaporized atoms. The metal atoms have a finite probability of heating in the other direction before reaching the wafer and thus forming a shadow deposit that makes the true gate length 1 micron. Furthermore, metal atoms that reach the aperture 10 do not have a 100% probability that the depositing gate metal will attach to the sidewalls; some atoms will be re-evaporated and re-deposited in random directions, resulting in shadow deposition. cause Referring to FIG. 5, the thermalized and redeposited gate material is indicated at 14, and it has been completely coated, although it was hoped that the surface 8 of body 9 would not be completely coated. Figure 3 shows that a gate with a length greater than the desired size is formed when coated with the desired, but rarely obtained, angular deposition technique. shows no gate attachment. This angular deposition technique
Individual FE that can tolerate small yields
It is only practical when manufacturing T. Also, with this angular deposition technique, it is impractical, if not impossible, to process more than one wafer at a time, which is an additional drawback.

1-Sword The present invention has been made in view of the above points, and provides a method of forming a gate having a short length for a semiconductor device by eliminating the drawbacks of the prior art as described above. The object of the present invention is to provide a more reliable and cost-effective method for performing the steps than those used in the prior art.

It is another object of the present invention to provide a method of forming short length gates using conventional optical lithography, thus requiring less initial capital investment and higher throughput than e-beam lithography; It is an object of the present invention to provide a method that does not require the use of contact printing.

Yet another object of the present invention is to provide a method for forming narrow length apertures in a coating on a solid surface.

In accordance with one aspect of the present invention, a method of manufacturing a gate of a predetermined length for a semiconductor device is provided, the method comprising: providing a semiconductor body; and applying a first layer of insulating material to the gate. and removing a portion of the first layer of the insulating material at the location where the gate is to be formed to form an area on the surface having a length greater than the predetermined length. applying a second layer of insulating material over the first layer of insulating material in the exposed area where the gate is to be formed;
removing a portion of the second layer of insulating material to define an area on the surface at a location selected for the gate having a length substantially equal to the predetermined length; and applying a gate to the gate-defining area. It is characterized by having each of the above-mentioned steps of applying a substance.

According to another feature of the invention, when carrying out the method as described above, the step of removing a portion of the first layer of insulating material comprises applying a first photoresist to the first layer of insulating material; the steps of: removing a portion of the photoresist to expose a predetermined area on a surface of the first insulating material; and removing the first insulating material in the exposed area by reactive ion etching. It is characterized by

According to another feature of the invention, said reactive ion etching in the last step is carried out using CHF3.

According to a further feature of the invention, in the first process described above, the second layer of insulating material is applied by plasma enhanced CVD.

According to a further feature of the invention, when first performing the process described above, the step of removing a portion of the second layer of insulating material is performed by anisotropic reactive ion etching.

According to a further feature of the invention, in the process just described, the second layer of insulating material is removed by anisotropic ion etching, and the second layer of insulating material is etching with CF4 followed by etching the second layer of insulating material with SF.

According to still further features of the invention, the step of applying a gate material includes applying a second photoresist to the first and second layers of insulating material,
The steps described above include removing the photoresist and depositing the gate material by evaporation.

According to yet another feature of the invention, a method for forming an aperture with a predetermined narrow length in a coating on a surface of a solid includes applying a first coating material to the surface of the solid;
removing a portion of the first coating material at a desired position of the opening to expose an opening on the surface having a length one year larger than the predetermined length; applying a second coating material over the first coating material in the area to be formed and removing a portion of the second coating material to form the predetermined narrow length opening on the surface; The above-mentioned steps are included.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Although the present invention will be described with reference to the formation of a one-part 4 micron gate of the type used in a gallium arsenide MMIC, it will be apparent to those skilled in the art that gates for various other types of semiconductor devices may be formed. It is also possible to form it according to the invention.

The method of the invention is illustrated in Figures 6a to 6j,
It shows the steps of one embodiment used in forming a part 4 micron gate for a GaAs MMIC. Referring to FIG. 6a, there is shown in cross-section and highly exaggerated a portion of a GaAs wafer body 2° upon which it is desired to form a 4 micron gate. In a first step in the process, a first layer 21 of insulating material (which may consist of silicon dioxide) is deposited on the surface of the GaAs wafer 20 by plasma enhanced CVD (as shown in FIG. 6a).
Typical conditions for depositing the 0 layer 21 to a thickness of about 5,000 on 9 are SiH4 at a flow rate of 1105 CC, Neo at a flow rate of 30 SCCM, and an operating pressure of 0.4 Torr. , the zero-order step is to hold the substrate at a temperature of about 200°C, as shown in Figure 6b.
22, such photoresists are commonly manufactured and sold by American Hoechst Corporation, 3070 Highway 22 West, Tumerville, New Jersey 08876. AZ4070 and patterned with an opening 23 of 0.75 to 1 micron extending to the surface of the first insulating material 21. Note that the opening 23 is
The desired gate is centered where it is ultimately to be attached. After defining the opening 23 where the gate is to be deposited, the exposed portion of the first insulating material is removed by reactive ion etching in CHF to produce the structure shown in FIG. 6C. The reactive ion etching process used in removing the first layer of insulating material 21 is typically a 30 mTorr operating pressure at room temperature.
Carry out in a chamber using C) IF3 at a flow rate of 03 CCM. The reactive ion etching in CHF is highly selective for silicon dioxide compared to the first photoresist 22 and creates substantially vertical walls in the first insulating layer 21 regardless of the shape of the first photoresist 22. give.

Following the reactive ion etching shown in Figure 6C, the first photoresist 22 is removed with acetone to produce the structure shown in Figure 6d. The first photoresist 22 is AZ4
If the photoresist is other than 070, the first photoresist 2
Another compound is required to remove 2.

The next step in the process is shown in FIG. 6e and is to apply a second insulating material layer 24, which may be silicon dioxide, for example, over the first insulating material 21. The deposition of the first insulating material layer 21 is described above (discussed with respect to Figure 6a) to form a gate with a length of 1 part 4 microns.
A second layer of insulating material 24 is deposited to a depth of 5,000 nm under the same conditions as described above. As can be seen with reference to FIG. 6e, the second layer of insulating material 24 conformably covers the first layer of insulating material 21 according to the underlying topography, and the layer thickness of the second layer of insulating material 24 is The sidewall thickness designated by reference numeral 25 is formed to be 75-80% of . As will be more clearly understood after discussing the remaining process steps, the conformable recess 30 in the second layer of insulating material 24 defines the gate length to be formed. This length is indicated by reference numeral 31 in Figure 6e.

Following the deposition of the second layer of insulating material 24, the wafer 20 is placed in a reactive ion etching chamber and etched with CF4 to form a second layer of approximately 4,000 layers, as shown in FIG. 6e.
Remove the insulating material layer 24 and then perform a second etch by SF at a low self-bias of about 110 V to remove the second insulating material layer 24 of 1,000 volts from the focused laser beam. Using optical interference patterns,
Establish the thickness of the etch and determine the point at which the etch should stop. It has been found desirable to tightly control the amount of overetching beyond the termination points established by the optical interference pattern. CF, /SF,
RIE is also highly anisotropic. The minimum amount of anisotropy and overetching of the RIE process maintains the width 31 defined by the conformal recess 30 shown in FIG. 6e. Both sides 32a and 3 of the gate defining the opening
The gentle slope of 2b makes it possible to perform gap-free deposition of gate material, as can be seen by referring to Figure 6h. It has been found that varying the etch from CF4 to SF is highly desirable. This is because doing so avoids depositing residual carbon on the surface 29 of the wafer 20 that would prevent good adhesion of the gate material to the surface 29.

Following the reactive ion etching process, a second photoresist 26 is applied over the first and second insulating material layers 21 and 24 and patterned to form openings 27 as shown in FIG. 6g. . The second photoresist 26 is
It can be a material such as AZ4100 manufactured and sold by the aforementioned American Hoechst Corporation and is applied to a thickness of about 1.1 microns.

As can be seen in FIG. 6g, this patterning process is carried out in such a way that the opening 27 is wide enough to reach the connection between the first insulating material layer 21 and the second insulating material N24 on both sides of the opening 27. Following patterning as shown in FIG. 6g, T i /D t as used in GaAs devices.
A suitable gate material such as /A u is applied by a vapor deposition process of a type known to those skilled in the art to produce a configuration as shown in Figure 6h. As mentioned above, due to the sloped portions 32a and 32b of the second insulating material [24], the gate material 28 slopes from the surface 29 to the lower portion of the second photoresist layer 26, as can be seen with reference to Figure 6h. Therefore, a gate is formed without forming a space (cavity) even if it is formed in the prior art as shown in FIGS. 2 and 3.

To complete the process, when the second photoresist 26 is removed, the unnecessary gate material 28 deposited on top of the second photoresist layer 26 is also removed, leaving a completed gate as shown in FIG. It will be done. Removal of second photoresist 26 (and unwanted gate material 28) can be performed by a conventional lift-off process, such as immersion in acetone. It should be noted that the resulting gate 28 is T-shaped, with a predetermined narrow lower portion on the surface 29 and on each of the first and second layers of insulating material 21 and 24. It has a wide top part. This configuration reduces microwave losses over those encountered in prior art gate configurations.

Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. Of course it is.

[Brief explanation of the drawing]

1 to 5 are schematic diagrams illustrating a conventional method of forming gates for semiconductor devices, and FIGS. 6a to 61 are schematic diagrams illustrating a conventional method for forming gates for semiconductor devices, and FIGS. FIG. 3 is a schematic diagram showing a process step of forming an opening having a narrow width and a length, and a process step of forming a gate for a semiconductor device. (Explanation of symbols) 20+GaAs wafer body (main body) 21: First insulating material layer 22: First photoresist 23: Opening 24: Second insulating material layer 28 Two gate recesses

Claims (1)

[Claims] 1. A method for forming a gate of a predetermined length for a semiconductor device, comprising: providing a semiconductor body; applying a first layer of an insulating material to a surface of the body to which a gate is to be applied; removing a portion of the first layer of the insulating material at a location where a gate is to be formed to expose an area on the surface having a length greater than the predetermined length, and the area where the gate is to be formed; applying a second layer of insulating material over the first layer of insulating material, and removing a portion of the second layer of insulating material onto the surface at a location selected for the gate; A method comprising the steps of: defining an area having a length substantially equal to the predetermined length; and applying gate material to the gated area. 2. Claim 1, wherein the step of removing a portion of the first layer of insulating material includes applying a first photoresist to the first layer of insulating material, and removing a portion of the photoresist. exposing a predetermined area on the surface of the first insulating material, and removing the first insulating layer in the exposed area by reactive ion etching. . 3. The method of claim 2, wherein the reactive ion etching step is performed using CHF_3. 4. The method of claim 1, wherein the second layer of insulating material is applied by plasma enhanced CVD. 5. The method of claim 1, wherein the step of removing a portion of the second layer of insulating material is performed by anisotropic reactive ion etching. 6. In claim 5, the reactive ion etching step includes etching the second layer of the insulating material with CF_4, and then etching the second layer of the insulating material with SF_6. A method characterized by comprising: 7. The method of claim 4, wherein the step of removing a portion of the second layer of insulating material is performed by anisotropic ion etching. 8. Claim 7, wherein the reactive ion etching step includes etching the second layer of insulating material with CF_4, and then etching the second layer of insulating material with SF_6. A method characterized by comprising: 9. Any one of claims 1 to 8
The method of claim 1, wherein the first layer of insulating material is formed from silicon dioxide. 10. The method of any one of claims 1 to 8, wherein each of the first and second layers of insulating material is formed from silicon dioxide. 11. The method of claim 9, wherein the semiconductor body is formed from gallium arsenide. 12. The method of claim 10, wherein the semiconductor body is formed from gallium arsenide. 13. According to any one of claims 1 to 8, the step of applying the gate material comprises applying a second photoresist to the first and second layers of the insulating material; A method comprising the steps of removing the second photoresist within a defined area and depositing a gate material by evaporation. 14. Claim 10, wherein the step of applying gate material comprises applying a second photoresist to the first and second layers of insulating material, and applying the second photoresist within the gate-defining area. A method comprising the steps of removing and depositing a gate material by evaporation. 15. A method for forming an aperture with a predetermined width and length in a coating on a surface of a solid, wherein a first coating material is applied to the surface of the solid, and the first coating material is formed at a desired position of the aperture. exposing an opening on the surface having a length greater than the predetermined length, and depositing a second coating material above the first coating material in the area where the predetermined narrow-length opening is to be formed. A method comprising the steps of applying a coating material and removing a portion of the second coating material to form an opening with the predetermined narrow length on the surface.