JP2870579B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a field effect transistor having a heterojunction.

[0002]

2. Description of the Related Art As the frequency of a field effect transistor having a heterojunction is increased and the integration thereof is increased, it is required to shorten the gate length and to make the characteristics uniform. Exposure with an electron beam (EB) is used to form a fine gate. On the other hand, dry etching of a crystal has been studied from the viewpoint of achieving high uniformity of characteristics, and its effect has been reported. In recent years, from the viewpoint of cost reduction of devices, the use of the above-described techniques has been required. However, by simply combining the two techniques, when performing crystal dry etching after EB exposure and development, the EB resist is exposed to the high-density plasma generated in the etching chamber and exposed to plasma electrons. There is a problem that the gate is degenerated and the gate length formed by the subsequent vacuum deposition becomes long, and the controllability deteriorates. That is, the completed gate length is 0.23 μm with respect to the EB opening size of 0.12 μm, which greatly increases the gate length. Incidentally, when the recess is formed by wet etching, the opening dimension is 0.15 μm with respect to the opening dimension of 0.13 μm.

In the prior art, as shown in FIG. 3, a GaAs2 / Al _0.2 Ga _0.8 layer is formed on a semi-insulating GaAs substrate 1 in order to reduce the increase in gate length and the deterioration in controllability due to the degeneracy of the EB resist. As3 / In _0.15 Ga
_On an epitaxial substrate having a heterojunction of _0.85 As4 formed thereon, SiO ₂ 5 was grown to a thickness of 100 nm, and PMMA 7 was subjected to EB exposure and development, followed by application of a resist 10 for optical exposure,
A mixed layer 11 of an EB resist and a resist for optical exposure is formed (FIG. 3A), and using this as a mask, SiO ₂ 5 is etched with an HF-based solution to perform crystal dry etching (FIG. 3).
(B)). Thereafter, vacuum deposition of Mo8 was performed (FIG. 3C). According to this method, the EB opening size is 0.12.
The finished gate length was 0.17 μm with respect to μm.

[0004]

As described above, when an EB resist is used as a mask for dry etching, the resist is exposed to high-density plasma generated in an etching chamber, is exposed to plasma electrons, and the resist degenerates. As a result, there is a problem that the gate length increases and controllability deteriorates. In the prior art described above, since a mixed layer of an EB resist and a resist for optical exposure is formed, and crystal dry etching is performed using the mixed layer as a mask, the increase in gate length and deterioration in controllability due to resist degeneration can be reduced. The point had not been completely resolved.

[0005] Therefore, an object of the present invention is to provide a method of manufacturing a field-effect transistor which can shorten the gate length and improve controllability, and can attain high uniformity of characteristics.

[0006]

In order to completely solve the above-mentioned problems, a method of manufacturing a field effect transistor according to the present invention comprises growing SiO ₂ on a semiconductor epitaxial substrate having a GaAs / AlGaAs heterojunction. , The Si
The method of manufacturing a field effect transistor comprising the step of applying a resist sensitive to electron beam on the O _2, after EB exposure and development, the SiO ₂ and etching with HF based solution, the GaAs citric acid solution selectively etching only the layer, a step of depositing a metal for forming a Schottky junction of the gate by vacuum deposition, the SiO
₂ for additional etching for a desired time with SF ₆ gas or HF solution, selectively etching only the GaAs layer for a desired time with BCl ₃ + SF ₆ gas, and remaining gate by vacuum evaporation. Forming a metal.

In order to completely solve the above problems, a method for manufacturing a field effect transistor according to the present invention is disclosed in US Pat.
In a method for manufacturing a field effect transistor, the method includes a step of growing SiO ₂ on a semiconductor epitaxial substrate having a heterojunction of As / AlGaAs and applying a resist sensitive to an electron beam on the SiO ₂ , Etching the SiO ₂ with an HF solution, etching the GaAs layer and the AlGaAs layer having a desired thickness with an H ₂ SO ₄ solution, and forming a gate Schottky junction by vacuum evaporation. A step of depositing a metal, a step of additionally etching the SiO ₂ with a gas of SF ₆ or an HF-based solution for a desired time, and a step of adding BCl ₃ +
A step of selectively etching only the GaAs layer with a SF ₆ gas for a desired time; and a step of forming the remaining gate metal by vacuum deposition.

[0008]

According to the present invention, only the gate metal for forming the Schottky junction is vapor-deposited before the formation of the recess near the gate and before the dry etching step. Since the gate is formed using the resist as a mask, the gate length is determined by EB exposure and development unless the resist is degenerated in the subsequent dry etching step. In the crystal dry etching process, the metal is coated on the resist surface, so even when exposed to high-density plasma in the etching chamber, the electrons in the plasma pass through the metal covering the resist surface and exit the etching system. The resist is escaped so that the resist is not affected by the electrons and does not degenerate.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a process sectional view of a method for manufacturing a field effect transistor according to a first embodiment of the present invention. FIG.
As shown in FIG.
The _{Al 0.2 Ga 0.8 As3 / In 0.15} Ga 0.85 As4 comprising an epitaxial substrate formed with heterojunction, SiO
₂ 5 100nm growth, PMAA6 (polymethacrylate acid) / PMMA (polymethyl methacrylate) 7 applied to EB exposure and development, for those having 0.13μm of opening dimension (FIG. 1 (a)), SiO ₂ 5
Is etched with an HF-based solution for 30 seconds using the resists 6 and 7 as masks (FIG. 1B). Thereafter, only GaAs2 on the epitaxial substrate is selectively etched with a citric acid-based solution (FIG. 1C). Using a vacuum deposition apparatus, Mo8 is deposited to a thickness of 20 nm to form a gate Schottky junction on the entire surface of the wafer (FIG. 1D). Further SF
_The SiO ₂ 5 is additionally etched with a ₆ gas (or HF solution) for a desired time (FIG. 1E). Using the side-etched SiO ₂ 5 as a mask, only GaAs 2 is selectively etched with a mixed gas of BCl ₃ and SF ₆ for a desired time (FIG. 1F). At this time, since the resists 6 and 7 are covered with metal, there is no degeneration due to plasma electrons. Au / Pt9, which is the remaining gate metal, is deposited by vacuum deposition (FIG. 1 (g)). When the unnecessary metal and the resists 6 and 7 are removed by the lift-off method, a one-stage recess structure T-type gate is completed. The finished gate was 0.15 μm. This is a value equivalent to wet etching.

FIG. 2 is a process sectional view of a method for manufacturing a field effect transistor according to a second embodiment of the present invention. GaAs2 / Al _0.2 Ga _0.8 on a semi-insulating GaAs substrate 1
As3 / an In the _0.15 Ga _0.85 As4 comprising an epitaxial substrate formed with heterojunction, 100 nm and SiO ₂ 5
After growing, applying PMAA6 / PMMA7, EB exposure and development, and having an opening dimension of 0.13 μm (FIG. 2 (a)), SiO ₂ 5 was exposed to HF solution for 30 seconds using resists 6 and 7 as a mask. Etching (Fig. 2
(B)). Thereafter, the desired thickness etched GaAs2 and Al _0.2 Ga _0.8 As3 of the epitaxial substrate in H ₂ SO ₄ based solution (Fig. 2 (c)). 20 nm of Mo8 for forming a gate Schottky junction is deposited on the entire surface of the wafer using a vacuum deposition apparatus (FIG. 2).
(D)). In addition, SF ₆ gas (HF solution may be used)
Additional etching is performed on iO ₂ 5 for a desired time (FIG. 2).
(E)). Desired time SiO ₂ 5 was side-etched with a mixed gas of BCl ₃ and SF ₆ as a mask, GaAs 2
Only this is selectively etched (FIG. 2 (f)). At this time, since the resists 6 and 7 are covered with metal, there is no degeneration due to plasma electrons. Au / Pt9, which is the remaining gate metal, is deposited by vacuum deposition (FIG. 2 (g)). Unnecessary metal and resist 6,7 are removed by lift-off method.
A two-stage recess structure T-type gate is completed. The resulting gate length was 0.15 μm.

[0012]

As described above, according to the present invention,
Even if dry etching is applied to the recess forming step in the formation of a fine gate, no increase in gate length and deterioration in controllability due to resist degeneration does not occur at all, and a gate length equivalent to that when a gate is formed by wet etching and the same. Controllability and high uniformity of characteristics by dry etching were simultaneously realized.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a method for manufacturing a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of a method for manufacturing a field-effect transistor according to a second embodiment of the present invention.

FIG. 3 is a process sectional view of a conventional method for manufacturing a field-effect transistor.

[Explanation of symbols]

1 semi-insulating GaAs substrate _{2 GaAs 3 Al 0.2 Ga 0.8 As} 4 In 0.15 Ga 0.85 As 5 SiO 2 6 PMAA 7 PMMA 8 Mo 9 Au / Pt 10 optical exposure resist 11 mixed layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29 / 80-29/812 H01L 21/3065 H01L 21/28-21/288 H01L 29/47

Claims (3)

(57) [Claims] 1. A method for manufacturing a field-effect transistor, comprising the steps of: growing SiO ₂ on a semiconductor epitaxial substrate having a GaAs / AlGaAs heterojunction and applying a resist sensitive to an electron beam on the SiO ₂ . After EB exposure and development, a step of etching the SiO ₂ with an HF-based solution, a step of selectively etching only the GaAs layer with a citric acid-based solution, and a step of forming a metal forming a Schottky junction of a gate by vacuum evaporation. A step of vapor-depositing, a step of additionally etching the SiO ₂ with a gas of SF ₆ or an HF-based solution for a desired time, and a step of adding BCl ₃ + SF
_6. A method for manufacturing a field-effect transistor, comprising: a step of selectively etching only the GaAs layer for a desired time with the gas of No. ₆ ; and a step of forming remaining gate metal by vacuum deposition. 2. A method for manufacturing a field effect transistor, comprising the steps of: growing SiO ₂ on a semiconductor epitaxial substrate having a GaAs / AlGaAs heterojunction and applying a resist sensitive to an electron beam on the SiO ₂ . After EB exposure and development, a step of etching the SiO ₂ with an HF solution, and a step of etching the GaAs with an H ₂ SO ₄ solution.
Etching the AlGaAs layer and the AlGaAs layer having a desired thickness, depositing a metal forming a Schottky junction of the gate by vacuum deposition, and subjecting the SiO ₂ to a gas of SF ₆ or an HF solution for a desired time. Performing an additional etching step and the above-mentioned Ga for a desired time with a gas of BCl ₃ + SF _6.
A method for manufacturing a field effect transistor, comprising: a step of selectively etching only an As layer; and a step of forming a remaining gate metal by vacuum deposition. 3. The method according to claim 1, wherein the resist is PMMA.