JPH05291300A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05291300A
JPH05291300A JP11825992A JP11825992A JPH05291300A JP H05291300 A JPH05291300 A JP H05291300A JP 11825992 A JP11825992 A JP 11825992A JP 11825992 A JP11825992 A JP 11825992A JP H05291300 A JPH05291300 A JP H05291300A
Authority
JP
Japan
Prior art keywords
insulating film
inclined surface
semiconductor substrate
gate electrode
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11825992A
Other languages
Japanese (ja)
Other versions
JP3081361B2 (en
Inventor
Daijiro Inoue
大二朗 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP04118259A priority Critical patent/JP3081361B2/en
Publication of JPH05291300A publication Critical patent/JPH05291300A/en
Application granted granted Critical
Publication of JP3081361B2 publication Critical patent/JP3081361B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To provide a method of manufacturing semiconductor device to form a gate electrode of a short gate length with good reproducibility and uniform distribution within the surface by a photolithography. CONSTITUTION:An SiO2 insulating film 2 is deposited on a GaAs semiconductor substrate 1 having horizontal surfaces 21, 21 and an inclined surface 22. When the horizontal planes 21, 21 of the GaAs semiconductor substrate 1 is vertically irradiated with plasma by the ECR plasma CVD method, an insulating film 2 formed on the horizontal surfaces 21, 21 is formed as a dense film with an adequate ion bombardment. Meanwhile, the insulating film 2 formed on the inclined surface 22 is easily etched with weak ion bombardment. A photoresist 3 is deposited on the insulating film 2 and an aperture 6 exposing only the inclined surface 22 is formed on the insulating film 2 with the etching. A gate electrode 5 is formed at the aperture 6 by the lift-off method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法、
特に化合物半導体トランジスタのゲート電極の形成方法
に関する。
BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
In particular, it relates to a method for forming a gate electrode of a compound semiconductor transistor.

【0002】[0002]

【従来の技術】GaAs系の化合物半導体を用いたトランジ
スタは高周波用デバイスとして重要であり、中でも金属
−半導体接触電界効果トランジスタ( Metal Semicondu
ctorField Effect Transistor :MESFET)は、集積回路
(IC)用デバイスとして広く研究されている。このMESF
ETの高周波動作特性の向上には、そのゲート長の短縮が
極めて有効な手段であり、ゲート長を短縮すべくその製
造工程において様々な工夫がなされている。
2. Description of the Related Art Transistors using GaAs-based compound semiconductors are important as high-frequency devices, and particularly metal-semiconductor contact field effect transistors (metal semiconductors).
ctorField Effect Transistor (MESFET) has been widely studied as a device for integrated circuits (ICs). This MESF
To improve the high-frequency operating characteristics of ET, shortening the gate length is an extremely effective means, and various measures have been taken in the manufacturing process to shorten the gate length.

【0003】通常の光リソグラフィ技術でゲート電極を
形成した場合は、そのゲート長は略0.5 μmが限界であ
る。このため、ゲート電極を斜め蒸着させる方法、又は
ダミーゲートを形成する方法等により、ゲート長を短く
する工夫がなされている。
When the gate electrode is formed by the usual photolithography technique, the gate length is limited to about 0.5 μm. Therefore, the gate length is shortened by a method of obliquely vapor-depositing the gate electrode, a method of forming a dummy gate, or the like.

【0004】[0004]

【発明が解決しようとする課題】図1は、従来の斜め蒸
着法によりゲート電極を形成する工程を示す模式的断面
図である。図1(a) に示すようにGaAs半導体基板1上に
絶縁膜2を形成する。この表面にフォトレジスト3を堆
積させ、開口部を形成する。そして斜め上方から金属4
を蒸着すると、フォトレジスト3表面と開口部底面の片
側に金属が蒸着する。図1(b) に示すように開口部底面
の金属が蒸着されなかった部分の絶縁膜2をエッチング
し、こうして形成された開口部にゲート電極5をリフト
オフ法により形成する。
FIG. 1 is a schematic sectional view showing a step of forming a gate electrode by a conventional oblique vapor deposition method. An insulating film 2 is formed on a GaAs semiconductor substrate 1 as shown in FIG. Photoresist 3 is deposited on this surface to form an opening. And metal 4 from diagonally above
Is vapor-deposited, metal is vapor-deposited on the photoresist 3 surface and one side of the bottom surface of the opening. As shown in FIG. 1B, the insulating film 2 on the bottom of the opening where the metal has not been vapor-deposited is etched, and the gate electrode 5 is formed in the opening thus formed by the lift-off method.

【0005】このような方法でフォトレジスト開口部の
略2分の1のゲート長のゲート電極を形成することがで
きる。しかしながら、蒸着角度の違いにより、またフォ
トレジスト3の膜厚のばらつきにより、ゲート長が変化
したり、ゲート電極の面内分布均一性が悪化したりする
問題があった。
By such a method, a gate electrode having a gate length which is about ½ of the photoresist opening can be formed. However, there are problems that the gate length is changed and the in-plane distribution uniformity of the gate electrode is deteriorated due to the difference in vapor deposition angle and the variation in the film thickness of the photoresist 3.

【0006】また、ダミーゲートを形成する方法では、
形成したダミーゲートを細くしてパターン反転するが、
ダミーゲートを細くする過程において、再現性が悪くま
た面内分布均一性も悪くなる問題があった。
Further, in the method of forming the dummy gate,
The formed dummy gate is made thin and the pattern is inverted,
In the process of thinning the dummy gate, there was a problem that reproducibility was poor and in-plane distribution uniformity was poor.

【0007】また、ゲート長を短くするために電子線リ
ソグラフィ技術を用いる方法があるが、露光に多大な時
間を要し、スループットが悪いという問題があった。
There is also a method of using an electron beam lithography technique for shortening the gate length, but it takes a lot of time for exposure and there is a problem that throughput is poor.

【0008】本発明は、かかる事情に鑑みてなされたも
のであり、光リソグラフィにより短ゲート長のゲート電
極を再現性良く、またその面内分布が均一になるように
形成できる、半導体装置の製造方法を提供することを目
的とする。
The present invention has been made in view of the above circumstances, and manufactures a semiconductor device in which a gate electrode having a short gate length can be formed by photolithography with good reproducibility and a uniform in-plane distribution. The purpose is to provide a method.

【0009】[0009]

【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、化合物半導体基板上に堆積された絶縁膜
にエッチングを施し、これによって形成された開口部に
ゲート電極を形成して半導体装置を製造する方法におい
て、化合物半導体基板に傾斜面を形成する工程と、前記
化合物半導体基板の水平面及び傾斜面に絶縁膜を夫々エ
ッチング速度を異ならせるべく堆積する工程と、前記絶
縁膜に前記傾斜面のみを露出させた前記開口部を形成す
る工程とを有することを特徴とする。
According to the method of manufacturing a semiconductor device of the present invention, an insulating film deposited on a compound semiconductor substrate is etched, and a gate electrode is formed in an opening formed by the etching to form a semiconductor. In the method of manufacturing a device, a step of forming an inclined surface on a compound semiconductor substrate, a step of depositing an insulating film on a horizontal surface and an inclined surface of the compound semiconductor substrate so as to have different etching rates, and the inclination film on the insulating film. And a step of forming the opening in which only the surface is exposed.

【0010】[0010]

【作用】まず、本発明の基本的原理を説明する。図2は
GaAs半導体基板上にゲート電極を形成する工程を示す模
式的断面図である。図2(a) に示すように、水平面21,2
1 及び傾斜面22を有するGaAs半導体基板1上にSiO2
の絶縁膜2を堆積する。この堆積の際に ECRプラズマCV
D 法を用いた場合は、GaAs半導体基板1の水平面21,21
に、垂直にプラズマを照射する。この水平面21,21 上に
は、適度なイオン衝撃による緻密な絶縁膜2が形成され
る。一方、傾斜面22上には、イオン衝撃が弱いために、
エッチングされ易い絶縁膜2が形成される。この傾斜面
22上の絶縁膜2は、水平面21,21 上の絶縁膜2よりもエ
ッチング速度が速い。
First, the basic principle of the present invention will be described. Figure 2
It is a schematic cross section showing a process of forming a gate electrode on a GaAs semiconductor substrate. As shown in Fig. 2 (a), horizontal planes 21,2
1 and SiO 2 on the GaAs semiconductor substrate 1 having the inclined surface 22
Insulating film 2 is deposited. ECR plasma CV during this deposition
When the D method is used, the horizontal planes 21 and 21 of the GaAs semiconductor substrate 1
Then, the plasma is vertically irradiated. A dense insulating film 2 is formed on the horizontal planes 21 by the appropriate ion bombardment. On the other hand, on the inclined surface 22, since the ion impact is weak,
The insulating film 2 that is easily etched is formed. This slope
The insulating film 2 on 22 has a higher etching rate than the insulating film 2 on the horizontal surfaces 21, 21.

【0011】この後、絶縁膜2をエッチングする。図2
(b) に示すように絶縁膜2上にフォトレジスト3を堆積
し、傾斜面22を含んだ部分を光リソグラフィによりパタ
ーニングする。そしてエッチングにより絶縁膜2に開口
部6を形成する。上述したように、傾斜面22上に形成さ
れた絶縁膜2は、水平面21,21 上に形成された絶縁膜2
よりもエッチング速度が速いために、傾斜面22のみが露
出するようにエッチングすることが可能となる。また、
絶縁膜2をエッチングする際のパターニングに、精密さ
を必要としない。このように形成された開口部6に、図
2(c) に示すようにゲート電極5をリフトオフ法により
形成する。
After that, the insulating film 2 is etched. Figure 2
As shown in (b), a photoresist 3 is deposited on the insulating film 2, and the portion including the inclined surface 22 is patterned by photolithography. Then, the opening 6 is formed in the insulating film 2 by etching. As described above, the insulating film 2 formed on the inclined surface 22 is the insulating film 2 formed on the horizontal surfaces 21, 21.
Since the etching rate is faster than that, it is possible to perform etching so that only the inclined surface 22 is exposed. Also,
The patterning when etching the insulating film 2 does not require precision. In the opening 6 thus formed, the gate electrode 5 is formed by the lift-off method as shown in FIG. 2 (c).

【0012】本発明の半導体装置の製造方法では、エッ
チング速度の差により選択的にGaAs半導体基板の傾斜面
のみを露出させ、ここにゲート電極が形成されるため、
傾斜面の長さがゲート長となり、ゲート長を制御しなが
ら定められた位置にゲート電極を形成することができ
る。
In the method of manufacturing a semiconductor device of the present invention, only the inclined surface of the GaAs semiconductor substrate is selectively exposed due to the difference in etching rate, and the gate electrode is formed there.
The length of the inclined surface becomes the gate length, and the gate electrode can be formed at a predetermined position while controlling the gate length.

【0013】[0013]

【実施例】以下、本発明をその実施例を示す図面に基づ
き具体的に説明する。図3は、本発明によりMESFETを製
造する工程を示す模式的断面図である。まず、図3(a)
に示すように、GaAs半導体基板1に2000Åのメサエッチ
ングを行い、水平面と傾斜面とを形成する。次にSiイ
オン注入及び活性化アニールにより中央にn層7を、そ
の両側にソース,ドレイン領域形成部分となるn+
8,8を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments thereof. FIG. 3 is a schematic cross-sectional view showing a process of manufacturing MESFET according to the present invention. First, Fig. 3 (a)
As shown in, the GaAs semiconductor substrate 1 is mesa-etched to 2000 Å to form a horizontal plane and an inclined plane. Next, an n layer 7 is formed in the center by Si ion implantation and activation annealing, and n + layers 8 and 8 to be source and drain region forming portions are formed on both sides thereof.

【0014】図3(b) に示すように、 ECRプラズマCVD
法を用いて、GaAs半導体基板1の水平面に垂直にプラズ
マを照射する。GaAs半導体基板1の表面にSiO2 の絶
縁膜2を堆積する。傾斜面上に形成された絶縁膜2を含
んだ部分を光リソグラフィによりパターニングし、図3
(c) に示すように、エッチングにより絶縁膜2に開口部
6を形成する。水平面上の絶縁膜2と傾斜面上の絶縁膜
2とは上述したように、緻密な膜質の水平面と弱い膜質
の傾斜面とで形成されており、弱い膜質の傾斜面上の絶
縁膜2の方がエッチング速度が速いので、傾斜面のみを
露出することができる。これにより、開口部6の底部は
GaAs半導体基板1の傾斜面のみとなる。次に図3(d) に
示すように開口部6にゲート電極5をリフトオフ法によ
り形成し、図3(e) に示すように、オーミック電極9,
9を形成してMESFETが製造される。
As shown in FIG. 3 (b), ECR plasma CVD
Method is used to irradiate plasma vertically to the horizontal plane of the GaAs semiconductor substrate 1. An SiO 2 insulating film 2 is deposited on the surface of the GaAs semiconductor substrate 1. The portion including the insulating film 2 formed on the inclined surface is patterned by photolithography,
As shown in (c), the opening 6 is formed in the insulating film 2 by etching. As described above, the insulating film 2 on the horizontal surface and the insulating film 2 on the inclined surface are formed by the horizontal surface of the dense film quality and the inclined surface of the weak film quality. Since the etching rate is faster, only the inclined surface can be exposed. As a result, the bottom of the opening 6
Only the inclined surface of the GaAs semiconductor substrate 1 is provided. Next, the gate electrode 5 is formed in the opening 6 by the lift-off method as shown in FIG. 3 (d), and the ohmic electrode 9 is formed as shown in FIG. 3 (e).
9 is formed and MESFET is manufactured.

【0015】このように形成されたMESFETのゲートは、
ゲート長を短く制御され、面内分布良く形成されてい
る。
The gate of the MESFET thus formed has
The gate length is controlled to be short and the in-plane distribution is good.

【0016】[0016]

【発明の効果】以上のように、本発明の半導体装置の製
造方法においては、半導体基板の傾斜面の長さがゲート
長となるため、短ゲート長のゲート電極が再現性良く形
成され、またその面内分布を均一にして形成される等、
本発明は優れた効果を奏する。
As described above, in the method of manufacturing a semiconductor device of the present invention, since the length of the inclined surface of the semiconductor substrate becomes the gate length, a gate electrode having a short gate length is formed with good reproducibility. It is formed by making its in-plane distribution uniform, etc.
The present invention has excellent effects.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の斜め蒸着法によりゲート電極を形成する
工程を示す模式的断面図である。
FIG. 1 is a schematic cross-sectional view showing a step of forming a gate electrode by a conventional oblique vapor deposition method.

【図2】GaAs半導体基板上にゲート電極を形成する工程
を示した模式的断面図である。
FIG. 2 is a schematic cross-sectional view showing a step of forming a gate electrode on a GaAs semiconductor substrate.

【図3】本発明によりMESFETを製造する工程を示す模式
的断面図である。
FIG. 3 is a schematic cross-sectional view showing a process of manufacturing a MESFET according to the present invention.

【符号の説明】[Explanation of symbols]

1 GaAs半導体基板 2 絶縁膜 3 フォトレジスト 5 ゲート電極 6 開口部 21 GaAs半導体基板の水平面 22 GaAs半導体基板の傾斜面 1 GaAs semiconductor substrate 2 Insulating film 3 Photoresist 5 Gate electrode 6 Opening 21 Horizontal surface of GaAs semiconductor substrate 22 Sloped surface of GaAs semiconductor substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 化合物半導体基板上に堆積された絶縁膜
にエッチングを施し、これによって形成された開口部に
ゲート電極を形成して半導体装置を製造する方法におい
て、 化合物半導体基板に傾斜面を形成する工程と、前記化合
物半導体基板の水平面及び傾斜面に絶縁膜を夫々エッチ
ング速度を異ならせるべく堆積する工程と、前記絶縁膜
に前記傾斜面のみを露出させた前記開口部を形成する工
程とを有することを特徴とする半導体装置の製造方法。
1. A method for manufacturing a semiconductor device by etching an insulating film deposited on a compound semiconductor substrate and forming a gate electrode in an opening formed by the etching, wherein an inclined surface is formed on the compound semiconductor substrate. And a step of depositing an insulating film on the horizontal surface and the inclined surface of the compound semiconductor substrate so as to have different etching rates, and a step of forming the opening in which the inclined surface is exposed in the insulating film. A method of manufacturing a semiconductor device, comprising:
JP04118259A 1992-04-10 1992-04-10 Method for manufacturing semiconductor device Expired - Fee Related JP3081361B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04118259A JP3081361B2 (en) 1992-04-10 1992-04-10 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04118259A JP3081361B2 (en) 1992-04-10 1992-04-10 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05291300A true JPH05291300A (en) 1993-11-05
JP3081361B2 JP3081361B2 (en) 2000-08-28

Family

ID=14732199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04118259A Expired - Fee Related JP3081361B2 (en) 1992-04-10 1992-04-10 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3081361B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101103775B1 (en) * 2008-11-21 2012-01-06 페어차일드코리아반도체 주식회사 GaN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
CN109052311A (en) * 2018-07-06 2018-12-21 中国工程物理研究院电子工程研究所 A method of preparing all covering side electrodes

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109052310B (en) * 2018-07-06 2021-07-23 中国工程物理研究院电子工程研究所 Method for preparing partially covered side electrode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101103775B1 (en) * 2008-11-21 2012-01-06 페어차일드코리아반도체 주식회사 GaN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
CN109052311A (en) * 2018-07-06 2018-12-21 中国工程物理研究院电子工程研究所 A method of preparing all covering side electrodes
CN109052311B (en) * 2018-07-06 2021-07-23 中国工程物理研究院电子工程研究所 Method for preparing all-covered side electrode

Also Published As

Publication number Publication date
JP3081361B2 (en) 2000-08-28

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