JPH02251850A - Mask for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an etchant from leaking at the time of etching by arranging chip patterns circularly so that none of them do not touch the edges of a semiconductor wafer. CONSTITUTION:After making mask matching of a reverse surface mask 1 for a pressure sensor and the semiconductor wafer 2, the semiconductor wafer 2 is exposed to the chip patterns 1a of the reverse surface mask 1 for the pressure sensor and developed to form a pattern, and then an O ring 3 is set at the edge parts of the semiconductor wafer 2, which is to be etched. At this time, the chip patterns 1a of the reverse surface mask 1 for the pressure sensor are arranged circularly without touching the edges of the semiconductor wafer 2. Consequently, no chip pattern is present beneath the O ring 3 at the time of the etching, so no etchant leaks.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit mask, and particularly to a back mask for a pressure sensor used when etching a silicon diaphragm or the like.

[Conventional technology]

FIG. 2 is a plan view showing a conventional back mask for a pressure sensor of this type. In the figure, 1 is a back mask for a pressure sensor, 1a is a chip pattern arranged on the back mask 1 for a pressure sensor, lb is the outer frame of the pressure sensor back mask 1.

2 indicates the position of the semiconductor wafer during mask alignment, and 3 indicates the position of the O-ring during etching.

In the conventional back mask 1 for a pressure sensor, a chip pattern is arranged up to the edge of the semiconductor wafer 2. When etching the back side of a silicon diaphragm for a pressure sensor, an O-ring 3 is installed at the edge of the semiconductor wafer 2, as shown in FIG. Therefore, the chip pattern is placed under the O-ring 3.

[Problem to be solved by the invention]

In the conventional pressure sensor back mask 1, the chip pattern is placed under the O-ring 3, so that the etching solution may leak.

This invention was made to solve the above-mentioned problems, and the chip pattern under the O-ring is removed to prevent the etching solution from leaking.

[Means to solve the problem]

In the semiconductor integrated circuit mask according to the present invention, the chip patterns are arranged in a circular shape so as not to overlap the edges of the semiconductor wafer.

[Effect]

In this invention, the chip patterns are arranged in a circular shape so as not to cover the edges of the semiconductor wafer, thereby eliminating leakage of etching solution from the edges of the semiconductor wafer.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained based on FIG. 1. In FIG. 1, 1 is a pressure sensor back mask, la is a chip pattern arranged in a circular shape 1 on the pressure sensor back mask 1, is the outer frame of the back mask 1 for pressure sensor. 2 is the position of the semiconductor wafer 1 during mask alignment, 3
indicates the position of the O-ring during etching.

Next, the operation will be explained. First, the pressure sensor back mask 1 and the semiconductor wafer 2 are mask-aligned, and then the chip pattern la of the pressure sensor back mask 1 is exposed and developed onto the semiconductor wafer 2 to form a pattern. Thereafter, an O-ring 3 is placed on the edge portion of the semiconductor wafer 2 and etching is performed.

In this embodiment, the chip pattern 1a of the pressure sensor back mask 1 is arranged in a circular shape, and is formed so as not to overlap the edge of the semiconductor wafer 2.

That is, during etching, since there is no chip pattern under the O-ring 3, there is no leakage of the etching solution.

In addition, although the above-mentioned example explained the back mask for pressure sensors, it can also be applied to masks for other semiconductor integrated circuits.

〔Effect of the invention〕

As described above, in this invention, the chip pattern of the semiconductor integrated circuit mask is arranged in a circular shape so as not to cover the edge of the semiconductor wafer, so that the etching solution is prevented from leaking during etching. Furthermore, since no chip pattern is formed on the edge of the semiconductor wafer, there is an effect that wafer cracks, chips, etc. are reduced.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a mask for a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a plan view showing a conventional back mask for a pressure sensor. In the figure, 1 is a mask for a pressure sensor, Ia is a chip pattern, lb is an outer frame, 2 is a position of a semiconductor wafer during mask alignment, and 3 is an O-ring position during etching. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] A mask for semiconductor integrated circuits, characterized in that chip patterns are arranged in a circular shape so as not to cover the edge of a semiconductor wafer.