JPS61224421A - Alignment of pattern - Google Patents

Abstract

PURPOSE:To enable to align a pattern with the surface or back of silicon even after silicon etching process while reducing the pit size by a method wherein, CONSTITUTION:When the first pattern is formed using the first exposure mask, quadraconical pit is formed on a part of the first alignment pattern 1 by silicon.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a pattern alignment method for a mask for pattern exposure of integrated circuits, and relates to a pattern alignment method that improves the alignment pattern of a mask for silicon etching by %. Regarding the method.

(Prior art and its problems) In the manufacture of silicon integrated circuits, a pattern exposure mask is used to form fine patterns, and photolithographic &
A pattern is formed by the principle. Integrated circuits are created by overlaying multiple pattern exposure masks onto a reference pattern to form a pattern, which is then oxidized.

It is made through processes such as widening and arranging S. The shape of the 0 alignment pattern used for this superimposition is generally shown in FIG. 5. FIG. 5 is an example of a case in which patterned storage light masks from three companies are superimposed. When using a negative resist, the method for zero alignment in which the inside of each pattern is a dark area is shown below. First of all, the first alignment pattern makes it seem like the inside is a dark area! Number 1 including 1! Baking the pattern onto the oxidized silicon substrate using a pattern fog light mask. When the oxide film is etched, a cross pattern is formed on the silicon substrate. Next, a second alignment pattern 12 including a second alignment pattern 12 whose interior is a dark area is provided.
Using a pattern exposure mask, print 2!42 mask patterns while aligning them with the oxide film pattern on the silicon substrate. The alignment pattern 13 of *S is placed within the second alignment pattern 12 in the same way as below 0. Normally, the margin between each pattern is 1 to 2 μm. As explained above, alignment is done by applying S to the base pattern formed on the silicon substrate.
This is the process of superimposing Ku's pattern Reiko masks. Therefore, for alignment, a base pattern must be formed on the silicon substrate.

Silicon integrated circuits such as memory circuits and logic circuits do not require the process of deeply etching silicon, but pressure sensors also use silicon as a mechanical material.

; In the case of speed sensors and ultrasonic sensors, there is a process in which silicon is deeply etched. For example, a structural cross-sectional view of a pressure sensor is shown in FIG. A diffused resistor 15 is formed on the front surface of the silicon substrate 14, and a silicon diaphragm 16 is formed by peeling and protruding from the back surface. Etching is generally KO.
H (potassium hydroxide), EDP (ethylene diamine
Anisotropic agents such as pyrocatechol (pyrocatechol) and tender liquids are used. For example, when a (100) plane silicon substrate is anisotropically etched, the brass oblique portion becomes a (111) plane forming an angle of 54.7°. However, the pattern exposure mask is assumed to be parallel to the (110> direction.The pattern for etching the diaphragm from the back side is printed on the back side while aligning with the center of the integrated circuit pattern on the front side. The alignment pattern is also etched, and after etching the oxide film, the silicon is anisotropically etched to form a diacrum, and the alignment pattern is also etched, creating a bib.

A square pyramid hole is formed.

FIGS. 7(a) and 7(b) show a plan view and a sectional view of this pit, respectively. In contrast to the cross-shaped alignment pattern 17, the pit 18 is a square pyramid. This means that the convex corner is (
This is because a high-speed etching surface such as a 331) surface is exposed and the area under the oxide film mask is undercut. When a gap is formed in this way, the effective area of the part that is bonded to the pedestal on the back side of the pressure sensor decreases, resulting in a decrease in bond strength and the possibility that a leak path may occur, resulting in insufficient airtight sealing. comes out.

Further, in the case of a cantilever type ultrasonic sensor, as shown in FIG. 8, the silicon substrate 19 is anisotropically etched from the surface to leave an oxide film cantilever 20. 'If the same alignment pattern as that shown in Fig. 7 is used, the cross-shaped alignment pattern 17 on the surface will be etched in the same way, and the pressure sensor shown in Figs. 7(a) and (b) will be As in the example, pits are formed and the cross pattern disappears. Therefore, after this step.

It was not possible to align accurately with the surface. In other words, alignment can only be made to the extent that the cross-shaped alignment pattern of the next pattern exposure mask is roughly formed within the area formed by silicon etching. For example, after etching silicon, the piezoelectric material Zn0
(zinc oxide) and the upper metal electrode cannot be precisely patterned, making it difficult to miniaturize. For this reason, it may be possible to perform silicon etching at the end of the process, but ZnO is sensitive to acids and alkalis, and a protective film is required during silicon etching and tending, and measures must be taken to prevent etching from the cross section and intrusion of tender fluid. must be given.

(Object of the Invention) An object of the invention is to provide a pattern alignment method in which the pit size is small and alignment can be performed on the front or back surface even after silicon etching.

(Structure of the Invention) The pattern alignment method of the present invention is a method for exposing one surface of a silicon substrate to a first pattern having a plurality of first alignment patterns located in a rectangular shape with a dark interior and not in contact with each other. forming a second mask pattern on the silicon substrate by etching the bits formed by the first alignment pattern when forming the first mask pattern by anisotropic etching using a mask; 0 (Embodiment) Next, the present invention will be described with reference to drawings showing embodiments. . FIGS. 1(a) and 1(b) show alignment patterns in the first embodiment of the present invention. FIG. 1(a) shows an example of overlapping 33 types of pattern exposure masks. It is assumed that the inside of the pattern is a dark area. When forming the first pattern using the first pattern exposure mask,
At the first alignment hole (turn 10), a square pyramidal bit is formed by a silicone etching gummy cutter, as shown in the sectional view taken along line A-A' in FIG. 1(b).Here, 7 The recon wafer is in the (100) plane, the orientation V17 flat is in the (110> direction, the resist is negative type, and the anisotropic etching solution is KOH or EDP. The 0 pit is formed by four (l11) planes. The etching is automatically stopped.The first alignment pattern 1 is not under-forced, it is not larger than the mask pattern, and the etching is not formed.The size of the first alignment pattern 1 The width is arbitrary, and a width of approximately 5 μm square is also possible.

Next, a second pattern exposure mask including the second alignment pattern 2 is aligned with the first alignment pattern l to form a second mask pattern. Furthermore, the third alignment pattern 3
It is possible to align a third pattern exposure mask containing the second alignment pattern 2 to the second alignment pattern 2 to form a third mask pattern.

In this manner, even after silicon etching, patterns can be formed by aligning other pattern exposure masks on the silicon surface one after another with the first alignment pattern serving as a reference.

Next, a second embodiment of the present invention will be described using FIG. 2.

The same numbers as in FIG. 1 indicate patterns in the same layer. The difference from FIG. 1 is that the dimensions of the first alignment pattern 40 are made smaller. The bit size is determined by the first alignment pattern 4.
Since the first alignment pattern is determined by the size of the pit, the smaller the first alignment pattern, the smaller the pit.

FIG. 3 shows an alignment pattern in a third embodiment of the invention. The same numbers as in FIG. 1 indicate patterns in the same layer.

The difference from FIG. 1 is that there are four first alignment patterns 5 to improve alignment accuracy.

The above explanation has been made regarding the case of aligning to the front side of silicone, but it goes without saying that it also applies to the case of aligning to the back side and performing silicon etching.

FIG. 4 shows an alignment pattern in a fourth embodiment of the invention. In each of the first to third embodiments, the plane orientation of the silicon substrate is the (ioo) plane.
Although the explanation has been made assuming that the orientation is in the (110> direction, the present invention is not limited to this, and other surface orientations or orientation flat directions may also be used. This is an example where the plane is the (100) plane and the orientation flat direction is the <100>direction.; Each side of the alignment pattern l of jgl is <110>
It forms an angle of 45° with respect to the orientation direction 7 and 7 so that it is parallel to the direction. When silicon etching is performed, the bit is defined by the first alignment pattern and is under-forced.

will not be hit. Other plane orientations (e.g. (110) plane), orientations 7 and 7 (e.g. <101)
>), each side of the first pattern is <110>
The exposure pattern and the scribe line are parallel to the orientation/7 rat direction.0 (Effects of the Invention) According to the present invention, the bits due to alignment and silicon etching are As the size becomes smaller, it becomes necessary to align other pattern exposure masks in the subsequent process. If a diaphragm pressure sensor is manufactured using this method, since the bit is small, the adhesive area increases, the adhesive strength increases, and the possibility of leakage of the fluid to be measured is reduced. Alternatively, if it is applied to an acceleration sensor, other pattern exposure masks can be accurately overlapped even after silicon etching.

[Brief explanation of drawings]

FIG. 1(a) is a plan view showing the alignment pattern in the first embodiment of the present invention, and FIG. 1(b) is A of FIG. 1(1).
-A sectional view, FIG. 2 is a plan view showing the alignment pattern in the second embodiment of the present invention, FIG. 3 is a plan view showing the alignment pattern in the third embodiment of the present invention, and FIG. 4 5 is a plan view showing an alignment pattern in a third embodiment of the present invention, FIG. 5 is a plan view showing an alignment pattern in a conventional example, and FIG. 6 is a sectional view showing a known diaphragm pressure sensor. FIGS. 7(a) and lb) are a plan view and a sectional view showing a bit formed at the position of an alignment pattern in a conventional example, and FIG. 8 is a sectional view showing a well-known acceleration centimeter. l...sl alignment pattern, 2...
Second alignment pattern % 3...Third alignment pattern, 11...First pattern, 4...
...First alignment pattern, 5...First alignment pattern, 12...Second pattern, 13...
...Third pattern, 14... Silicon substrate, 15... Diffused resistor, 16... Silicon diaphragm, 17... Alignment pattern, 18
·····bit. Rod 1st (b) 71st fi (b) Ascending g figure

Claims (1)

[Claims] When forming a first mask pattern by anisotropically etching one surface of a silicon substrate using a first pattern exposure mask having a plurality of rectangular first alignment patterns located at positions that do not touch each other. aligning a second alignment pattern of a second pattern exposure mask for forming a second mask pattern on the silicon substrate by etching with the pits formed by the first alignment pattern; A pattern alignment method characterized by: