CN110865520B - Photoetching method - Google Patents
Photoetching method Download PDFInfo
- Publication number
- CN110865520B CN110865520B CN201810994609.3A CN201810994609A CN110865520B CN 110865520 B CN110865520 B CN 110865520B CN 201810994609 A CN201810994609 A CN 201810994609A CN 110865520 B CN110865520 B CN 110865520B
- Authority
- CN
- China
- Prior art keywords
- pattern
- semiconductor wafer
- photoetching
- pattern area
- photoresist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
Abstract
The invention provides a photoetching method, which comprises the following steps: providing a semiconductor wafer, and forming a photoresist layer on the semiconductor wafer; aligning the semiconductor wafer with a photoetching plate based on an alignment mark on the surface of the photoetching plate, wherein the photoetching plate also comprises a mark position for isolating a pattern area and a non-pattern area; and exposing and developing the photoresist layer on the surface of the semiconductor wafer to pattern the photoresist layer. In the photoetching process, the photoresist in the non-pattern area at the edge of the wafer is isolated from the pattern area through the marking position, so that the consistency of the pattern on the outermost circle of the wafer is ensured, and the product yield is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a photoetching method.
Background
The manufacture of semiconductor devices requires hundreds of processes, and the photolithography process is a main process step of patterning, which is important in the manufacture of semiconductor devices. With the increasing complexity of semiconductor device structures, more and more photolithography processes are required, and the alignment between photolithography patterns is important to ensure the yield of semiconductor device fabrication.
At present, in the contact/proximity lithography process of semiconductors and LEDs, edge covering process is almost used, namely, no pattern is made on the edge of a wafer within a range of several millimeters. When the edge covering area is completely covered by the photoresist, the unit pattern at the outermost circle of the wafer is connected with the large-area photoresist in the edge covering area, and due to the change of chemical properties of the photoresist in the photoetching process, the outermost circle of the unit pattern possibly cannot meet the process requirements, so that the efficiency is influenced.
Disclosure of Invention
In order to overcome the defects, the invention provides a photoetching method, which effectively solves the technical problem that the outermost circle of patterns cannot meet the technological requirements due to the change of chemical properties of photoresist in the photoetching technological process in the existing production technology.
A lithographic method, comprising:
providing a semiconductor wafer, and forming a photoresist layer on the semiconductor wafer;
aligning the semiconductor wafer with a photoetching plate based on an alignment mark on the surface of the photoetching plate, wherein the photoetching plate also comprises a mark position for isolating a pattern area and a non-pattern area;
and exposing and developing the photoresist layer on the surface of the semiconductor wafer to pattern the photoresist layer.
Further preferably, in the photolithography plate, the mark position for isolating the pattern region and the non-pattern region is formed by a ring of marks surrounding the entire periphery of the pattern region.
Further preferably, the mark bit is 10 to 200 μm from the pattern unit in the pattern region.
Further preferably, the width of the mark bit is 10 to 200 μm.
According to the photoetching method provided by the invention, a circle of mark is made in the periphery of the whole pattern area of the photoetching plate in advance as a mark position, and in the photoetching process, the photoresist in the non-pattern area at the edge of the wafer is isolated from the pattern area through the mark position, so that the consistency of the pattern at the outermost circle of the wafer is ensured, and the product yield is improved. In practical application, the photoetching method provided by the invention is applied to a production process of a silicon-based LED chip, and the yield can be improved by 0.5-5% according to different unit pattern sizes.
Drawings
FIG. 1 is a schematic flow chart of a photolithography method according to the present invention;
FIG. 2(a) is a partial view of the edge of a prior art reticle, and FIG. 2(b) is a cross-sectional view of a semiconductor wafer after photolithography in the prior art;
FIG. 3(a) is a partial view of the edge of a semiconductor wafer after photolithography in accordance with the present invention, and FIG. 3(b) is a cross-sectional view of the semiconductor wafer after photolithography in accordance with the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
Based on the technical problem that in the prior art, the unit pattern at the outermost circle of the wafer is connected with the large-area photoresist in the edge covering area, which may cause that the outermost circle pattern does not meet the process requirement, the present application provides a new photolithography method, as shown in fig. 1, in which the photolithography method includes: s1 providing a semiconductor wafer, forming a photoresist layer on the semiconductor wafer; s2 aligning the semiconductor wafer with the photoetching plate based on the alignment mark on the surface of the photoetching plate, wherein the photoetching plate also comprises a mark position for isolating the pattern area and the non-pattern area; s3 exposes and develops the photoresist layer on the surface of the semiconductor wafer to pattern the photoresist layer.
Specifically, in the photolithography mask, the mark positions for isolating the pattern region and the non-pattern region are formed by a circle of marks surrounding the whole periphery of the pattern region, the distance between the mark positions and the pattern unit in the pattern region is 10-200 μm, and the width of the mark positions is 10-200 μm.
Taking the photoresist as an example of the negative photoresist, the photolithography method is further described as follows:
fig. 2(a) is a partial diagram of the edge of a photolithography mask in the prior art, which includes a pattern region 1 (including a plurality of unit patterns) and a non-pattern region 2 (edge-covered region of the photolithography mask), and fig. 2(b) is a cross-sectional diagram of a semiconductor wafer after photolithography.
Fig. 3(a) shows a partial diagram of the edge of the photolithography mask according to the present invention, which includes a pattern region 1 (including a plurality of unit patterns), a non-pattern region 2 (edge-covering region of the photolithography mask) and a mark position 3 disposed between the two regions, and fig. 3(b) shows a cross-sectional diagram of a semiconductor wafer after photolithography, in which a trench 4 is formed between the pattern region and the non-pattern region to isolate the pattern region from the non-pattern region, particularly isolate the unit patterns of the edge region from the photoresist of the bulk region, thereby effectively avoiding the influence caused by the deformation of the photoresist of the bulk region.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (3)
1. A photoetching method is characterized by being applied to a hemming process, and comprises the following steps:
providing a semiconductor wafer, and forming a photoresist layer on the semiconductor wafer;
aligning the semiconductor wafer with a photoetching plate based on an alignment mark on the surface of the photoetching plate, wherein the photoetching plate also comprises a mark position for isolating a pattern area and a non-pattern area;
exposing and developing the photoresist layer on the surface of the semiconductor wafer to pattern the photoresist layer;
in the photoetching plate, the mark positions for isolating the pattern area and the non-pattern area are formed by a circle of marks surrounding the whole pattern area.
2. The photolithography method according to claim 1, wherein the mark bit is 10 to 200 μm from the pattern unit in the pattern region.
3. The photolithography method according to claim 1, wherein the width of the mark bit is 10 to 200 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810994609.3A CN110865520B (en) | 2018-08-28 | 2018-08-28 | Photoetching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810994609.3A CN110865520B (en) | 2018-08-28 | 2018-08-28 | Photoetching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110865520A CN110865520A (en) | 2020-03-06 |
| CN110865520B true CN110865520B (en) | 2022-03-18 |
Family
ID=69651757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810994609.3A Active CN110865520B (en) | 2018-08-28 | 2018-08-28 | Photoetching method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110865520B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002162730A (en) * | 2000-11-28 | 2002-06-07 | Sony Corp | Reticle, exposing method using the reticle, and semiconductor apparatus produced by using the exposing method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102540699A (en) * | 2012-01-18 | 2012-07-04 | 上海华力微电子有限公司 | Novel photomask reference mark pattern |
| CN105549342B (en) * | 2016-03-08 | 2019-01-08 | 佛山市国星半导体技术有限公司 | A kind of ultraviolet laser photolithography method |
| CN106292176B (en) * | 2016-09-30 | 2023-12-19 | 西安立芯光电科技有限公司 | Photoetching plate matched with contact type photoetching machine in wafer photoetching process and application method thereof |
| CN108227389B (en) * | 2016-12-21 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
-
2018
- 2018-08-28 CN CN201810994609.3A patent/CN110865520B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002162730A (en) * | 2000-11-28 | 2002-06-07 | Sony Corp | Reticle, exposing method using the reticle, and semiconductor apparatus produced by using the exposing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110865520A (en) | 2020-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103246156B (en) | Method for forming self-aligned overlay mark | |
| JP2009238777A (en) | Manufacturing method of semiconductor device | |
| US8440372B2 (en) | Single field zero mask for increased alignment accuracy in field stitching | |
| KR20140096863A (en) | method for forming graphene pattern | |
| US6828071B2 (en) | Method of aligning a wafer and masks | |
| CN110865520B (en) | Photoetching method | |
| CN110648997B (en) | SiC chip photoetching mark forming method | |
| US10593551B2 (en) | Method to increase the process window in double patterning process | |
| CN113745198B (en) | Wafer structure and manufacturing method thereof | |
| CN101354528B (en) | Mask and related photo-etching method | |
| JP2000147743A (en) | Reticle for production of semiconductor and production of semiconductor device using same | |
| KR20110101404A (en) | Method for manufacturing semiconductor device | |
| CN104460246B (en) | A kind of novel lithography alignment method | |
| US11892774B2 (en) | Lithography | |
| US10095115B2 (en) | Forming edge etch protection using dual layer of positive-negative tone resists | |
| CN109765764B (en) | Graphic overlay method for chip return time | |
| US6775920B2 (en) | Method of fabricating semiconductor device comprising superposition inspection step | |
| CN110865519B (en) | Method for aligning wafer in photoetching process | |
| JPS59202632A (en) | Photomask | |
| TWI690768B (en) | Method for designing photomask and semiconductor photolithography process | |
| KR20090127638A (en) | Method for manufacturing semiconductor device | |
| CN114624960A (en) | Large-size chip photoetching splicing method | |
| CN117784528A (en) | Overlay deviation compensation method | |
| KR100412139B1 (en) | Method for forming mask pattern of semiconductor device | |
| KR19980052412A (en) | Reticle for semiconductor device manufacturing and pattern formation method using same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Patentee after: Jingneng optoelectronics Co.,Ltd. Address before: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Patentee before: LATTICE POWER (JIANGXI) Corp. |
|
| CP01 | Change in the name or title of a patent holder |