CN114624960A - Large-size chip photoetching splicing method - Google Patents
Large-size chip photoetching splicing method Download PDFInfo
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- CN114624960A CN114624960A CN202011457478.9A CN202011457478A CN114624960A CN 114624960 A CN114624960 A CN 114624960A CN 202011457478 A CN202011457478 A CN 202011457478A CN 114624960 A CN114624960 A CN 114624960A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
Abstract
The invention provides a large-size chip photoetching and splicing method, which comprises the following steps: 1): designing a splicing photoetching plate, finding out a repetitive small-structure pattern module in a large-size chip, and then manufacturing the repetitive small-structure pattern module on the photoetching plate according to the area of each repetitive and/or non-repetitive small-structure pattern module until all patterns of all small-structure pattern modules are manufactured on a plurality of photoetching plates to form the splicing photoetching plate; 2): carrying out photoetching splicing process on the first layer by adopting a stepping photoetching machine; 3): carrying out photoetching splicing process on a second layer by adopting the stepping photoetching machine; 4): and (4) repeatedly executing the step 3) until the splicing photoetching process of all the layers of the large-size chip is completed. By adopting the photoetching splicing method, the pattern occupancy rate on the photoetching plate can be reduced, and the utilization rate of the effective exposure area of the photoetching plate is greatly improved; in addition, the number of the photoetching plates can be effectively reduced, the cost of the photoetching plates can be reduced, and the exposure speed of a large-size chip can be increased during photoetching.
Description
Technical Field
The invention belongs to the technical field of wafer-level semiconductor photoetching processes, and particularly relates to a photoetching and splicing method for large-size chips.
Background
In the field of semiconductors and Micro Electro Mechanical Systems (MEMS), there are often special devices that require large-sized chips and at the same time have very high requirements for line width and overlay accuracy, for example, the chip size of a full-scale CIS is 36mm x 24mm, and the size of a camera for a studio is 60mm x 60 mm. However, the exposure field of the existing mainstream lithography machine is smaller than the area of the large-sized chip, for example, the maximum size of a single chip that can be exposed by the exposure field of the i-line exposure machine is 22mm × 22mm, and the maximum size of a single chip that can be exposed by the exposure field of the duv-line exposure machine is 25mm × 33 mm. Therefore, for manufacturing the large-size chip exceeding the exposure field of the lithography machine, a graph splicing technology is needed, multiple exposures of a plurality of photomasks are utilized, and a plurality of small-size local modules are spliced into a large-size complete chip.
At present, in the splicing design of a large-size chip photomask layout, an equal division cutting method is generally adopted, for example, the pattern area of the large-size chip is more than 40mm x 40mm, conventional equal division cutting needs to be completed by using 4 photomasks for each layer of photoetching, the exposure speed is low, the photomask replacement process is complicated, and the improvement of the productivity is inhibited; it is also important that the reticle cost be high, thereby increasing the cost of photolithography.
Disclosure of Invention
In view of the above disadvantages of the prior art, the present invention aims to provide a large-size chip photo-etching splicing method, which is used for solving the problems that in the prior art, the exposure speed is slow, the photomask needs to be replaced in a complicated manner, and the increase of the productivity is inhibited, caused by the adoption of an equal division cutting method in the layout splicing design of a large-size chip photomask; in addition, the use of more masks is required, which leads to a problem of high cost of photolithography.
In order to achieve the above and other related objects, the present invention provides a large-sized chip photo-etching splicing method, which is suitable for a pattern module with a repetitive small structure in the large-sized chip, the splicing method comprising:
1): designing a splicing photoetching plate, which comprises the steps of splitting the large-size chip into a plurality of small-structure graphic modules, finding out repetitive small-structure graphic modules, manufacturing the graphs of one or a plurality of different repetitive small-structure graphic modules on one photoetching plate according to the area of each repetitive small-structure graphic module, and manufacturing the graphs of at least one non-repetitive small-structure graphic module on one photoetching plate according to the area of each small-structure graphic module until all the graphs of all the small-structure graphic modules are manufactured on a plurality of photoetching plates to form the splicing photoetching plate;
2): performing a photoetching splicing process of a first layer by adopting a stepping photoetching machine, wherein the photoetching splicing process comprises the steps of carrying out splicing photoetching, etching and photoresist removing on a large-size chip subjected to photoetching on the first layer based on the splicing photoetching plate;
3): performing photoetching splicing process on the second layer by adopting the stepping photoetching machine, wherein the photoetching splicing process comprises the steps of carrying out splicing photoetching, etching and photoresist removing on the large-size chips subjected to photoetching on the second layer based on the splicing photoetching plate;
4): and (4) repeatedly executing the step 3) until the splicing photoetching process of all the layers of the large-size chip is completed.
Optionally, in step 2), an alignment mark is made on a first reticle subjected to photolithography based on the splicing reticle, and after the step 2) is finished, a pattern of the alignment mark is transferred onto the large-size chip to serve as an alignment basis for a subsequent splicing photolithography process for all levels of the large-size chip.
Further, in step 2), the patterns of the small-structure pattern modules located at 4 corners of the large-size chip are manufactured on the first photolithography mask, and the alignment mark is manufactured on the pattern of the small-structure pattern module located at one corner.
Further, in the step 2), the small-structure graphic modules at 4 corners of the large-size chip are repetitive small-structure graphic modules and/or non-repetitive small-structure graphic modules.
Further, in step 2), the first reticle is further manufactured with one or more patterns of different repetitive small structure pattern modules.
Further, step 2) comprises:
2-1) photoetching, etching and removing photoresist on the first layer of photoetching large-size chip based on the patterns of the small-structure pattern modules with 4 corners on the first photoetching plate, so that the patterns on the small-structure pattern modules with 4 corners are transferred onto the large-size chip, and meanwhile, the alignment mark is transferred onto the large-size chip;
2-2) carrying out photoetching, etching and photoresist removing on the large-size chip of the first layer of photoetching based on the graphs of the one or more different repetitive small-structure graph modules on the first photoetching plate and the rest splicing photoetching plates so as to realize the first-layer photoetching process of the large-size chip.
Optionally, the first layer is any one of multiple layers of the large-size chip manufacturing process, and the first layer is subjected to photoetching; the second layer is any layer subsequent to the first layer, and the second layer is subjected to photoetching.
Further, the first layer is a first layer in the large-size chip manufacturing process, and the second layer is a layer immediately subsequent to the first layer.
Optionally, the step-by-step lithography machine is an i-line lithography machine or a duv-line lithography machine.
Optionally, the large-size chip is a far-infrared sensor chip.
As described above, according to the large-size chip photoetching splicing method, when the splicing photomask is prepared, the small-area repetitive structure pattern module in the large-size chip is found in advance, the pattern of the small-area repetitive structure pattern module is manufactured on one photomask, the exposure effect of the complete pattern in the local area of the large-size chip is completed by utilizing the characteristic of repetitive exposure of the stepping photoetching machine, the pattern occupancy rate on the photomask is greatly reduced, and the utilization rate of the effective exposure area of the photomask is greatly improved; in addition, the number of the photoetching plates can be effectively reduced, the cost of the photoetching plates is greatly reduced, the exposure speed of large-size chips during photoetching can be increased, and the productivity is improved.
Drawings
FIG. 1 is a schematic flow chart of the large-size chip photo-etching splicing method of the present invention.
FIG. 2 is a schematic structural diagram of a large-size chip of the large-size chip photo-etching splicing method of the present invention.
Fig. 3 is a schematic structural diagram illustrating a large-size chip split into a plurality of small-structure pattern modules by the large-size chip photo-etching splicing method of the present invention.
Fig. 4 is a schematic structural diagram of a first reticle of a splicing reticle according to an embodiment of the large-size chip lithography splicing method of the present invention.
Fig. 5 and fig. 6 are schematic structural views of the remaining photomasks of the splicing photomask according to the embodiment of the large-size chip photolithographic splicing method of the present invention.
Fig. 7 is a schematic structural diagram of a large-sized chip after performing photolithography, etching and photoresist removal on a first layer of a large-sized chip by using a pattern of a small-structure pattern module with 4 corners on a first reticle according to an embodiment of the large-sized chip photolithography and splicing method of the present invention.
Fig. 8 is a schematic structural diagram of a large-size chip after performing splicing lithography, etching and photoresist removal on a first layer of a large-size chip subjected to lithography based on a splicing reticle in an embodiment of the large-size chip lithography splicing method of the present invention.
Description of the element reference numerals
10 large-size chip
11 little structural pattern module
12 photo-etching plate
13 first mask
14 alignment mark
S1-S4
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a large-size chip lithography splicing method, which is particularly suitable for the case of a pattern module with a repetitive small structure in the large-size chip, and the splicing method includes the following steps:
s1: designing a splicing reticle, which comprises splitting the large-size chip 10 into a plurality of small-structure pattern modules 11 (shown in fig. 2 and 3), finding out repetitive small-structure pattern modules, then manufacturing the patterns of one or more different repetitive small-structure pattern modules on one reticle 12 (shown in fig. 5 and 6) according to the area of each repetitive small-structure pattern module, and simultaneously manufacturing the patterns of at least one non-repetitive small-structure pattern module on one reticle 12 (shown in fig. 4) according to the area of each small-structure pattern module until all the patterns of all the small-structure pattern modules are manufactured on a plurality of reticles 12 to form the splicing reticle;
s2: performing a photoetching splicing process of a first layer by adopting a stepping photoetching machine, wherein the photoetching splicing process comprises the steps of carrying out splicing photoetching, etching and photoresist removing on a large-size chip subjected to photoetching on the first layer based on the splicing photoetching plate;
s3: performing a photoetching splicing process of a second layer by adopting the stepping photoetching machine, wherein the photoetching splicing process comprises splicing photoetching, etching and photoresist removing of a large-size chip subjected to photoetching of the second layer based on the spliced photoetching plate;
s4: and repeating the step S3 until the splicing photoetching process of all the layers of the large-size chip is completed.
As an example, the large-size chip is a chip made of any existing semiconductor material, and in this embodiment, the large-size chip is made of a silicon material.
It should be noted that, in step S1, when designing the splicing reticle, if the small structure pattern blocks 11 formed by splitting the large-sized chip 10 are all repetitive small structure pattern blocks 11, rather than having non-repeating small feature pattern modules, then in designing the tiled reticle, one or more different patterns of repeating small feature pattern modules need only be patterned on a reticle 12, based on the area of each repeating small feature pattern module, such as shown in figure 5, a pattern H, B having 2 different repetitive small feature pattern modules is created on a reticle 12, as shown in figure 6, the number of the patterns E of 1 repetitive small-structure pattern module manufactured on the photoetching plate 12 is determined by the area of the small-structure pattern module and the exposure field area of the stepping photoetching machine. If a plurality of small structural pattern modules 11 formed by splitting the large-size chip 10 have both repetitive small structural pattern modules 11 and non-repetitive small structural pattern modules, then when designing the splicing reticle, a pattern of the non-repetitive small structural pattern module and a pattern of the repetitive small structural pattern module can be made on one reticle 12, as shown in fig. 4, a pattern I, G, C, A of 4 non-repetitive small structural pattern modules and a pattern F, D of 2 different repetitive small structural pattern modules are made on one reticle 12; or only the pattern of the non-repetitive small-structure pattern module can be made on one reticle 12, and the pattern of the repetitive small-structure pattern module can be made on other reticles 12. The above method of how to make the pattern of the small-structure pattern module on one reticle 12 is set according to the specific structure of different large-size chips, and is determined in principle according to the area of each repetitive small-structure pattern module, the area of a non-repetitive small-structure pattern module and the exposure field area of the stepper, and the stepper is considered to be convenient for exposure.
When the splicing photoetching plate is prepared, the small-area repetitive structure pattern module in the large-size chip is found out in advance, the pattern of the small-area repetitive structure pattern module is manufactured on the photoetching plate, the exposure effect of the complete pattern in the local area in the large-size chip is completed by utilizing the characteristic of repetitive exposure of a stepping photoetching machine, the pattern occupancy rate on the photoetching plate is greatly reduced, and the utilization rate of the effective exposure area of the photoetching plate is greatly improved; in addition, the number of the photoetching plates can be effectively reduced, the cost of the photoetching plates is greatly reduced, the exposure speed of large-size chips during photoetching can be increased, and the productivity is improved.
As shown in fig. 4, as an example, in step S2, an alignment mark 14 is formed on the first reticle 13 that is subjected to photolithography based on the splicing reticle, and after step S2 is completed, the pattern of the alignment mark 14 is transferred to the large-size chip 10 to be used as an alignment basis for a subsequent splicing photolithography process for all levels of the large-size chip 10. It is known that, in the process of the chip lithography process, since the first layer lithography can only adopt pre-alignment, the alignment accuracy is poor, and is usually about tens of microns, the first layer lithography pattern of the large-sized chip cannot be completed by using a splicing method, so that a zero-layer lithography plate with an alignment mark pattern is usually required to be manufactured first, so as to make an alignment mark for the subsequent level lithography alignment on the large-sized chip in advance, which adds a lithography plate and further increases the complexity of replacing the lithography plate. According to the invention, the alignment mark 14 is manufactured on the first photoetching plate 13, so that after the photoetching process of the first layer, the alignment mark 14 is formed while the required normal pattern is formed on the large-size chip, and a zero-layer photoetching plate is saved; in addition, the alignment mark 14 is used for alignment in the subsequent splicing lithography process of all layers of the large-size chip 10, so that the alignment mark is only required to be manufactured on one photoetching plate, and each exposure module is not required to manufacture the alignment mark, so that the occupied space of the alignment mark can be effectively reduced, and the alignment precision can be improved.
As shown in fig. 3 and 4, as a further example, in step S2, the patterns of the small structural pattern modules 11 located at 4 corners of the large-sized chip 10 are formed on the first reticle 13, and the alignment mark 14 is formed on the pattern of the small structural pattern module 11 located at one corner, for example, the pattern of the small structural pattern module a. Here, it is not limited whether the small structural pattern module 11 of 4 corners of the large-sized chip 10 is repeated, and the small structural pattern module may be a repetitive small structural pattern module, a non-repetitive small structural pattern module, or a combination of a repetitive small structural pattern module and a non-repetitive small structural pattern module. Since the small structural patterning module 11 with 4 corners of the large-sized chip 10 is an area where each adjacent large-sized chip is adjacent to each other, it is disposed on the same reticle for exposure.
As a further example, as shown in fig. 4, in step S2, the first reticle 13 is further patterned with one or more different repetitive small structure pattern modules. Such as the 2 different repetitive small structure graphics modules F, D of fig. 4. In this case, as a preferred example, the step S2 of the first layer photolithography splicing process includes:
s2-1, performing lithography, etching and photoresist stripping on the large-sized chip 10 by the first lithography layer based on the pattern of the 4 corner small structure pattern modules 11 on the first reticle 13, so as to transfer the pattern on the 4 corner small structure pattern modules 11 to the large-sized chip 10, and simultaneously transfer the alignment mark 14 to the large-sized chip 10;
s2-2, performing photolithography, etching and photoresist removal on the large-size chip 10 subjected to the first layer photolithography based on the patterns of the one or more different repetitive small-structure pattern modules on the first reticle 13 and the other splicing reticles, so as to implement a first layer photolithography process for the large-size chip 10.
It should be noted that, in step S2, the first layer is any one of the plurality of layers in the manufacturing process of the large-size chip 10, and the first layer is a lithography of the any one layer; the second layer is any layer subsequent to the first layer, and the second layer is subjected to photoetching. Preferably, the first layer is a first layer in the manufacturing process of the large-size chip 10, and the second layer is a layer subsequent to the first layer, that is, the photoetching splicing method provided by the invention is used from the first layer in the manufacturing process of the large-size chip 10, so that the improvement of the chip productivity, the improvement of the exposure speed and the improvement of the utilization rate of the effective exposure area of the photoetching plate are more obvious.
By way of example, the stepper may be any type of stepper known in the art, such as an i-line or duv line lithography machine.
In order to further understand the method for photo-lithographically splicing the large-size chips of the present invention, the photo-lithographically process of the far-infrared sensor chip, which is 40mm by 40mm, is described as an example, and a total of 11 photo-lithographically processes are required. The photoetching splicing method comprises the following steps:
1) splitting a large-size chip of the far infrared sensor, namely splitting a large-size chip 10 into 16 small-structure graphic modules 11 shown in fig. 3; then find out the repetitive small-structure pattern module, where the repetitive small-structure pattern module has B1-B2-B, D1-D2-D, F1-F2-F, H1-H2-H, E1-E2-E3-E4-E, and the other 4 small-structure pattern modules A, G, C, I are 4 corners of the large-size chip and also are adjacent areas of each adjacent large-size chip.
2) Making a splicing photoetching plate, and making 3 photoetching plates as splicing photoetching plates of a first layer according to the area of each repetitive small-structure pattern module, the area of 4 corner small-structure pattern modules and the area of a photoetching plate exposure field, wherein as shown in fig. 4, the first photoetching plate 13 is made with patterns of two groups of small-structure pattern modules, the first group is the patterns of 4 corner small-structure pattern modules A, G, C, I, an alignment mark (not shown in the figure) is made in the pattern of the small-structure pattern module A, and the second group is the patterns of 2 different repetitive small-structure pattern modules F, D; as shown in fig. 5, second reticle 12 has 2 different patterns of repetitive small structure pattern modules H, B fabricated thereon; as shown in fig. 6, the third reticle 12 is patterned with 1 repetitive small structure pattern module E.
3) The first layer of photoetching splicing process is carried out by adopting a stepping photoetching machine, and because the small structure pattern modules A, G, C, I of 4 corners are adjacent regions of each adjacent large-size chip, the exposure is convenient, the photoetching of A, G, C, I regions of four corners in all the large-size chips is completed on the substrate silicon at one time based on the patterns of the first group of small structure pattern modules on the first photoetching plate 13, and the patterning and the photoresist removal are etched (as shown in figure 7), so that the patterns on the small structure pattern modules of 4 corners are transferred to the large-size chips 10, and simultaneously the alignment marks are transferred to the large-size chips 10; then, by using the alignment mark in the region A of the small structure pattern module of the large-size chip, sequentially using the patterns of the second group of small structure pattern modules on the first photoetching plate 13, the patterns on the second photoetching plate and the patterns on the third photoetching plate, carrying out photoetching splicing process after aligning the residual region in the first layer of photoetching patterns of the large-size chip; and finally, etching, patterning and photoresist removing are carried out, so that the photoetching splicing process of the first layer of the large-size chip is completed (as shown in figure 8). The process of this step is a key point of this embodiment, that is, the alignment mark is placed in advance in the region a of the first reticle, after one-time photolithography, etching and photoresist removal processes, the normal chip pattern and the alignment mark are both retained, and then the alignment mark in this region is used to complete the alignment post-splicing process of other regions of the first layer pattern of the chip, so that the alignment accuracy between the regions is improved from tens of micrometers to tens of nanometers, even several nanometers.
4) The step-type photoetching machine is adopted to carry out photoetching splicing process of a second layer, the alignment mark on the first layer of the pattern of the large-size chip is utilized, and the splicing photoetching plate in the step 2) is used for realizing the splicing photoetching, etching and photoresist removal of the large-size chip subjected to the photoetching of the second layer, wherein the splicing sequence of the pattern is the same as that of the first layer, but the alignment mark exists after the first layer of the patterning process, so that when the layer is processed, only the photoetching splicing is finished, and then the etching process is carried out once.
5) And repeating the step 4) until the photoetching, etching and photoresist removing processes of the remaining 9 layers of patterns are completed in sequence.
In this embodiment, 11 layers are used for photoetching, and compared with the prior art, the photoetching splicing method of the invention can manufacture one fewer photoetching plate per layer, does not need a zero-layer photoetching plate, can save 12 photoetching plates, greatly reduces the cost of the photoetching plate, can improve the exposure speed of a chip during photoetching, and effectively improves the productivity; in addition, only the alignment mark is left on the first layer of photoetching pattern, the alignment mark is utilized to align in the subsequent layers, only step-by-step photoetching splicing is needed, step-by-step etching is not needed, and photoetching complexity is reduced; finally, only one alignment mark of the photoetching machine needs to be placed, and each exposure module does not need to be placed with the alignment mark, so that the occupied space of the alignment mark is greatly reduced, and the alignment precision is improved.
In summary, the present invention provides a large-sized chip photo-etching splicing method, when a splicing reticle is prepared, a small-area repetitive structure pattern module in a large-sized chip is found in advance, and a pattern thereof is made on a reticle, and the characteristic of repetitive exposure of a stepper is utilized to complete the exposure effect of a complete pattern in a local area in the large-sized chip, thereby greatly reducing the pattern occupancy rate on the reticle, and greatly improving the utilization rate of an effective exposure area of the reticle; in addition, the number of the photoetching plates can be effectively reduced, the cost of the photoetching plates is greatly reduced, the exposure speed of large-size chips during photoetching can be increased, and the productivity is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A large-size chip photoetching and splicing method is suitable for a pattern module with a repetitive small structure in the large-size chip, and is characterized by comprising the following steps:
1): designing a splicing photoetching plate, which comprises the steps of splitting the large-size chip into a plurality of small-structure graphic modules, finding out repetitive small-structure graphic modules, manufacturing the graphs of one or a plurality of different repetitive small-structure graphic modules on one photoetching plate according to the area of each repetitive small-structure graphic module, and manufacturing the graphs of at least one non-repetitive small-structure graphic module on one photoetching plate according to the area of each small-structure graphic module until all the graphs of all the small-structure graphic modules are manufactured on a plurality of photoetching plates to form the splicing photoetching plate;
2): performing a photoetching splicing process of a first layer by adopting a stepping photoetching machine, wherein the photoetching splicing process comprises the steps of carrying out splicing photoetching, etching and photoresist removing on a large-size chip subjected to photoetching on the first layer based on the splicing photoetching plate;
3): performing photoetching splicing process on the second layer by adopting the stepping photoetching machine, wherein the photoetching splicing process comprises the steps of carrying out splicing photoetching, etching and photoresist removing on the large-size chips subjected to photoetching on the second layer based on the splicing photoetching plate;
4): and (4) repeatedly executing the step 3) until the splicing photoetching process of all the layers of the large-size chip is completed.
2. The large-size chip photoetching splicing method according to claim 1, wherein: in the step 2), an alignment mark is manufactured on a first photoetching plate which is used for photoetching based on the splicing photoetching plate, and after the step 2) is finished, the pattern of the alignment mark is transferred to the large-size chip to be used as an alignment basis of the subsequent splicing photoetching process of all the layers of the large-size chip.
3. The large-size chip photoetching splicing method according to claim 2, wherein: in step 2), the patterns of the small-structure pattern modules positioned at the 4 corners of the large-size chip are manufactured on the first photoetching plate, and the alignment mark is manufactured on the pattern of the small-structure pattern module at one corner.
4. The large-size chip photoetching splicing method according to claim 3, wherein: in the step 2), the small-structure graphic modules at 4 corners of the large-size chip are repetitive small-structure graphic modules and/or non-repetitive small-structure graphic modules.
5. The large-size chip photoetching splicing method according to claim 4, wherein: in the step 2), one or more different patterns of the repetitive small-structure pattern module are also manufactured on the first photoetching plate.
6. The large-size chip photoetching and splicing method according to claim 5, wherein; the step 2) comprises the following steps:
2-1) photoetching, etching and removing photoresist on the first layer of photoetching large-size chip based on the patterns of the small-structure pattern modules with 4 corners on the first photoetching plate, so that the patterns on the small-structure pattern modules with 4 corners are transferred onto the large-size chip, and meanwhile, the alignment mark is transferred onto the large-size chip;
2-2) carrying out photoetching, etching and photoresist removing on the large-size chip of the first layer of photoetching based on the graphs of the one or more different repetitive small-structure graph modules on the first photoetching plate and the rest splicing photoetching plates so as to realize the first-layer photoetching process of the large-size chip.
7. The large-size chip photoetching splicing method according to claim 1, wherein: the first layer is any one of the layers of the large-size chip manufacturing process, and the first layer is subjected to photoetching; the second layer is any layer subsequent to the first layer, and the second layer is subjected to photoetching.
8. The large-size chip photoetching and splicing method according to claim 7, wherein: the first layer is a first layer in the large-size chip manufacturing process, and the second layer is a layer immediately subsequent to the first layer.
9. The large-size chip photoetching splicing method according to claim 1, wherein: the stepping photoetching machine is an i-line photoetching machine or a duv-line photoetching machine.
10. The large-size chip photoetching splicing method according to claim 1, wherein: the large-size chip is a far infrared sensor chip.
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