CN117826522A - Method for correcting critical dimension deviation in optical proximity correction - Google Patents
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- 238000012937 correction Methods 0.000 title claims abstract description 124
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- 230000003287 optical effect Effects 0.000 title claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000011161 development Methods 0.000 claims abstract description 12
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 42
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- 239000002356 single layer Substances 0.000 claims description 3
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- 238000004519 manufacturing process Methods 0.000 abstract description 17
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 230000004044 response Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 230000005540 biological transmission Effects 0.000 description 1
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Abstract
A method for critical dimension bias correction in optical proximity correction, comprising: acquiring a first corrected layout; forming a mask plate according to the first corrected layout; acquiring a mask critical dimension load model; providing a substrate and a patterning layer positioned on the substrate; exposing the mask plate to form a plurality of patterned structures on the patterned layer; acquiring a development critical dimension load model; etching the substrate by taking the patterned structure as a mask to form a plurality of device structures; obtaining an etching critical dimension load model; and carrying out optical proximity correction on the first correction layout according to each critical dimension load model to obtain a second correction layout. The size deviation between each adjacent process is obtained in the manufacturing process of the device structure, so that a corresponding critical dimension load model is constructed. And the optical proximity correction is carried out on the first correction layout, so that the dimensional accuracy of the device structure can be effectively improved when the semiconductor manufacturing process is carried out on the basis of the second correction layout.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for correcting critical dimension deviation in optical proximity correction.
Background
In semiconductor fabrication, circuit pattern definition is typically achieved by transferring a circuit pattern in a reticle to a photoresist by exposure and development, and then transferring the pattern to a silicon wafer by etching or the like. Since special areas are required to realize numerous functions in logic circuit technology, the density and variety of patterns in different areas are greatly different, and usually etching bias (etching bias) is also large, and bias compensation of critical dimensions needs to be considered in mask manufacturing. With the continued shrinking of design dimensions, which are approaching the limits of photolithographic imaging systems, multiple patterning techniques are widely used for the definition of the most dense metal lines in the front-end (FEOL) and back-end (BEOL) of advanced semiconductors. Under the severe micro-scale condition, the pattern on one mask plate needs to be split into two mask plates to realize the definition of the pattern, so that more severe pattern changes are generated, and the deviations generated in the photomask manufacturing, photoetching and etching processes need to be uniformly compensated.
However, the optical proximity correction of the prior art still has a number of problems.
Disclosure of Invention
The invention solves the technical problem of providing a critical dimension deviation correction method in optical proximity correction, which is used for fitting and modeling pattern density and critical dimension through the relation between pattern density and critical dimension deviation so as to improve correction precision and correction efficiency.
In order to solve the above technical problems, the technical solution of the present invention provides a method for correcting critical dimension deviation in optical proximity correction, comprising: acquiring a first correction layout, wherein the first correction layout comprises a first area and a second area which are adjacent, the first area is provided with a plurality of first correction patterns, the first correction patterns are of a first size, and the pattern density of the first area is larger than that of the second area; forming a mask plate according to the first correction layout, wherein the mask plate is provided with a plurality of mask patterns corresponding to the first correction patterns, and the mask patterns are of a second size; acquiring a first pattern density, modeling according to the first pattern density and the critical dimension deviation between the first dimension and the second dimension, and acquiring a mask critical dimension load model; providing a substrate, wherein the substrate comprises a base and a patterning layer positioned on the base; exposing the mask plate to form a plurality of patterned structures corresponding to the mask patterns on the patterned layer, wherein the patterned structures have a third size; acquiring a second pattern density, modeling according to the second pattern density and the critical dimension deviation between the second dimension and the third dimension, and acquiring a developing critical dimension load model; etching the substrate by taking the patterned structure as a mask, and forming a plurality of device structures corresponding to the patterned structure on the substrate, wherein the device structures have a fourth size; obtaining a third pattern density, modeling according to the third pattern density and the critical dimension deviation between the third dimension and the fourth dimension, and obtaining an etching critical dimension load model; and compensating the critical dimension of the first correction layout according to the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model, and carrying out optical proximity correction after the compensation of the critical dimension to obtain a second correction layout, wherein the second correction layout is provided with a plurality of second correction patterns corresponding to the first correction patterns.
Optionally, the mask critical dimension load model is:
b1＝b 0 ’+c’*D1；
wherein b1 is a critical dimension deviation between the first dimension and the second dimension; b 0 ' is a graphical intrinsic load; c' is a mask critical dimension loading effect coefficient; d1 is the first pattern density, wherein D1 is:
wherein M (R, θ) is a mask function, i.e., there is a pattern of 1, no pattern of 0, and the radius R1 may be plural.
Optionally, the developing critical dimension load model is:
b2＝b 0 ”+c”*D2；
wherein b2 is a critical dimension deviation between the second dimension and the third dimension; b 0 "is a graphic intrinsic load; c' is the development critical dimension loading effect coefficient; d2 is the followingA second pattern density, wherein D2 is:
wherein M (R, θ) is a mask function, i.e., there is a pattern of 1, no pattern of 0, and the radius R2 may be plural.
Optionally, the etching critical dimension load model is:
b3＝b 0 ”’+c”’*D3；
wherein b3 is a critical dimension offset between the third dimension and the fourth dimension; b 0 "' is the graph intrinsic load; c' "is the etch critical dimension loading effect coefficient; d3 is the third pattern density, wherein D3 is:
wherein M (R, θ) is a mask function, i.e., there is a pattern of 1, no pattern of 0, and the radius R3 may be plural.
Optionally, the method for performing critical dimension compensation on the first corrected layout according to the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model includes: superposing the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model to obtain a deviation compensation value B, namely:
B＝b1+b2+b3＝b 0 ’+c’*D1+b 0 ”+c”*D2+b 0 ”’+c”’*D3；
and carrying out reverse compensation on the first corrected layout according to the deviation compensation value B.
Optionally, the patterned layer is a photoresist layer.
Optionally, the substrate further includes: and the patterning layer is positioned on the mask layer.
Optionally, the device structure includes: a fin.
Optionally, the fin comprises a single layer structure or a multi-layer structure.
Optionally, when the fin portion is of a multilayer structure, the fin portion includes: and a plurality of layers of channel layers and sacrificial layers which are overlapped and arranged along the normal direction of the substrate.
Optionally, the method for obtaining the first corrected layout includes: providing an initial layout; splitting the initial layout to form a plurality of split layouts; and carrying out initial optical proximity correction on the split layout to obtain the first corrected layout.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the critical dimension deviation correction method in optical proximity correction provided by the technical scheme of the invention, the dimension deviation between each adjacent process is obtained in the manufacturing process of the device structure, so that the corresponding mask critical dimension load model, development critical dimension load model and etching critical dimension load model are constructed, and the first correction layout is subjected to optical proximity correction through the mask critical dimension load model, the development critical dimension load model and the etching critical dimension load model, and a second correction layout is obtained. And further, the correction precision and correction efficiency are improved when the semiconductor manufacturing process is performed on the basis of the second correction layout.
Drawings
FIG. 1 is a flow chart of a method for correcting CD bias in optical proximity correction according to an embodiment of the invention;
FIGS. 2 to 8 are schematic structural diagrams illustrating steps of a critical dimension deviation correcting method in optical proximity correction according to an embodiment of the present invention;
Detailed Description
As described in the background, there are still a number of problems with the optical proximity correction of the prior art. The following will specifically explain.
In the manufacturing process of semiconductors, as the integrated level of integrated circuits is higher and higher, the feature size of semiconductor devices therein is smaller and smaller, the requirements on the manufacturing process are correspondingly more and more precise, the number and density of target patterns on a mask layout are rapidly increased, and all the target patterns cannot be exposed to a wafer at one time in the photoetching process. For this reason, MP (Multi-Patterning) technology is becoming a necessary means to make exposure patterns meet the process requirements of each node. MP technology is to split the dense target pattern originally placed on one mask pattern into a plurality of mask patterns, and expose the target pattern to complete the transfer of the target pattern.
However, after the denser target pattern is split into a plurality of mask patterns in the prior art, a larger-area blank area appears on each mask pattern, and the difference between the pattern density of the pattern area and the pattern density of the adjacent blank area is larger. Even if the optical proximity correction is performed on the split mask layout, the larger pattern density difference still has larger influence on the subsequent mask manufacturing, exposure and development and etching transmission, so that the finally obtained actual size of the etched device and the target size of the etched device have larger difference.
In order to solve the technical problems, the technical scheme of the invention provides a critical dimension deviation correction method in optical proximity correction, which is characterized in that dimension deviation among adjacent processes is obtained in the manufacturing process of a device structure, so that a corresponding mask critical dimension load model, development critical dimension load model and etching critical dimension load model are constructed, and further, optical proximity correction is carried out on the first correction layout through the mask critical dimension load model, the development critical dimension load model and the etching critical dimension load model, so as to obtain a second correction layout. And further, the correction precision and correction efficiency are improved when the semiconductor manufacturing process is performed on the basis of the second correction layout.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
FIG. 1 is a flow chart of a method for correcting CD bias in optical proximity correction according to an embodiment of the present invention, taking the simplest mandrel pattern as an example, showing CD bias correction from mask to final pattern for CD load, comprising:
step S101, a first correction layout is obtained, wherein the first correction layout comprises a first area and a second area which are adjacent, the first area is provided with a plurality of first correction patterns, the first correction patterns are of a first size, and the pattern density of the first area is larger than that of the second area;
step S102, forming a mask plate according to the first corrected layout, wherein the mask plate is provided with a plurality of mask patterns corresponding to the first corrected patterns, and the mask patterns are of a second size;
step S103, obtaining a first pattern density, and modeling according to the first pattern density and the critical dimension deviation between the first dimension and the second dimension to obtain a mask critical dimension load model;
step S104, providing a substrate, wherein the substrate comprises a base and a patterned layer positioned on the base;
step S105, performing exposure treatment on the mask plate to enable the patterning layer to form a plurality of patterning structures corresponding to the mask pattern, wherein the patterning structures have a third size;
step S106, obtaining a second pattern density, and modeling according to the second pattern density and the critical dimension deviation between the second dimension and the third dimension to obtain a developing critical dimension load model;
step S107, etching the substrate by taking the patterned structure as a mask, and forming a plurality of device structures corresponding to the patterned structure on the substrate, wherein the device structures have a fourth size;
step S108, obtaining a third pattern density, and modeling according to the third pattern density and the critical dimension deviation between the third dimension and the fourth dimension to obtain an etching critical dimension load model;
step S109, performing critical dimension compensation on the first correction layout according to the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model, and performing optical proximity correction after the critical dimension compensation to obtain a second correction layout, wherein the second correction layout is provided with a plurality of second correction patterns corresponding to the first correction patterns.
The following describes the steps of the critical dimension deviation correction method in the optical proximity correction in detail with reference to the accompanying drawings.
Fig. 2 to 8 are schematic structural diagrams illustrating steps of a cd bias correction method in optical proximity correction according to an embodiment of the invention.
The method comprises the steps of obtaining a first correction layout, wherein the first correction layout comprises a first area and a second area which are adjacent, the first area is provided with a plurality of first correction patterns, the first correction patterns are of a first size, and the pattern density of the first area is larger than that of the second area. The specific process of obtaining the first corrected graph is shown in fig. 2 to 3.
Referring to FIG. 2, an initial layout (not shown) is provided; and splitting the initial layout to form a plurality of split layouts 100.
In this embodiment, since the pattern density on the initial layout is relatively high, all the patterns cannot be exposed to the wafer at one time in the photolithography process. Therefore, the initial layout is split into a plurality of split layouts 100, so that the exposure pattern meets the technological requirements of each node.
Referring to fig. 3, an initial optical proximity correction is performed on the split layout 100 to obtain the first corrected layout 200.
In this embodiment, the initial optical proximity correction is a first optical proximity correction, and the initial optical proximity correction performs a certain transformation on each graph in the split layout 100 based on a correction model, that is, translates fragments of each edge of a plurality of graphs in the split layout 100 by a certain pitch size, so as to obtain a plurality of first correction graphs 201 in the first correction layout 200.
In this embodiment, the first correction pattern 201 has a rectangular shape, and the first dimension includes: the width dimension of the first corrected pattern.
In this embodiment, the second region has no pattern; in other embodiments, the second region may also have a pattern, and the pattern density of the first region is greater than the pattern density of the second region.
Referring to fig. 4, a mask 300 is formed according to the first corrected layout 200, the mask 300 has a plurality of mask patterns 301 corresponding to the first corrected patterns 201, and the mask patterns 301 have a second size.
In this embodiment, the method for forming the mask 300 according to the first corrected layout 200 includes: providing an initial mask (not shown), wherein the initial mask comprises a mask layer and a first photoresist layer positioned on the mask layer; forming a photoresist opening on the first photoresist layer by using an electron beam according to the first correction pattern 201; and etching the mask layer by taking the first photoresist as a mask, and forming a mask pattern 301 corresponding to the first correction pattern 201 in the mask layer.
In this embodiment, the mask pattern 301 is consistent with the first corrected pattern 201, so that the mask pattern 301 is also rectangular, and the second dimension includes: the width dimension of the mask pattern 301.
With continued reference to fig. 3 and 4, a first pattern density is obtained, and modeling is performed according to the first pattern density and a critical dimension deviation between the first dimension and the second dimension, so as to obtain a mask critical dimension load model.
In this embodiment, since the first corrected layout 200 includes the first region I without patterns, the critical position pattern density spans of the second region II and the first region I are large, so that when the mask layer is etched, the difference between the etching environments of the mask layer and the region of the first corrected layout 200, where the critical positions of the first region I and the second region II are opposite, is large, and thus a large deviation exists between the second dimension of a part of the mask pattern 301 and the corresponding first dimension of the first corrected pattern 201. Thus, a mask load model is obtained based on the first dimension and the second dimension.
In this embodiment, the mask critical dimension load model is:
b1＝b 0 ’+c’*D1；
wherein b1 is a critical dimension deviation between the first dimension and the second dimension; b 0 ' is a graphical intrinsic load; c' is a mask critical dimension loading effect coefficient; d1 is the first pattern density, wherein D1 is:
wherein M (R, θ) is a mask function, i.e., there is a pattern of 1, no pattern of 0, and the radius R1 may be plural.
B is the same as 0 ' graphic intrinsic load refers specifically to dimensional deviations exhibited during the processing process, b 0 ' is the intrinsic load of the mask making process, mainly from the etching process. And c' is a mask critical dimension loading effect coefficient, namely the response of the critical dimension deviation to the first pattern density in the mask process.
Referring to fig. 5, a substrate is provided, which includes a base 400 and a patterned layer 402 on the base 400.
In this embodiment, the substrate further includes: a mask layer 401 on the substrate 400, and the patterned layer 402 is on the mask layer 401.
In this embodiment, the patterned layer 402 is a photoresist layer.
Referring to fig. 6, the mask 300 is exposed, so that the patterned layer 402 forms a plurality of patterned structures 403 corresponding to the mask pattern 301, and the patterned structures 403 have a third size.
In this embodiment, the patterned structure 403 has a first projected pattern on the substrate 400. The first projected pattern is consistent with the mask pattern 301, so that the first projected pattern is also rectangular, and the third dimension includes: the width dimension of the first projected pattern.
With continued reference to fig. 4 and 6, a second pattern density is obtained, and modeling is performed according to the second pattern density and a critical dimension deviation between the second dimension and the third dimension, so as to obtain a developed critical dimension load model.
In this embodiment, the developing critical dimension load model is:
b2＝b 0 ”+c”*D2；
wherein b2 is a critical dimension deviation between the second dimension and the third dimension; b 0 "is a graphic intrinsic load; c' is the development critical dimension loading effect coefficient; d2 is the second pattern density, wherein D2 is:
wherein M (R, θ) is a mask function, i.e., there is a pattern of 1, no pattern of 0, and the radius R2 may be plural.
B is the same as 0 "intrinsic load for pattern" refers specifically to dimensional deviations exhibited during the process, b 0 And the' is the intrinsic load of the developing manufacturing process. c' is the loading effect coefficient of the development critical dimension, i.e. the response of the critical dimension deviation to the second pattern density during the development process.
Referring to fig. 7, the patterned structure 403 is used as a mask to etch the substrate 400, and a plurality of device structures 404 corresponding to the patterned structure 403 are formed on the substrate 400, where the device structures 404 have a fourth size.
In this embodiment, the device structure 404 has a second projected pattern on the substrate 400. The second projected pattern is consistent with the first projected pattern, so the second projected pattern is also rectangular, and the fourth dimension includes: and the width dimension of the second projection pattern.
In this embodiment, the device structure 404 is a fin.
In this embodiment, the fin portion has a single-layer structure. In other embodiments, the fin may further be a multi-layer structure, and when the fin is a multi-layer structure, the fin includes: and a plurality of layers of channel layers and sacrificial layers which are overlapped and arranged along the normal direction of the substrate.
With continued reference to fig. 6 and 7, a third pattern density is obtained, and modeling is performed according to the third pattern density and a critical dimension deviation between the third dimension and the fourth dimension, so as to obtain an etching critical dimension load model.
In this embodiment, the etching critical dimension load model is:
b3＝b 0 ”’+c”’*D3；
wherein b3 is a critical dimension offset between the third dimension and the fourth dimension; b 0 "' is the graph intrinsic load; c' "is the etch critical dimension loading effect coefficient; d3 is the third pattern density, wherein D3 is:
wherein M (R, θ) is a mask function, i.e., there is a pattern of 1, no pattern of 0, and the radius R3 may be plural.
B is the same as 0 "' is the intrinsic load of the pattern, which specifically refers to the dimensional deviation, b, exhibited during the process 0 "' is the intrinsic load of the etching process. c' "is the developed cd loading effect factor, i.e., the response of cd bias to the third pattern density during the etch process.
Referring to fig. 8, according to the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model, the first correction layout 200 is subjected to critical dimension compensation, and optical proximity correction is performed after the critical dimension compensation, so as to obtain a second correction layout 500, where the second correction layout 500 has a plurality of second correction patterns 501 corresponding to the first correction patterns 201.
In this embodiment, the method for performing critical dimension compensation on the first corrected layout 200 according to the mask critical dimension load model, the developed critical dimension load model and the etched critical dimension load model includes: superposing the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model to obtain a deviation compensation value B, namely:
B＝b1+b2+b3＝b 0 ’+c’*D1+b 0 ”+c”*D2+b 0 ”’+c”’*D3；
and carrying out reverse compensation on the first corrected layout 200 according to the deviation compensation value B.
In this embodiment, the dimension deviation between each adjacent process is obtained during the fabrication of the device structure 404, so as to construct the corresponding mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model, and then the optical proximity correction is performed on the first corrected layout 200 by using the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model, so as to obtain the second corrected layout 500. Thereby ensuring that the correction accuracy and correction efficiency are improved when the semiconductor manufacturing process is performed based on the second correction layout 500.
After the device structure 404 is obtained, providing a target fourth size corresponding to the fourth size of the device structure 404, and when a difference between the fourth size and the target fourth size is within a preset range, taking the second correction layout 500 as a final correction layout; and when the difference value between the fourth dimension and the target fourth dimension exceeds a preset range, acquiring the difference value between the fourth dimension and the target fourth dimension, and adjusting the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model according to the difference value between the fourth dimension and the target fourth dimension, so as to correspondingly form an mask critical dimension adjustment load model, a developing critical dimension adjustment load model and an etching critical dimension adjustment load model.
Reversely pushing out a target third dimension corresponding to the patterned structure third dimension according to the load model for adjusting the etching critical dimension and the target fourth dimension; reversely pushing out a target second size corresponding to the mask pattern second size according to the exposure load adjusting model and the target third size; and reversely pushing out a target first size corresponding to the first corrected pattern first size according to the mask load adjusting model and the target second size.
And performing optical proximity correction on the second correction layout 500 according to the mask critical dimension load model adjustment, the developing critical dimension load model adjustment and the etching critical dimension load model adjustment, so as to obtain a third correction layout (not shown). And carrying out semiconductor manufacturing processes on the basis of the third correction layout, and measuring the sizes of corresponding patterns in each manufacturing process. When the difference value between the size of the graph in each process and the corresponding target first size, target second size, target third size and target fourth size is in a preset range, taking the third correction layout as a final correction layout; when the difference between the size of the pattern in each process and the corresponding target first size, target second size, target third size and target fourth size exceeds a preset range, the repeated iterative updating in the above process is needed until the difference between the size of the pattern in each process and the corresponding target first size, target second size, target third size and target fourth size is within the preset range, and then the final corrected layout is obtained.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (11)
1. A method for correcting critical dimension bias in optical proximity correction, comprising:
acquiring a first correction layout, wherein the first correction layout comprises a first area and a second area which are adjacent, the first area is provided with a plurality of first correction patterns, the first correction patterns are of a first size, and the pattern density of the first area is larger than that of the second area;
forming a mask plate according to the first correction layout, wherein the mask plate is provided with a plurality of mask patterns corresponding to the first correction patterns, and the mask patterns are of a second size;
acquiring a first pattern density, modeling according to the first pattern density and the critical dimension deviation between the first dimension and the second dimension, and acquiring a mask critical dimension load model;
providing a substrate, wherein the substrate comprises a base and a patterning layer positioned on the base;
exposing the mask plate to form a plurality of patterned structures corresponding to the mask patterns on the patterned layer, wherein the patterned structures have a third size;
acquiring a second pattern density, modeling according to the second pattern density and the critical dimension deviation between the second dimension and the third dimension, and acquiring a developing critical dimension load model;
etching the substrate by taking the patterned structure as a mask, and forming a plurality of device structures corresponding to the patterned structure on the substrate, wherein the device structures have a fourth size;
obtaining a third pattern density, modeling according to the third pattern density and the critical dimension deviation between the third dimension and the fourth dimension, and obtaining an etching critical dimension load model;
and compensating the critical dimension of the first correction layout according to the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model, and carrying out optical proximity correction after the compensation of the critical dimension to obtain a second correction layout, wherein the second correction layout is provided with a plurality of second correction patterns corresponding to the first correction patterns.
2. The method for correcting cd bias in optical proximity correction according to claim 1, wherein the mask cd load model is:
b1＝b 0 ’+c’*D1；
wherein b1 is a critical dimension deviation between the first dimension and the second dimension; b 0 ' is a graphical intrinsic load; c' is a mask critical dimension loading effect coefficient; d1 is the first pattern density, wherein D1 is:
wherein M (R, θ) is a mask function, i.e., there is a pattern of 1, no pattern of 0, and the radius R1 may be plural.
3. The method for CD bias correction in optical proximity correction as claimed in claim 2, wherein said developed CD load model is:
b2＝b 0 ”+c”*D2；
wherein b2 is a critical dimension deviation between the second dimension and the third dimension; b 0 "is a graphic intrinsic load; c' is the development critical dimension loading effect coefficient; d2 is the second pattern density, wherein D2 is:
wherein M (R, θ) is a mask function, i.e., there is a pattern of 1, no pattern of 0, and the radius R2 may be plural.
4. The method for CD bias correction in optical proximity correction as claimed in claim 3, wherein said etching CD load model is:
b3＝b 0 ”’+c”’*D3；
wherein b3 is a critical dimension offset between the third dimension and the fourth dimension; b 0 "' is the graph intrinsic load; c' "is the etch critical dimension loading effect coefficient; d3 is the third pattern density, wherein D3 is:
wherein M (R, θ) is a mask function, i.e., there is a pattern of 1, no pattern of 0, and the radius R3 may be plural.
5. The method for critical dimension bias correction in optical proximity correction as claimed in claim 4, wherein the method for critical dimension compensation of the first corrected layout according to the mask critical dimension load model, developed critical dimension load model and etched critical dimension load model comprises: superposing the mask critical dimension load model, the developing critical dimension load model and the etching critical dimension load model to obtain a deviation compensation value B, namely:
B＝b1+b2+b3＝b 0 ’+c’*D1+b 0 ”+c”*D2+b 0 ”’+c”’*D3；
and carrying out reverse compensation on the first corrected layout according to the deviation compensation value B.
6. The method of claim 1, wherein the patterned layer is a photoresist layer.
7. The method for critical dimension bias correction in optical proximity correction as claimed in claim 1, wherein said substrate further comprises: and the patterning layer is positioned on the mask layer.
8. The method for critical dimension bias correction in optical proximity correction as claimed in claim 1, wherein said device structure comprises: a fin.
9. The method of claim 8, wherein the fin comprises a single layer structure or a multi-layer structure.
10. The method of claim 9, wherein when the fin is a multilayer structure, the fin comprises: and a plurality of layers of channel layers and sacrificial layers which are overlapped and arranged along the normal direction of the substrate.
11. The method for correcting critical dimension deviation in optical proximity correction according to claim 1, wherein the method for obtaining the first corrected layout comprises: providing an initial layout; splitting the initial layout to form a plurality of split layouts; and carrying out initial optical proximity correction on the split layout to obtain the first corrected layout.
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