JPS63211739A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63211739A JPS63211739A JP4570987A JP4570987A JPS63211739A JP S63211739 A JPS63211739 A JP S63211739A JP 4570987 A JP4570987 A JP 4570987A JP 4570987 A JP4570987 A JP 4570987A JP S63211739 A JPS63211739 A JP S63211739A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- patterns
- semiconductor device
- etching
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 9
- 235000008429 bread Nutrition 0.000 claims 1
- 238000003486 chemical etching Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にエツチングの均一化を
計った半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which etching is made uniform.
従来この種の半導体装置においては、エツチングに関す
るパターンは不用なパターンは形成せず半導体基板上に
装置を構成する上で不可欠のパターン、例えば配線パタ
ーンのみを形成した。Conventionally, in this type of semiconductor device, unnecessary etching patterns were not formed, and only patterns essential for constructing the device, such as wiring patterns, were formed on the semiconductor substrate.
かかる従来の半導体装置は、チップ内で構成される装置
によりそのパターンの密度分布が全くばらばらになって
いるため、各種のエツチング工程において形成されるパ
ターンの均一性が阻害されるという欠点があった。Such conventional semiconductor devices had the disadvantage that the density distribution of the pattern was completely inconsistent depending on the device configured within the chip, which hindered the uniformity of the pattern formed in various etching processes. .
本発明の目的は半導体基板をエツチングする除肉−にエ
ツチングすることのできる半導体装置を提供することに
ある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can be etched by etching a semiconductor substrate.
本発明の半導体基板は実際に使用するパターンとは別の
ダミーパターンを形成しており半導体チップ内において
均一なパターン密度分布をなすように構成される。The semiconductor substrate of the present invention has a dummy pattern formed thereon that is different from the pattern actually used, and is configured to have a uniform pattern density distribution within the semiconductor chip.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第一の実施例を説明するための半導体
装置における基板上パターンの概略平面図である。FIG. 1 is a schematic plan view of a pattern on a substrate in a semiconductor device for explaining a first embodiment of the present invention.
第１図に示すように、かかる半導体装置は半導体基板（
図基省略）上に構成上不可欠なパターン、例えば配線パ
ターン１１とこの配線パターン１１間もしくはこれら配
線パターン１１以外の所に形成されるダミーパターン１
２とを有する。As shown in FIG. 1, such a semiconductor device has a semiconductor substrate (
(Illustration omitted) A pattern that is essential for the configuration, for example, a wiring pattern 11 and a dummy pattern 1 formed between this wiring pattern 11 or in a place other than these wiring patterns 11
2.
かかるダミーパターン１２を形成することにより、かか
る半導体基板をホトエツチングあるいはケミカルエツチ
ングなど種々の作業を行う際に基板上の高さがいずれの
個所においてもほぼ同一となるためエツチングの均一化
を図ることが可能になる。By forming such a dummy pattern 12, when performing various operations such as photoetching or chemical etching on such a semiconductor substrate, the height on the substrate is almost the same at any location, so that uniform etching can be achieved. It becomes possible.
第２図は本発明の第二の実施例を示すパターンの概略図
である。FIG. 2 is a schematic diagram of a pattern showing a second embodiment of the invention.
第２図に示すように、前記第一の実施例に比べ、配線パ
ターン２１は同様であるが、ダミーパターン２２をより
細かに分割することにより半導体チップ内の密度分布を
さらに均一化したものである。また、ダミーパターン２
２を形成することによってゴミなどによるパターンショ
ートの問題が発生するのを抑制している。As shown in FIG. 2, the wiring pattern 21 is the same as that of the first embodiment, but the dummy pattern 22 is divided into smaller parts to make the density distribution within the semiconductor chip more uniform. be. Also, dummy pattern 2
2 suppresses the problem of pattern shorts caused by dust and the like.
〔発明の効果〕
以上説明したように、本発明は半導体装置を構成する上
で不可欠なパターンとは別にダミーのパターンを形成す
ることにより、半導体チップ内のパターン密度を均一化
し、各種のエツチング精度を向上させることができる効
果がある。[Effects of the Invention] As explained above, the present invention uniformizes the pattern density within a semiconductor chip by forming a dummy pattern separately from the essential patterns for configuring a semiconductor device, and improves various etching precisions. It has the effect of improving the
第１図は本発明の第一の実施例を説明するための半導体
装置における基板上パターンの概略平面図、第２図は本
発明の第二の実施例を説明するための同様のパターンの
概略平面図である。
１１．２１・・・配線パターン、１２．２２・・・ダミ
ーパターン。FIG. 1 is a schematic plan view of a pattern on a substrate in a semiconductor device for explaining a first embodiment of the present invention, and FIG. 2 is a schematic plan view of a similar pattern for explaining a second embodiment of the present invention. FIG. 11.21...Wiring pattern, 12.22...Dummy pattern.
Claims (1)
ーンと前記実際に使用されるパターン間もしくはこれら
のパン以外の所に形成されるダミーパターンとを設け、
エッチングの均一化を計るようにしたことを特徴とする
半導体装置。A pattern actually used such as a wiring pattern and a dummy pattern formed between the actually used patterns or in a place other than these breads are provided on a semiconductor substrate,
A semiconductor device characterized by ensuring uniform etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4570987A JPS63211739A (en) | 1987-02-27 | 1987-02-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4570987A JPS63211739A (en) | 1987-02-27 | 1987-02-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63211739A true JPS63211739A (en) | 1988-09-02 |
Family
ID=12726879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4570987A Pending JPS63211739A (en) | 1987-02-27 | 1987-02-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63211739A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0241442U (en) * | 1988-09-12 | 1990-03-22 | ||
| EP0443811A2 (en) * | 1990-02-19 | 1991-08-28 | Nec Corporation | Semiconductor memory device |
| US5652465A (en) * | 1994-12-26 | 1997-07-29 | Fujitsu Limited | Semiconductor device having dummy patterns and an upper insulating layer having cavities |
| US5998814A (en) * | 1997-03-27 | 1999-12-07 | Yamaha Corporation | Semiconductor device and fabrication method thereof |
| US6099992A (en) * | 1994-12-12 | 2000-08-08 | Fujitsu Limited | Method for designing reticle, reticle, and method for manufacturing semiconductor device |
| US6197452B1 (en) | 1997-09-17 | 2001-03-06 | Nec Corporation | Light exposure pattern mask with dummy patterns and production method of the same |
| US6396146B2 (en) * | 1997-11-20 | 2002-05-28 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
| US6600180B1 (en) * | 2000-01-19 | 2003-07-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, method of manufacturing the same and exposure mask for implantation |
| JP2008270276A (en) * | 2007-04-16 | 2008-11-06 | Nec Electronics Corp | Dummy pattern arranging device, dummy pattern arranging method, and semiconductor device |
| WO2014125994A1 (en) * | 2013-02-18 | 2014-08-21 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and method for designing same |
-
1987
- 1987-02-27 JP JP4570987A patent/JPS63211739A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0241442U (en) * | 1988-09-12 | 1990-03-22 | ||
| EP0443811A2 (en) * | 1990-02-19 | 1991-08-28 | Nec Corporation | Semiconductor memory device |
| US6553274B1 (en) | 1994-12-12 | 2003-04-22 | Fujitsu Limited | Method for designing reticle, reticle, and method for manufacturing semiconductor device |
| US6099992A (en) * | 1994-12-12 | 2000-08-08 | Fujitsu Limited | Method for designing reticle, reticle, and method for manufacturing semiconductor device |
| US5946557A (en) * | 1994-12-26 | 1999-08-31 | Fujitsu Ltd. | Method of manufacturing a semiconductor device having dummy patterns and an upper insulating layer having cavities |
| US5652465A (en) * | 1994-12-26 | 1997-07-29 | Fujitsu Limited | Semiconductor device having dummy patterns and an upper insulating layer having cavities |
| US5998814A (en) * | 1997-03-27 | 1999-12-07 | Yamaha Corporation | Semiconductor device and fabrication method thereof |
| US6080652A (en) * | 1997-03-27 | 2000-06-27 | Yamaha Corporation | Method of fabricating a semiconductor device having a multi-layered wiring |
| US6197452B1 (en) | 1997-09-17 | 2001-03-06 | Nec Corporation | Light exposure pattern mask with dummy patterns and production method of the same |
| US6396146B2 (en) * | 1997-11-20 | 2002-05-28 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
| US6600180B1 (en) * | 2000-01-19 | 2003-07-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, method of manufacturing the same and exposure mask for implantation |
| JP2008270276A (en) * | 2007-04-16 | 2008-11-06 | Nec Electronics Corp | Dummy pattern arranging device, dummy pattern arranging method, and semiconductor device |
| WO2014125994A1 (en) * | 2013-02-18 | 2014-08-21 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and method for designing same |
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