JPH05326707A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate a wiring region, which becomes necessary on the same plane when a wiring is provided between functional macroblocks after second aluminum layer is used on the whole surface of the functional blocks and input/ output signal terminals are positioned on each side of the functional blocks, and to make a chip small in size. CONSTITUTION:In functional macroblocks 1 and 2 on which a wire is distributed on a first aluminum layer, a polycrystalline silicon layer and a second aluminum layer, the input/output signal terminals between each of functional macroblocks are connected to the second aluminum layer, and the input/output signal terminals are positioned by unifying the order of the input/output signal terminals to the functional macroblocks. As a result, the wiring between the functional macroblocks is formed on the second aluminum layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to its layout structure.

[0002]

2. Description of the Related Art Conventionally, as a layout method of an integrated circuit device, as shown in FIG.
2nd aluminum is used on the entire surface, and the input / output signal terminals 3, 4, 5, 6 are provided on each side of the functional macro blocks 1 and 2.
Since 7 and 8 were positioned, functional macro block 1,
The wiring area 9 was required when wiring between two.

That is, when the same input / output signal terminal names are set to have the same potential, the input / output signal terminal A3 of the functional macro block 1 and the input / output signal terminal A8 of the functional macro block 2 are connected to each other, so that the functional macro blocks 1 and 2 are connected. The wiring region 9 was formed between the two. Other input / output signal terminals 4,
The same applies to 5, 7, and 8.

[0004]

In this conventional layout method for an integrated circuit device, the second aluminum is used on the entire surfaces of the functional macro blocks 1 and 2, and the input / output signal terminals 3 to 8 are provided on each side of the functional macro block. Therefore, when wiring between the functional macroblocks 1 and 2, the wiring area 9 is required on the same plane, which makes it difficult to reduce the chip size.

The object of the present invention is to eliminate these drawbacks.
An object of the present invention is to provide an integrated circuit device capable of reducing the chip size.

[0006]

The structure of the present invention is an integrated circuit device having a functional macroblock wired by a first aluminum layer, a polycrystalline silicon layer, and a second aluminum layer. The input / output signal terminals of each other are connected by the second aluminum layer, and the order of the input / output signal terminals is unified and positioned in the functional macroblocks in the X direction or the Y direction. Is characterized by.

[0007]

1 is a plan view illustrating an embodiment of the present invention. In this embodiment, the input / output signal terminals 3, 4, 5, 6, 7, 8 of the functional macro blocks 1 and 2 are set in the Y direction, and the input / output signal terminals 3 and 6 are set to the same X coordinate input / output signal 4. The second aluminum is wired on the functional macro block by setting 7 as the same X coordinate and input / output signal terminals 5 and 8 as the same X coordinate.

In this embodiment, the function macro blocks 1 and 2 are
Since the second aluminum can be wired on top, the conventional wiring region 9 can be eliminated.

[0009]

As described above, according to the present invention, the wiring area can be eliminated and the chip size can be reduced by locating the coordinates of the input / output signal terminals of the functional macro block in the X direction or the Y direction. Has the effect.

[Brief description of drawings]

FIG. 1 is a plan view of a mask layout according to an embodiment of the present invention.

FIG. 2 is a plan view of an example of a conventional mask layout.

[Explanation of symbols]

 1,2 Functional macro block 3,8 I / O signal terminal A 4,7 I / O signal terminal B 5,6 I / O signal terminal C 9 Wiring area

Claims (1)

[Claims] 1. A first aluminum layer, a polycrystalline silicon layer,
In an integrated circuit device having a functional macroblock wired with a second aluminum layer, the input / output signal terminals of the functional macroblocks are interconnected by the second aluminum layer and the order of the input / output signal terminals is changed. An integrated circuit device characterized in that the functional macroblocks are integrally positioned and laid out in the X direction or the Y direction.