JPS6085843U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6085843U
JPS6085843U JP17982783U JP17982783U JPS6085843U JP S6085843 U JPS6085843 U JP S6085843U JP 17982783 U JP17982783 U JP 17982783U JP 17982783 U JP17982783 U JP 17982783U JP S6085843 U JPS6085843 U JP S6085843U
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor equipment
layer
polycrystalline silicon
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17982783U
Other languages
Japanese (ja)
Inventor
幸次 田中
Original Assignee
日産自動車株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日産自動車株式会社 filed Critical 日産自動車株式会社
Priority to JP17982783U priority Critical patent/JPS6085843U/en
Publication of JPS6085843U publication Critical patent/JPS6085843U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Character Discrimination (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の部分拡大平面図、第２図は
この考案の一実施例による半導体装−の部分拡大平面図
、第３図は第２図の半導体装置の断面図、第４図はこの
考案の他の実施例による半導体装置の部分拡大平面図で
ある。 ２・・・電極パッド、３・・・入出力素子領域、４・・
・半導体基板、５・・・金属配線、６・・・主回路素子
領域、７・・・文字パターン、８・・・ＬＯＧＯ３によ
る酸化膜、９・・・相関絶縁膜、１０・・・表面保護膜
、１１・・・マスク合せマーク、２１・・・金属層、７
１・・・多結晶シリコン層。1 is a partially enlarged plan view of a conventional semiconductor device, FIG. 2 is a partially enlarged plan view of a semiconductor device according to an embodiment of the present invention, FIG. 3 is a sectional view of the semiconductor device of FIG. 2, and FIG. The figure is a partially enlarged plan view of a semiconductor device according to another embodiment of the invention. 2... Electrode pad, 3... Input/output element area, 4...
・Semiconductor substrate, 5...Metal wiring, 6...Main circuit element area, 7...Character pattern, 8...Oxide film by LOGO3, 9...Correlative insulating film, 10...Surface protection Film, 11... Mask alignment mark, 21... Metal layer, 7
1... Polycrystalline silicon layer.

Claims (1)

【実用新案登録請求の範囲】 半導体基板上に、多結晶シリコン層および金属層ででき
た゛配線部と、これに連なる電極パッド部とを有する半
導体装置において； 上記電極パッドの下部に文字またはマークのパターン層
を形成したことを特徴とする半導体装置。[Claims for Utility Model Registration] In a semiconductor device having, on a semiconductor substrate, a wiring section made of a polycrystalline silicon layer and a metal layer, and an electrode pad section connected thereto; A semiconductor device characterized by forming a pattern layer.
JP17982783U 1983-11-21 1983-11-21 semiconductor equipment Pending JPS6085843U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17982783U JPS6085843U (en) 1983-11-21 1983-11-21 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17982783U JPS6085843U (en) 1983-11-21 1983-11-21 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS6085843U true JPS6085843U (en) 1985-06-13

Family

ID=30390066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17982783U Pending JPS6085843U (en) 1983-11-21 1983-11-21 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6085843U (en)

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