JPH0223954B2 - - Google Patents

Info

Publication number
JPH0223954B2
JPH0223954B2 JP57033783A JP3378382A JPH0223954B2 JP H0223954 B2 JPH0223954 B2 JP H0223954B2 JP 57033783 A JP57033783 A JP 57033783A JP 3378382 A JP3378382 A JP 3378382A JP H0223954 B2 JPH0223954 B2 JP H0223954B2
Authority
JP
Japan
Prior art keywords
output
flop
flip
data
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57033783A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58153289A (ja
Inventor
Hiroshi Toguchi
Kuniaki Murakoshi
Takao Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Fujitsu Telecom Networks Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Fujitsu Telecom Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Fujitsu Telecom Networks Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57033783A priority Critical patent/JPS58153289A/ja
Publication of JPS58153289A publication Critical patent/JPS58153289A/ja
Publication of JPH0223954B2 publication Critical patent/JPH0223954B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)
JP57033783A 1982-03-05 1982-03-05 フア−ストイン・フア−ストアウト・メモリ回路 Granted JPS58153289A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57033783A JPS58153289A (ja) 1982-03-05 1982-03-05 フア−ストイン・フア−ストアウト・メモリ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57033783A JPS58153289A (ja) 1982-03-05 1982-03-05 フア−ストイン・フア−ストアウト・メモリ回路

Publications (2)

Publication Number Publication Date
JPS58153289A JPS58153289A (ja) 1983-09-12
JPH0223954B2 true JPH0223954B2 (sv) 1990-05-25

Family

ID=12396057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57033783A Granted JPS58153289A (ja) 1982-03-05 1982-03-05 フア−ストイン・フア−ストアウト・メモリ回路

Country Status (1)

Country Link
JP (1) JPS58153289A (sv)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2501204B2 (ja) * 1986-10-22 1996-05-29 日本電気株式会社 半導体メモリ
JPS63155498A (ja) * 1986-12-19 1988-06-28 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
JPS58153289A (ja) 1983-09-12

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