JPH0223732U - - Google Patents
Info
- Publication number
- JPH0223732U JPH0223732U JP10106488U JP10106488U JPH0223732U JP H0223732 U JPH0223732 U JP H0223732U JP 10106488 U JP10106488 U JP 10106488U JP 10106488 U JP10106488 U JP 10106488U JP H0223732 U JPH0223732 U JP H0223732U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- bus
- transmitted
- driver
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Description
第１図は本考案の一実施例の構成概念図、第２
図はその動作を説明するための動作波形図、第３
図は従来のバス・インターフエイス回路の構成を
示す説明図、第４図はその動作を説明するための
波形図である。
Ｄ１……ドライバー回路、ＢＢ……バツクボー
ド、１１〜１ｎ……第１ドライバー回路群、２１
〜２ｎ……第２ドライバー回路群、ＲＬ１〜ＲＬ
ｎ……負荷抵抗、３……逆相信号印加回路。
Figure 1 is a conceptual diagram of the configuration of one embodiment of the present invention;
The figure is an operation waveform diagram to explain the operation.
FIG. 4 is an explanatory diagram showing the configuration of a conventional bus interface circuit, and FIG. 4 is a waveform diagram for explaining its operation. D1...driver circuit, BB...back board, 11-1n...first driver circuit group, 21
~2n...Second driver circuit group, RL1~RL
n...Load resistance, 3...Negative phase signal application circuit.
Claims (1)
号をバスにそれぞれ出力する複数個の第１ドライ
バー回路群と、 出力端に負荷抵抗が接続された複数個の第２の
ドライバー回路群と、 前記伝送すべき信号と同期し、かつ当該信号と
逆相の信号を前記複数個の第２のドライバー回路
群の入力端に印加する逆相信号印加回路とを備え
たバス・インターフエイス回路。[Claim for Utility Model Registration] A plurality of first driver circuits connected to a bus in the backboard and outputting signals to be transmitted to the bus, and a plurality of second driver circuits each having a load resistor connected to the output terminal. A bus comprising a driver circuit group, and an anti-phase signal applying circuit that is synchronized with the signal to be transmitted and applies a signal having an opposite phase to the signal to the input terminals of the plurality of second driver circuit groups. interface circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10106488U JPH0223732U (en) | 1988-07-29 | 1988-07-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10106488U JPH0223732U (en) | 1988-07-29 | 1988-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223732U true JPH0223732U (en) | 1990-02-16 |
Family
ID=31329715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10106488U Pending JPH0223732U (en) | 1988-07-29 | 1988-07-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223732U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6330037A (en) * | 1986-07-23 | 1988-02-08 | Matsushita Electric Ind Co Ltd | Signal transmission equipment |
-
1988
- 1988-07-29 JP JP10106488U patent/JPH0223732U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6330037A (en) * | 1986-07-23 | 1988-02-08 | Matsushita Electric Ind Co Ltd | Signal transmission equipment |
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