JPH0429228U - - Google Patents

Info

Publication number
JPH0429228U
JPH0429228U JP7087890U JP7087890U JPH0429228U JP H0429228 U JPH0429228 U JP H0429228U JP 7087890 U JP7087890 U JP 7087890U JP 7087890 U JP7087890 U JP 7087890U JP H0429228 U JPH0429228 U JP H0429228U
Authority
JP
Japan
Prior art keywords
terminal
delay line
resistors
signal input
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7087890U
Other languages
Japanese (ja)
Other versions
JP2503666Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7087890U priority Critical patent/JP2503666Y2/en
Publication of JPH0429228U publication Critical patent/JPH0429228U/ja
Application granted granted Critical
Publication of JP2503666Y2 publication Critical patent/JP2503666Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Landscapes

  • Filters And Equalizers (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例の回路図、第2図aお
よび第3図aは本考案の実施例の適用例を示す回
路図、第2図b,cおよび第3図b,cはそれぞ
れ第2図aおよび第3図aにかかる信号波形図で
ある。1,2……遅延線、3,4……抵抗器、5
……信号入力端子、6……信号出力端子、7,8
……終端用端子、9……アース端子、10……複
合部品。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIGS. 2a and 3a are circuit diagrams showing an application example of the embodiment of the present invention, and FIGS. 2b, c and 3b, c are FIG. 3 is a signal waveform diagram according to FIG. 2a and FIG. 3a, respectively; 1, 2...Delay line, 3, 4...Resistor, 5
...Signal input terminal, 6...Signal output terminal, 7, 8
... Termination terminal, 9 ... Earth terminal, 10 ... Composite part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同一の基板上にパターニング形成した第1およ
び第2の遅延線と、信号入力端子および信号出力
端子の間に直列接続した2つの抵抗器と、一端を
前記信号入力端子に接続した前記第1の遅延線の
他端を接続した第1の終端用端子と、一端を2つ
の前記抵抗器の相互接続箇所に接続した前記第2
の遅延線の他端を接続した第2の終端用端子とを
備えていることを特徴とする遅延線を含む複合部
品。
first and second delay lines patterned on the same substrate, two resistors connected in series between a signal input terminal and a signal output terminal, and the first delay line whose one end is connected to the signal input terminal. a first terminating terminal to which the other end of the delay line is connected; and the second terminal to which one end is connected to the interconnection point of the two resistors.
and a second termination terminal connected to the other end of the delay line.
JP7087890U 1990-07-03 1990-07-03 Composite part including delay line Expired - Lifetime JP2503666Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7087890U JP2503666Y2 (en) 1990-07-03 1990-07-03 Composite part including delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7087890U JP2503666Y2 (en) 1990-07-03 1990-07-03 Composite part including delay line

Publications (2)

Publication Number Publication Date
JPH0429228U true JPH0429228U (en) 1992-03-09
JP2503666Y2 JP2503666Y2 (en) 1996-07-03

Family

ID=31607418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7087890U Expired - Lifetime JP2503666Y2 (en) 1990-07-03 1990-07-03 Composite part including delay line

Country Status (1)

Country Link
JP (1) JP2503666Y2 (en)

Also Published As

Publication number Publication date
JP2503666Y2 (en) 1996-07-03

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