JPS6381425U - - Google Patents
Info
- Publication number
- JPS6381425U JPS6381425U JP17400186U JP17400186U JPS6381425U JP S6381425 U JPS6381425 U JP S6381425U JP 17400186 U JP17400186 U JP 17400186U JP 17400186 U JP17400186 U JP 17400186U JP S6381425 U JPS6381425 U JP S6381425U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- resistor
- series
- operational amplifier
- inverting input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Networks Using Active Elements (AREA)
- Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
Description
第１図は本考案の一実施例の回路図、第２図お
よび第３図は夫々従来の異なる例の回路図、第４
図及び第５図は夫々プリエンフアシス回路の基本
回路図の一例である。
１……入力端子、２……出力端子、１０……演
算増幅器、１２〜１７……端子、Ｒ１〜Ｒ７……
抵抗、Ｃ，Ｃ１〜Ｃ３……コンデンサ。
Figure 1 is a circuit diagram of one embodiment of the present invention, Figures 2 and 3 are circuit diagrams of different conventional examples, respectively, and Figure 4 is a circuit diagram of an embodiment of the present invention.
5 and 5 are examples of basic circuit diagrams of the pre-emphasis circuit. 1...Input terminal, 2...Output terminal, 10...Operation amplifier, 12-17...Terminal, R1 -R7 ...
Resistance, C, C1 to C3 ... Capacitor.
Claims (1)
入力端子と信号入力端子との間に直列接続した抵
抗及びコンデンサと、前記信号入力端子と演算増
幅器の出力端子との間に並列接続したｎ個の抵抗
列と、このｎ個の抵抗列の夫々の中間接続点に設
けたｎ個の端子と、前記演算増幅器の反転入力端
子或いは前記抵抗とコンデンサの接続点に設けた
ｎ個の端子とを備え、これら各ｎ個の端子を選択
的に相互接続可能に構成したことを特徴とするプ
リエンフアシス回路。 an operational amplifier having an inverting input terminal; a resistor and a capacitor connected in series between the inverting input terminal and a signal input terminal; and n resistors connected in parallel between the signal input terminal and the output terminal of the operational amplifier. a series of resistors, n terminals provided at intermediate connection points of each of the n resistor series, and n terminals provided at an inverting input terminal of the operational amplifier or a connection point between the resistor and the capacitor; A pre-emphasis circuit characterized in that each of these n terminals is configured to be selectively interconnectable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17400186U JPH0352045Y2 (en) | 1986-11-14 | 1986-11-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17400186U JPH0352045Y2 (en) | 1986-11-14 | 1986-11-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6381425U true JPS6381425U (en) | 1988-05-28 |
| JPH0352045Y2 JPH0352045Y2 (en) | 1991-11-11 |
Family
ID=31111991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17400186U Expired JPH0352045Y2 (en) | 1986-11-14 | 1986-11-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0352045Y2 (en) |
-
1986
- 1986-11-14 JP JP17400186U patent/JPH0352045Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0352045Y2 (en) | 1991-11-11 |
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