JPH02234434A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a bipolar transistor with small base resistance by forming a short base lead-out electrode using a metal. CONSTITUTION:Three layers, namely first to third insulation layers 41-43, which are formed on a semiconductor substrate 1. Sides of three layers, namely, a collector layer 6, a base layer 7, and an emitter layer 8 are in contact with sides of the first to third insulation layer 41-43, and the side surface of the base layer 7 contacts all of the side surface of the insulation layer 42, one part of the side surface of the first insulation layer 41, and one part of the side surface of the third insulation layer 43. Then, a first hole 5 which is adjacent to the base layer 7 to the second insulation layer 42 are selectively etched, thus forming a hole leading from the side surface of the base layer 7 to the upper part of the third insulation layer 43. Then, it is embedded by a metal layer 11 to form a base lead-out electrode. Also, the collector layer 6, the base layer 7, and the emitter layer 8 are formed being closer to an element isolating region 2. Then, by forming the first hole 5 in the element isolating region 2, the length of the base lead-out electrode 13 is reduced, thus reducing base resistance.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing semiconductor devices, and in particular to a method for manufacturing high-bolar transistors, and aims to provide a method for reducing base resistance and increasing speed. A first layer is formed on a semiconductor substrate having an element isolation region and a buried layer.
a step of laminating an insulating layer, a second insulating layer, and a third insulating layer in this order; and a step of laminating an insulating layer, a second insulating layer, and a third insulating layer in this order; After forming a first hole, a collector layer, a base layer, and an emitter layer are formed in this order in the first hole by selective epitaxial growth, and the thickness of the collector layer is made smaller than the thickness of the first insulating layer. a step of forming the sum of the thickness of the collector layer and the thickness of the base layer to be larger than the sum of the thickness of the first insulating layer and the thickness of the second insulating layer; The third
forming a second opening in the insulating layer reaching at least the first insulating layer; removing the second insulating layer from the second opening by selective etching; A method for manufacturing a semiconductor device comprising: exposing a side surface of the base layer to the opening, and then depositing a metal layer in the second opening to form a base electrode connected to the side surface of the base layer. do.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a bibolar transistor.

Bibolar transistors are required to be faster. Therefore, it is necessary to reduce the base resistance.

[Conventional technology]

Conventionally, in order to increase the speed of bipolar transistors, device structures have been proposed in which the extension length of the base electrode is shortened.

For example, SST (Super
Self-align+ent Technolo
gy) structure and. S I CO S (Side w
All Contact Structures) structure, but all of them are designed to shorten the length of the base electrode, but polysilicon is used for the electrode lead-out. The resistance as low as when using metal cannot be achieved. Another disadvantage is that the manufacturing process is complicated.

[Problems to be Solved by the Invention] Therefore, it has been difficult to reduce the base resistance, resulting in the problem that high speed cannot be achieved.

The present invention uses metal to lead out the base electrode. Moreover, it is an object of the present invention to provide a method for manufacturing a bibolar transistor with a simple manufacturing process.

[Means to solve the problem]

FIGS. 1(a) to 1(h) show the manufacturing process of an embodiment of the present invention, and means for solving the above problem will be explained with reference to the reference numerals in the figures.

The above problem is solved by forming a first insulating layer 41, a second insulating layer 42 .
A step of stacking a third insulating layer 43 in this order, and a step of stacking the third insulating layer 43 on the buried layer 3 close to the element isolation region 2.
After forming a first opening 5 that opens in 3 and reaches the buried layer 3. A collector layer 6, a base layer 7, and an emitter layer 8 are formed in this order in the first opening 5 by selective epitaxial growth, and the thickness of the collector layer 6 is set to be equal to that of the first insulating layer f4.
1, and the sum of the thickness of the collector layer 6 and the thickness of the base layer 7 is larger than the sum of the thickness of the first insulating layer 41 and the thickness of the second insulating layer 42. forming a second opening 9 in the third insulating layer 43 on the element isolation region 2 and reaching at least the first insulating layer 41; After removing the second insulating layer 42 by selective etching and exposing the side surface of the base layer 7 in the second opening 9. The problem is solved by a semiconductor device manufacturing method including a step of depositing a metal layer 11 in the second opening 9 and forming a base electrode 13 connected to the side surface of the base layer 7.

[Effect]

In the present invention. Three layers consisting of a first insulating layer 41, a second insulating layer 42, and a third insulating layer 43 formed on a semiconductor substrate 1, and a collector layer 6, a base layer 7, and an emitter layer formed by selective epitaxial method. The three layers of the layer 8 are in contact with each other on their side surfaces, and the side surface of the base layer 7 is in contact with the second insulating layer 42.
, a portion of the side surface of the first insulating layer 41 , and a portion of the side surface of the third insulating layer 43 .

Therefore, by selectively etching the second insulating layer 42 from the first opening 5 close to the base layer 7, an opening leading from the side surface of the base layer 7 to the top of the third green-free layer 43 is formed. Done. A base extraction electrode can be formed by burying the metal layer 11 there.

Moreover. The collector layer 6, base layer 7, and emitter layer 8 are formed close to the element isolation region 2. Since the first opening 5 is formed in the element isolation region 2, the length of the base lead-out electrode can be reduced.

In this way, since a short base lead-out electrode can be formed using metal, the Heas resistance can be reduced.

〔Example〕

FIGS. 1(a) to 1(h) are diagrams for explaining the manufacturing process of an embodiment of the present invention. 1 is a semiconductor substrate, 2 is an element isolation region, 3 is an active region, 41 to 43 are first to third insulating layers, 5 is a first opening, 6 is a collector layer, 7 is a base layer, and 8 is an emitter. 9 is the second opening, 10 is the third opening, and 11 is the metal layer. 12 represents a collector electrode, 13 represents a base electrode, and 14 represents an emitter electrode.

The present invention will be described below with reference to FIGS. 1(a) to 1(h).

See Figure 1(a) Figure 1(a) is. A state in which an SiOz element isolation region 2 and an n-type buried layer 3 are formed on a P-type semiconductor substrate is shown.

Referring to FIG. 1(b), a first insulating layer 41 is deposited on the entire surface by chemical vapor deposition (CVD). Second insulating layer 42. A third insulating layer 43 is deposited in this order. The composition and thickness of each layer are as follows.

? 1. First insulating layer Si0■ 1500 people42.
Second insulating layer SiJ. 500 people 43. Third insulating layer Si0. 2,750 people FIG. 1(c) Reference A first groove-shaped opening 5 with a width of 1 μm is opened on the third insulating layer 43 on the buried layer 3 close to the element isolation region 2 and reaches the buried layer 3. Form.

Referring to FIG. 1(d), a collector layer 6, a base layer 7, and an emitter layer 8 are selectively epitaxially grown in this order on the buried layer 3 in the first opening 5. The formation conditions and the thickness of each layer are as follows.

? Item: SillzCIz + HCI +ll■(
Carrier gas) The volume ratio of SiHzC1z and HCI is 10
0 to 5 to 30 pressure is 1OTorr 6, collector layer (n type) 1250 people 7. Base layer (p type) 1000 people 8, emitter layer (n +
Type) 1250 peopleRefer to Fig. 1(e), this is the process of forming a window for drawing out the base electrode and collector electrode.

A mask (not shown) having a groove-shaped opening with a width of 1 μm on the element isolation region 2 and the buried layer 3 is formed on the third insulating layer 43, and reactive ion etching (RIE) is performed from the opening.
), the first insulating layer 41, the second insulating layer 42 . Third
The insulating layer 43 is removed, and a second opening 9. is formed on the element isolation region 2. A third opening 10 is formed on the buried layer 3.

The etching conditions are as follows.

? 1. First! ! ! Limb layer: CF4 + CIl■Fz(
1:1)42. Second insulating layer: CF4 43. 3rd (7) vA marginal layer: CF4 + CthFz
(1:1) The width 2 of the insulating layer between the first aperture 5 and the second aperture 9 is 5000, and the width L of the insulating layer between the first aperture 5 and the third aperture 10 is It is 1 μm.

Referring to FIG. 1(f), the second insulating layer 42 is removed from the first opening 5 and the second opening 9 by selective etching using hot phosphoric acid at 180°C, and the inside of the first opening 5 is removed. The side surfaces of the base layer 7 are exposed.

This selective sex. Stop when the side surface of the base layer 7 is fully exposed in the first opening 5. The second insulating layer 42 is left between the first opening 5 and the third opening 10.

Referring to FIG. 1(g), aluminum is deposited on the entire surface by chemical vapor deposition to form a metal layer l1. The forming conditions are as follows.

AI (CTo > s + Ib (carrier gas) substrate temperature approximately 300″C Aluminum fills the second opening 9 and connects to the side surface of the base layer 7, and also fills the third opening IO. It is connected to the buried layer 3 under the collector layer 6.

Refer to FIG. 1(h), the aluminum metal layer 11 is patterned. A collector electrode 12, a base electrode 13, and an emitter electrode 14 are formed.

In this way, a bipolar transistor element is formed. Its base resistance was 200Ω. On the other hand, when polysilicon was used for the base lead-out electrode in a similar structure, the base resistance was 400Ω.

In addition to AI, there are other materials for the base extraction electrode.
AISi alloys, W, Si alloys, etc. containing about 1% of St may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, a bipolar transistor with low base resistance can be provided. The present invention greatly contributes to increasing the speed of bipolar transistors.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(h) are diagrams for explaining the manufacturing process of an embodiment of the present invention. In the figure. 1 is a semiconductor substrate, 2 is an element isolation region, 3 is a buried layer, 41 to 43 are first to third insulating layers, 5 is a first opening, 6 is a collector layer, 7 is a base layer, 8 is an emitter layer. 9 is the second aperture, 10 is the third aperture, 11 is the metal layer, 12 is the collector electrode, l3 is the base electrode, 14 is the emitter electrode (Fig.

Claims (1)

[Claims] On a semiconductor substrate (1) having an element isolation region (2) and a buried layer (3), a first insulating layer (41) and a second insulating layer (
42), a step of stacking a third insulating layer (43) in this order, and forming an opening in the third insulating layer (43) on the buried layer (3) close to the element isolation region (2). After forming the first opening (5) reaching the buried layer (3), the first opening (5) is formed.
) by selective epitaxial growth to form a collector layer (6),
A base layer (7) and an emitter layer (8) are formed in this order,
and the thickness of the collector layer (6) is set to the thickness of the first insulating layer (41).
), and the sum of the thickness of the collector layer (6) and the thickness of the base layer (7) is the thickness of the first insulating layer (41) and the thickness of the second insulating layer (42). forming a second opening (9) in the third insulating layer (43) on the element isolation region (2) and reaching at least the first insulating layer (41); ), and removing the second insulating layer (42) from the second opening (9) by selective etching to form a side surface of the base layer (7) in the second opening (9). After exposing the base layer (7), a metal layer (11) is deposited in the second opening (9) to form a base electrode (13) connected to the side surface of the base layer (7). A method for manufacturing a semiconductor device.