JPH02228066A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve mutual conductance to signal voltage by forming first and second semiconductor element formation areas of a semiconductor substrate of the first conductivity type such that the circumferences are surrounded by the first semiconductor layers of the second conductivity types. CONSTITUTION:A pnp bipolar transistor 30A and an n-channel JFET 30B are formed separately such that the circumferences are surrounded by an n<+> buried layer 21 and an n layer 22 being formed on a p-type substrate 1. Moreover, these n<+> buried layer 21 and n layer 22 are formed in a region which is surrounded by the p-type substrate 1 and isolating layers 2a and 2b. That is, the first and second semiconductor element formation areas are formed, with the circumferences being surrounded by the first semiconductor layers of the second conductivity types, on the semiconductor substrate of the first conductivity type, so those are in the conditions of being electrically isolated from the semiconductor substrate 1. Accordingly, desired signals can be supplied to semiconductor elements to be formed in the first and second semiconductor element formation areas, without exerting influence upon the substrate potential. Hereby, mutual inductance to control signals can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device in which a junction field effect transistor and other semiconductor elements are formed on the same semiconductor substrate, and particularly relates to a semiconductor device in which a junction field effect transistor and a bipolar transistor are formed on the same semiconductor substrate. The present invention relates to semiconductor devices formed on the same semiconductor substrate.

[Conventional technology]

It has been known for a long time that the structure of a junction field effect transistor (hereinafter referred to as rJFETJ) is a structure that can coexist with bipolar transistor technology and can be manufactured at the same time.

FIG. 4 is a cross-sectional view of a conventional n-channel J FET integrated with a bipolar transistor in a bipolar transistor unihub assembly. As shown in the figure, an npn bipolar transistor (hereinafter referred to as rnpnTJ) 10A, an n-channel J
F E -r 10 B are respectively formed on p-type substrate 1 and p+ portions 1ff2a, 2bk: nff3.3, which are element formation regions separated from each other.

On the 0 layer 3 of npnTloA, an n" emitter (i') contact region 4 and a p base region 11ii5 are formed, and an n+ collector region 6 is formed on a part of this p base region 1815. Then, an emitter electrode 7 is formed on the n+ emitter contact region M4, and an emitter electrode 7 is formed on the p base region 1a5.
The base electrode 8 is on the n+ collector region bI! A collector electrode 9 is formed on L6. These electrodes 7~
9 are each insulated by an insulating film 11. Also,
An n+ buried layer 12 is formed between the 0 layer 3 and the p-type substrate 1.

On the other hand, on nN3 of n-channel JFET10B, n+
A source region [13, a p gate region 14 and an n+ drain region 15 are formed, respectively.

A source electrode 16 is formed on the n + source region 1t13, a gate electrode 17 is formed on the p gate region 14, and a train electrode 18 is formed on the n drain region 15. These electrodes 16 to 18 are each insulated by an insulating film 11. Furthermore, a p+ buried Ji 19 is formed between the 0 layer 3 and the p type substrate 1. This p
+The buried layer 19 is designed to reduce npnTloA without lowering its breakdown voltage.
This is provided to narrow the channel width of channel JFETIOB.

Such a structure of npnTloA and n-channel JFE
In TIOB, the former uses the 0 layer 3 as a collector region, and the latter as a channel region. Furthermore, when forming the p base region 5, the p gate region 14 is formed and the n
The n1 source region 13 and the n+ drain region 15 are formed when the + emitter contact region 4 and the n+ collector region 6 are formed, and the p+ buried layer 19 is formed when the p+ isolation W2b is formed.

FIG. 5 is an explanatory diagram illustrating the operation of the n-channel JFET 10B shown in FIG. 4. As shown in the figure, the source electrode 16 is grounded, the gate electrode 17, the source electrode 16
voltage (-VG) and V between and drain electrode 18, respectively.

When the voltage is applied (signal voltage v in"" o), the depletion layer 20 (20a, 20b) expands. This depletion layer 2
By changing the thickness of 0, the effective width of the current path between the source and drain is changed, and the amount of current between the source and drain is controlled.

The source-gate voltage V of such an n-channel JFE
. The mutual conductance for is generally expressed by the following equation (1).

Determine. However, in equation (2), q is the electron charge, ND is the impurity concentration of the channel, and ε is the dielectric constant of silicon.

In the n-channel JFET 10B having such a structure, the p-type substrate 1 itself also functions as a part of the gate, and depending on the substrate potential,
The thickness of the depletion layer 20b on the p-type substrate 1 and the p+ buried layer 19 is determined.

Therefore, assuming that the signal voltage V is applied to the p-gate region 14n and the p-type substrate 1, the signal voltage V,
The mutual conductance 'no' for is determined by the following equation (3).

Here, ρ is the specific resistance of the channel region (0 layer 3), 2a is the channel length, 2a is the channel width, Z is the depth of the channel perpendicular to L and 28, and 2 is the pinch-off voltage. Furthermore, the pinch-off voltage V is [a problem to be solved by the invention]. However, since the p-type substrate 1 always needs to be fixed at a lower potential than other elements formed on the p-type substrate 1, the depletion layer The signal voltage vio that controls the thickness of the p-type substrate 1 cannot be applied to the p-type substrate 1, and the signal voltage Vio can only be applied to the p+ gate region 14, which is separated from the p-type substrate 1 by n13. .

Therefore, the depletion H20 whose width is modulated by the signal voltage IO is only the depletion layer 20a around the p-gate region [14].

That is, the mutual conductance g,' with respect to the signal voltage vin is a'# 1/ as shown in the following equation (4).
2aIo (4) There is a problem in that the mutual conductance 'IQ becomes approximately 1/2 of the value when it is assumed that the signal voltage 1o is also applied to the p-type substrate 1.

This invention was made in order to solve the above-mentioned problems, and it is possible to form a junction field effect transistor with high mutual conductance for control signals by forming multiple types of semiconductor elements on the same semiconductor substrate. The purpose is to obtain a formed semiconductor device.

[Means to solve the problem]

A semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type, a first semiconductor layer formed on a distribution semiconductor substrate and surrounded by a first semiconductor layer of a second 'S conductivity type. a second semiconductor element formation region, and a first semiconductor element formed in the first and second semiconductor element formation regions, respectively. a second semiconductor element; Each of the second semiconductor element formation regions includes a second semiconductor layer of a first conductivity type formed on the first semiconductor layer and a second conductivity type formed on the first semiconductor layer. a third semiconductor layer formed on the third semiconductor layer, and a second semiconductor layer formed on the third semiconductor layer; a plurality of active layers forming the semiconductor element together with a third semiconductor layer; the first semiconductor element has at least one of the active layers as a first control electrode region; is used as a second control electrode region, and the third semiconductor layer between the first and second electrode regions is made to function as a channel region.

[Effect]

First in this invention. The second semiconductor element formation region is
Since it is formed on a semiconductor substrate of a first conductivity type and surrounded by a first semiconductor layer of a second conductivity type, it is electrically isolated from the semiconductor substrate. therefore,
1. without affecting the substrate potential. ξ by applying a desired signal to the semiconductor element formed in the second semiconductor element formation region.

〔Example〕

FIG. 1 shows a vertical pnp bipolar transistor (hereinafter simply referred to as "pnρTJ"), which is an embodiment of the present invention.

) is a cross-sectional view showing the n-channel JFE king integrated together with this pnp king in Unihabmycetes.

As shown in the figure, pnpT30A, n-channel JFE
T30B is the n+ buried layer 21 formed on the p-type substrate 1
andnl! ! 22, so that they are formed separately from each other. That is, pnpT30A,
n Chisenel JFE Ding 30B is p'! It is electrically isolated from the substrate 1. Also, these n+ embeddings [i2
The 1 and 0 layers 22 are formed in a region surrounded by the p-type substrate 1 and the p-separation layers 2a and 2b.

Both pnp-30A and n-channel JFET30B are
n+embedded M21. and p+1123 (2
3a, 23b) are formed and this p''!23
A 0 layer 24 is formed thereon.

In the pnpT 30A, an n+ base contact region 25 and a p emitter region 26 are formed on the 0 layer 24, and base electrodes 27.26 are formed on these regions 25.26, respectively. An emitter electrode 28 is formed. Also, p”
A collector electrode 29 is formed on a part of the surface of the layer 23a. These electrodes 27 to 29 are each insulated ll1
It is insulated by 111.

On the other hand, in the n-channel JFET30B, the 0 layer 24
On top is an n+ source region 31. A p gate region 32 and an n+ drain region 33 are formed, and these regions [31 to
Source electrodes 34.33 are respectively disposed on them. First gate electrode 3
5. A drain electrode 36 is formed. Also, p”!
A second gate electrode 37 is formed on a part of the surface of 23b.

These electrodes 34 to 37 are each insulated by an insulation wA11.

FIG. 2 is a cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. Hereinafter, the manufacturing method will be explained while referring to the same figure.

First, n+ is selectively diffused into the upper layer of the p-type substrate 1.
The buried layer 21 is formed as shown in FIG.
Selective n
Diffusion is performed to form a p-diffusion layer 41 as shown in FIG. 4(b).

Next, by epitaxial growth technology on the p-type substrate 1,
form nJ122. At this time, the n+ buried ff21 and the p+ diffusion layer 41 are diffused upward as shown in FIG.

Next, n-diffusion is selectively performed in the upper layer portion of the 0 layer 22 to form an n-diffused layer. As a result, the p+ diffusion layer 41 formed in the lower part of the 0 layer 22 and this n diffusion layer are combined, so that the p+
The layers 23a, 23b have p+ isolation layers 2a, 2b in other regions.
is formed.

The region of the layer 22 surrounded by p+1523a and 23b becomes the 0 layer 24.

Next, n diffusion is selectively performed in the upper part of the 0 layer 24, and as shown in FIG. A p-gate region [32 is formed on the inner 0 layer 24.

Furthermore, by selectively performing n diffusion, as shown in If), nl! in the p+ layer 2a! ! n+ on 124
Base region 25, p+ again! An n+ source region 31 and an n+ drain region 33 are formed in the 0 layer 24-hi in 123b.

Next, an insulation g having contact holes on the entire surface of the n layer 22 is prepared.
111 are formed, and electrodes 27 to 29 . are formed in the contact holes using aluminum or the like, respectively. Electrodes 34 to 37 are formed, and the semiconductor device shown in FIG. 1 is completed.

FIG. 3 is an explanatory diagram showing the effect of the n-channel JFET 30B shown in FIG. 1. The p+ layer 23k) of the n-channel JFET 30B is completely electrically isolated from the p-type substrate 1 by the n+ buried layer 21 and the 0 layer 22. Therefore, the signal voltage Vi0 can be applied to the p+ layer 23b as well as the p gate region 32.

As a result, the signal voltage V; Therefore, the depletion 1f around the p-gate region 32 is reduced by 1f! The width of not only the depletion layer 40a but also the depletion layer 40b around the p+ layer 23b is modulated.

That is, the mutual conductance 0 11 for the signal voltage V in the JFET of this example is given by the following In
1, (5), the mutual conductance q of the conventional JFET shown in FIGS. 4 and 5 is improved to about twice.

Ugly, in this embodiment, a vertical pnp is placed on the p-type substrate 1 in the figure.
A bipolar transistor and an n-channel JFET were formed, but the polarity was reversed and a vertical np transistor was formed on the same n-type substrate.
It is also possible to form n-bipolar transistors and p-channel JFETs. Further, in this embodiment, the same signal voltage Vi0 is applied to the p gate region 32 and the p+ layer 23b, but different signal voltages may be applied to each.

In addition, in this embodiment, element isolation is performed using an n+ buried layer 21.0.
Since this is done using the layer 22, it is not necessarily necessary to form the p+ isolation layers 2a and 2b. However, if the p+ molecule In layers 2a and 2b are not provided, p
Collector electrode 29 of npT30A and p-channel JFET
Since there is a possibility that a current may flow between the second gate electrode 37 and the second gate electrode 30B, it is preferable to form p+ portions 1t112a and 2b.

〔Effect of the invention〕

As described above, according to the present invention, the first and second semiconductor element formation regions are formed on a semiconductor substrate of a first conductivity type and surrounded by a first semiconductor layer of a second conductivity type. The semiconductor substrate is electrically isolated from the semiconductor substrate.

Therefore, the first . A signal voltage can be freely applied to the second control O electrode region, which has the effect of improving mutual conductance with respect to the signal voltage.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a cross-sectional view showing a semiconductor device as an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1, and FIG. FIG. 4 is a cross-sectional view showing the effect of the semiconductor device shown in FIG. 1, FIG. 4 is a cross-sectional view showing a conventional semiconductor device, and FIG. 5 is a cross-sectional view showing the operation of the semiconductor device shown in FIG. In the figure, 1 is a p-type substrate, 21 is an n+ buried layer, 22.
24 is an n layer, 23a and 23b are p+ layers, 31 is an n+ source region, 32 is a p base region, and 33 is an n+ drain region. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 2 (Part 1) Figure (f-2) Figure ↓

Claims (1)

[Claims] (1) a semiconductor substrate of a first conductivity type, and first and second semiconductor element formation regions formed on the semiconductor substrate surrounded by a first semiconductor layer of a second conductivity type; , first and second semiconductor elements formed in the first and second semiconductor element formation regions, respectively;
Each of the semiconductor element formation regions includes: a second semiconductor layer of a first conductivity type formed on the first semiconductor layer; and a second semiconductor layer of a second conductivity type formed on the second semiconductor layer. Third
and an active layer that is formed on the third semiconductor layer and forms the semiconductor element together with the second and third semiconductor layers, and the first semiconductor element comprises a semiconductor layer of the active layer. At least one of the control electrode regions is a first control electrode region, and the second semiconductor layer is a second control electrode region.
a control electrode region, and the third semiconductor layer between the first and second control electrode regions functions as a channel region.