JPH07202225A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a lateral transistor used in diode connection with a high breakdown reverse-voltage, by preventing an inversed layer caused by a reverse voltage in a parasitic MOS transistor, along with no functional damage to a diffusion structure even when the semiconductor is used in transistor connection. CONSTITUTION:In a diode structure, in which an emitter 5 of a lateral PNP transistor functions as an anode and a collector 6 and a base 7 function as a cathode, a polysilicon layer 9 with the same potential as the cathode is formed. Then, an inversed layer caused on a surface of a base region 2 is prevented even when a large reverse voltage is applied to the diode, and the breakdown strength in the diode against reverse voltage is improve. In addition, the lateral transistor functions well even when it is used conventionally as a normal lateral PNP transistor. The structure is suitable for a master slice-type semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and provides a technique for forming a diode having a high reverse breakdown voltage with less parasitic effect.

[0002]

2. Description of the Related Art In a master slice type semiconductor device, a diode required for a circuit is formed by utilizing a diffusion layer of a transistor. Therefore, in the master slice semiconductor device having the lateral PNP transistor as a main constituent element, the diode is formed by using the diffusion layer of the lateral PNP transistor.

2A and 2B are a plan view and a sectional view, respectively, showing a structure of a conventional diode using a diffusion layer of a lateral PNP transistor. As shown in the figure, this diode is used in a state in which the emitter 5 of the lateral PNP transistor is the anode, and the cathode is the collector 6 and the base 7 shorted by the aluminum wiring 11.

[0004]

By the way, in the diode having the above structure, the emitter diffusion layer 5 and the collector diffusion layer 6 are formed.
And a parasitic MO whose gate is the anode electrode wiring 11 between
An S transistor is formed. Therefore, when a reverse voltage is applied between the diode electrodes and the voltage causes the potential difference between the anode potential and the cathode potential to exceed the inversion voltage on the surface of the N-type epitaxial layer 3, that is, the threshold voltage of the parasitic MOS transistor. The inversion layer 13 shown in FIG. 2B is formed immediately below the aluminum wiring 11 on the anode side. The formation of the inversion layer 13 has a problem that the breakdown voltage between the emitter diffusion layer 5 and the collector diffusion layer 6 is lowered, and as a result, the reverse breakdown voltage of the diode is lowered.

FIGS. 3A and 3B show the structure of a conventional semiconductor device having an improved diode structure that solves the above problems. This figure shows a diode of such a lateral PNP transistor structure as in FIG. In this diode, in addition to the structure shown in FIG. 2, between the emitter diffusion layer 5 and the collector diffusion layer 6 of the lateral PNP transistor, a high concentration of the same conductivity type as the base diffusion layer 7 is provided so as to surround the emitter diffusion layer 5. The channel stop region 14 is provided. This prevents formation of a parasitic MOS transistor between the emitter and collector diffusion layers 5 and 6.

However, in the diode having the above structure, although the reverse breakdown voltage of the diode can be improved by forming the high-concentration N-type channel stop region 14, the inversion layer is formed by the existence of the high-concentration N-type channel stop region 14. The reverse breakdown voltage is lower than the reverse breakdown voltage of a diode having a similar structure without the channel stop region 14 in the case where a structure in which the above phenomenon does not occur can be provided.

Further, when the improved diode is adopted in the master slice type semiconductor device, in order to use the transistor having the same diffusion layer structure as the original lateral PNP transistor, the high concentration N-type channel is used. Current amplification rate (h _FE ) when the stop region is grounded
, So that the function as a PNP transistor is insufficient. Therefore, the above structure is difficult to be adopted in the semiconductor device of the master slice type.

In view of the above, the present invention provides a semiconductor device provided with a diode-connected lateral transistor that performs the original function of the lateral transistor and can be configured as a diode having a sufficiently high reverse breakdown voltage. Therefore, an object is to provide a semiconductor device suitable for a master slice type semiconductor device.

[0009]

In order to achieve the above object, a semiconductor device of the present invention includes an emitter connected to an anode electrode wiring, and a collector and base region connected to a cathode electrode wiring of a semiconductor substrate. In a semiconductor device including a PN junction diode having a lateral PNP transistor structure in a surface region, a conductive film disposed between a wiring layer forming the anode electrode wiring and at least the base region and maintained at a predetermined potential. Is further provided.

The conductive film is preferably formed, for example, as a polycrystalline silicon (polysilicon) layer on the substrate. Further, it is preferable to select the same potential as the cathode electrode wiring as the predetermined potential, and in this case, pattern formation of the conductive film is easy.

[0011]

The present invention will be further described below with reference to the drawings. 1A and 1B are a chip plane view and a cross-sectional view of a diode portion in a semiconductor device formed by a master slice method, which form an embodiment of the present invention, respectively. Further, FIG. 6C is an equivalent circuit diagram thereof.

In manufacturing the above semiconductor device, first,
Using a conventional semiconductor manufacturing technique, an N type buried layer 2 is formed in a P type silicon substrate 1 by an ion implantation method, and a P type diffusion layer 5 is formed in an N type epitaxial layer 3 grown on the N type buried layer 2. , 6 and the N-type diffusion layer 7 are formed by the ion implantation method to form the emitter 5, the collector 6 and the base 7 for the lateral PNP transistor.

Next, the first insulating film 8 is formed on the entire surface of the silicon substrate 1 and patterned by the photolithography technique. Then, an N-type polysilicon layer 9 is formed on the entire surface of the first insulating film 8, and the photolithography technique is used to
As shown in FIG. 1, patterning is performed so as to cover the base region 3 of the lateral PNP transistor. Subsequently, after the second insulating film 10 is formed on the entire surface, the emitter contact window 15, the collector contact window 16 and the base contact window 17 are formed by using the photolithography technique.
Are opened on the diffusion layers 5, 6 and 7 respectively corresponding thereto.

After that, the anode electrode wiring 11 and the cathode electrode wiring 12 are formed by a sputtering method using aluminum or the like. At this time, the anode wiring 11 is connected to the emitter diffusion layer 5, and the cathode wiring 12 is connected to the collector 6 and the base 7, so that the emitter E is the anode A and the collector C and the collector C are as shown in FIG. A diode having the base B as the cathode K is formed. It should be noted that by adopting a configuration different from the wiring connection of FIG. 1 by selecting the aluminum wiring, the original lateral type PNP can be obtained.
A transistor is formed.

In the semiconductor device of this embodiment formed as described above, the N-type polysilicon layer 9 is biased to a high potential even when a reverse voltage is applied between the anode A and the cathode K of the diode. The base area 3
Even if there is the anode electrode wiring 11 formed on the upper portion and biased to a low potential, the potential of the anode electrode wiring 11 does not affect the base region 3 due to the action of the N-type polysilicon layer 9. Therefore, the inversion layer 13 as shown in FIG. 2 does not occur on the surface of the base region 3 immediately below the anode electrode wiring 11. Therefore, in the conventional semiconductor device, for example, a diode having a structure in which only a reverse breakdown voltage of about 2 V is obtained can obtain a reverse breakdown voltage of about 30 V.

In the case of the conventional improved semiconductor device in which the high concentration channel stop region 14 (FIG. 3) for preventing the formation of the inversion layer is formed, the high concentration channel stop region 1 is formed.
Since the expansion of the depletion layer is suppressed in No. 4, the reverse breakdown voltage is reduced, and the reverse breakdown voltage is reduced as compared with the case where the high concentration channel stop region 14 is not provided. However, the structure of the semiconductor device according to the above-described embodiment does not have the drawback of lowering the reverse breakdown voltage.

Further, in the structure of the improved semiconductor device in which the high-concentration channel stop region is provided, when the element having the high-concentration diffusion layer is used as the original lateral PNP transistor, the current amplification factor is lowered. However, the structure of the semiconductor device of the above-described embodiment does not have such a defect and the function when used as an original lateral type PNP transistor is impaired. There is no danger of
Therefore, when the semiconductor device of the present invention is applied to a master slice type semiconductor device, its advantages are particularly great.

It should be noted that the description of the above embodiment is made for the purpose of illustration, and a semiconductor device in which various modifications and changes are made from the configuration of the above embodiment is also included in the scope of the semiconductor device of the present invention. For example, in the above-described embodiment, the polysilicon layer may be maintained at a potential different from that of the cathode electrode wiring within a range where the inversion layer is not formed in the N-type epitaxial layer. Further, the semiconductor device of the present invention is
The semiconductor device is not limited to the master slice type semiconductor device.

[0019]

As described above, the semiconductor device of the present invention comprises the conductive film of a predetermined potential disposed between the wiring layer forming the anode electrode wiring and the base region.
By adopting the diode of the lateral type transistor structure, the inversion layer is not formed on the surface of the base region even when a large reverse voltage is applied, so that a diode with a high reverse breakdown voltage can be formed and simply by selecting the wiring layer, Since an original lateral transistor can be formed instead of forming a diode, the present invention has a remarkable effect that a semiconductor device suitable as a master slice type semiconductor device can be provided.

[Brief description of drawings]

1A and 1B are a plan view and a cross-sectional view, respectively, of a semiconductor device according to an embodiment of the present invention.

2A and 2B are a plan view and a sectional view of a semiconductor device including a conventional diode having a lateral PNP transistor structure, respectively.

3A and 3B are a plan view and a cross-sectional view, respectively, of a conventional semiconductor device including an improved diode in which a high-concentration channel stop region is formed.

[Explanation of symbols]

 1 P-type semiconductor substrate 2 N-type buried layer 3 N-type epitaxial layer 4 P-type insulating region 5 P-type emitter 6 P-type collector 7 N-type base 8 First insulating layer 9 N-type polysilicon layer 10 Second insulating film 11 Anode electrode wiring 12 Cathode electrode wiring 13 Inversion layer 14 N-type high-concentration channel stop region 15 Emitter contact window 16 Collector contact window 17 Base contact window

Claims (3)

[Claims] 1. A lateral type PN having an emitter connected to an anode electrode wiring and a collector and base regions connected to a cathode electrode wiring in a surface region of a semiconductor substrate.
A semiconductor device including a PN junction diode having a P-transistor structure, further comprising a conductive film that is disposed between a wiring layer that constitutes the anode electrode wiring and at least the base region and is maintained at a predetermined potential. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the predetermined potential is a potential of the cathode electrode wiring. 3. The semiconductor device according to claim 1, which is configured as a master slice.