JPH02224020A - Adding and subtracting device - Google Patents

Abstract

PURPOSE:To obtain a fast adding and subtracting device which can be used without being aware of whether data to be added or subtracted is floating-point or fixed-point data by providing a means which converts floating-point data into fixed-point data. CONSTITUTION:When a floating-point display is converted (FLFX) into a fixed- point display, an exponent part satisfies a relation alphaE(alphaE: the exponent part of output data alpha from a selecting circuit 61)<betaE(betaE: the exponent part of output data beta from a selecting circuit 60), data having the value of a mantissa part betaM=0 is stored in a specific address of a data memory 5 or 6, and this address is made correspond to an address part of the instruction word of the FLFX. Then when the instruction of the FLFX is executed, calculation between two floating-point data A and data y1 is carried out and its calculated result is obtained in an accumulator 16. This data is normalized and the data of the mantissa part outputted to a data bus 20 is handled as fixed-point data. Consequently, a fast, high-accuracy OR arithmetic function is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an addition/subtraction device that can be incorporated into, for example, a digital signal processing processor to realize a high-speed, high-precision product-sum calculation function that can process data such as audio and one image in real time. Useful.

In devices such as voice synthesis or analysis, modems (modems), digital filters, codecs (CODECs), echo cancellers, etc. in the communication field,
The application of signal processing processors that can process digitized signals in real time is being considered.

This signal processing processor is provided as an LSI that includes a program memory and a dedicated multiplier and adder/subtractor for processing data at high speed, and can be adapted to various uses by changing the program.

When the above-mentioned signal processing processor is used for filter processing of audio signals, for example, the internal calculation data becomes a relatively large amplitude of 16 to 28 bits due to the product-sum calculation. For this reason, if the structure of the multiplier or adder/subtracter is a fixed-point f-ta operation type, the hardware scale will increase exponentially as the number of bits of operation data increases, making it difficult to implement into an LSI.

This problem can be solved by using a floating iJX several-point data calculation type for the configuration of the pro-7°. However, if we adopt the data processing method of a conventional general-purpose computer, in which a multiplier and an adder/subtractor are connected by a data bus and each performs floating-point operations independently, the basic operation of a signal processing processor is Product-sum calculations take time, making real-time processing of signals difficult.

The purpose of the present invention is to create a new configuration that is suitable for LSI integration, can be used without being aware of whether the data to be added/subtracted is floating point or fixed point, and can process digital signals at high speed in real time. An object of the present invention is to provide an addition/subtraction device useful for signal processing processors and the like.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a digital signal processor to which the present invention is applied, in which 1 is a memory for storing programs, 2 is a program counter for instructing the read address of the program memory 1, and 3 is the program memory. An instruction register 4 connected to the instruction register 4 is a control circuit that generates various control signals S for operating the processor from the instruction word read into the instruction register 3. In this embodiment, the number of instruction words stored in the memory 1 is, for example, 22.
It consists of bits, each containing an operation code, data, and address or address control information. The program counter 2 and the instruction register are connected to a 16-bit data bus (D bus) 20.

5.6 is a memory for storing data, and 7 is a general-purpose register. Memories 5 and 6 have one side randomly accessed.
Memory (RAM), the other is read-only memory (ROM)
). Further, each memory may be a plurality of ROMs of /J% capacity or a composite of ROMs. The above memory stores 16 bit data,
Each data is sent to the 16-bit X bus 21 via the selection circuit 8.
Alternatively, it is read out to the Y bus 22. 9 and 10 are registers that designate lower addresses of the data memories 5 and 7, respectively; 11. ．． 12 is a register that specifies the upper address of the memory. Note that register J1 is connected to X bus 21.
The upper address of the data to be read to register 1.
2 gives the Y bus 22 the upper address of the data to be read or the address of the general-purpose register 7, and address information is given to these registers from the instruction register 3 via the data bus 23.

14 is a floating point multiplier that calculates the product of two data given from the X bus 21 and the Y bus 22 and outputs the result to the P bus 24. Input data X.

It includes a register for holding Y, and the two unoperated data X and Y are directly transferred to the X bus 25. Output Y bus number 26.

Reference numeral 15 denotes a floating point arithmetic type adder/subtractor, which receives the output data X, , Y, P of the -1- notation multiplier 14 and the data bus 2.
Data D and A of 0.27 are manually operated and the results are output to the accumulator 1-6.

A switch circuit 17 outputs the floating point data latched by the accumulator 16 to a 20-bit data bus (A bus) 27, and also converts the data into 16-bit data and outputs it to the D bus 20. 18 is the above multiplier]-
4 and the adder/subtractor 15, and is a status codeless register that stores status codes related to the results of these operations.

30 transfers the 1-6 bit data on the data bus 20 to external terminals D0 to D1. 3 is an input register for inputting 1.6-bit data from the external terminal to the data bus 20 in parallel. Further, 32 is a 16-bit shift register for taking in serial input data from terminal SI in synchronization with the input clock of terminal 5ICK while the input pulse of terminal 5IEN is "1", and 33 is the input pulse of terminal 5OEN. 1 for serially outputting data to the terminal SO in synchronization with the input clock of the terminal 5OCK during the period when is "1".
Two shift registers shown in FIG. 9 are each connected in parallel to a data bus 20 of 16 bits.

35 is a register that controls the operating state of the processor; 36
37 is a counter to which the number of repetitions is set when the processor is caused to repeatedly execute an instruction by a repeat instruction, and 37 is a status register indicating the internal state of the processor.

The contents of registers 35 and 37 are data buses 20 and 37, respectively.
Writing and reading are possible from the outside via terminals RI and D.

40 is a control circuit for controlling interrupts to processor operations and input/output operations; for example, terminals 5IEN, 5O
The shift registers 32 and 33 are enabled at the rising edge of the EN input signal, and the program is interrupted at the falling edge of each signal.

At the rising edge of the input/output signal to terminal IE, registers 30 and 31
starts and interrupts the program at the falling edge. 41 is a function control circuit that controls processor operation in response to signals from an external control device (for example, a microcomputer); , signal, terminal R
A signal indicating the transfer direction of parallel input/output data from /W, a signal indicating that an external device has selected this processor from terminal C8, and a test operation mode designation signal from terminal TEST.

It receives a reset signal from R5T, an operation control signal from an external device from terminal F0-1, and outputs a parallel data transfer request signal from terminal TxRQ.

The terminal Bit Ilo indicates a bidirectional input/output terminal for inputting and outputting data one bit at a time. 42 is a clock pulse generation circuit, which receives and receives a basic clock from an external circuit via a terminal oSC.

Based on this, various internal clocks necessary for processor operation are generated, and a clock for synchronizing the internal operation of the processor and an external system is output to terminal 5YNC.

Next, the multiplier 14 and the adder/subtractor 15 will be further explained with reference to FIGS. 2, 3, and 4.

The multiplier 14 receives 16-bit data from the X bus 21 and the Y bus 22 as shown in FIG.

These data are given from memories 5 and 6, general register 7, or data bus 20. As shown in Figure 3 (A), these data have the lower 4 bits as the exponent part and the higher 12 bits as the mantissa part, and the most significant bits of each part shown with diagonal lines, that is, 23 and 21%. The bit at position is the sign bit. Also, the decimal point is between 2'' and 214. As shown in Figure 2,
The exponent data and mantissa data given from the X bus 2] and the Y bus 22 are held in registers 51, 52, 53, and 54, respectively, and the exponent data in registers 51 and 52 are added by an adder circuit 55. It is output to the P bus 24 via the bit output register 56. On the other hand, the mantissa data in the registers 53 and 54 is input to a multiplication circuit 57 having a circuit configuration similar to that of ordinary fixed-point arithmetic, and the 5-multiplication result is output to the 1-no register 58 with the upper 16 bits.
The signal is output to the P bus 24 via the P bus 24. In other words, the multiplier 14
As shown in FIG. 3(B), the output of the calculation becomes 20-bit data consisting of a lower 4-bit exponent part and an upper 6-bit mantissa part, and is input to the adder/subtractor 5. still,
The outputs of registers 52.54 are sent to the X bus 25 and also to registers 51.54. ．． The outputs of 53 are sent to the Y bus 26 and given to the adder/subtractor 15 as 16-bit data.

FIGS. 4(A) and 4(B) show the configuration of an adder/subtractor 15 according to an embodiment of the present invention. As shown in FIG. 4(A), the adder/subtractor is , data D, P,
X, , Y, A are input, and 1 specified by the control signal S
data is selected.

Further, the data A and X are input to the selection circuit 6, and one data designated by the control signal S2 is selected.

Here, the input data D, X, Y are shown in Figure 3 (A).
This is the 16-bit data shown in . As will be described later, when these 16-bit data are designated, the selection circuits 60 and 61 convert these data into 20-bit I-data as shown in FIG. 3(B) and output it. It has become. This bit conversion differs depending on whether the input data D, X, Y is fixed point data or floating point data, and the conversion operation is specified by the control signal S. This allows the floating-point type adder/subtractor to process input data in fixed-point representation. still.

Control signals S,, S2. S, ......Sn is the output data from the selection circuit 60, which is output from the control circuit 4 in response to the instruction word in the program, β (exponent part βE,
If the output data from the selection circuit 61 is α (exponent αε, mantissa αH), then the exponent data αE is input to the comparison circuit 63 via the selection circuit 62 and is compared with the exponent data βE in magnitude. be compared. Further, the exponent data αEl and βE of Niku et al.
5 is also input.

The mantissa data α is inputted to the selection circuit 67.68 via the negation circuit 66, and the mantissa data 6 questions are directly inputted to the selection circuit 67.68. In this embodiment, the negate circuit 66 is provided to realize the subtraction between the data α and β using the ALU 75 having an adder configuration, and in the case of an addition operation, the data αH is passed through the negate circuit. Pass by. The selection circuits 65, 67, and 68 each select one of the two inputs according to the output signal of the comparison circuit 1663. The output of the selection circuit 65 is sent to the latch circuit 71, the output of the y1 selection circuit 67 is sent to the latch circuit 72 via the shift circuit 69, and the output of the selection circuit 68 is sent to the latch circuit 7.
3 and latched by timing signal C, respectively. The subtraction circuit 64 is also controlled by the output of the comparison circuit 63,
It operates to subtract the smaller input from the larger one of inputs αE and βE according to the comparison result. The shift circuit 69 shifts the input data to the right by the number of bits corresponding to the output of the subtraction circuit 64 obtained via the selection circuit 70. The operation of this shift circuit 69 can also be controlled by another data E input to the selection circuit 70, and the number of shift bits is selected by the control signal S7.

The outputs eAI eB of the latch circuits 72 and 73 are shown in FIG.
As shown in B), the addition result tJM is input to a fixed-point arithmetic type adder (AI□U) 75 operated by the control signal sB, and the addition result tJM is given to a leftward shift circuit 76. On the other hand, the output γ of the latch circuit 71 is input to one input terminal of a constant addition circuit 77 and a subtraction circuit 78. 79 is an adder 75
If the output XJs of the adder given in complement representation is a positive number, it counts the number of consecutive IJOIt bits following the sign bit at the top of TJM. If U14 is a negative number,
The number of consecutive “” bits following the sign bit is counted. The output θ1 of the zero detection circuit 79 is sent to a shift circuit via an output correction circuit 80 provided for data normalization and overflow prevention. 7G, which determines the number of data shift bits by this shift circuit.The output of the 1-, 2 zero detection circuit 79 is also input to the other input terminal of the subtraction circuit 78. The output Ur:, of this subtraction circuit is input to the exponent part 16X of the accumulator 16 via the output correction circuit 80. The output data (, Ml) from the L shift circuit 76 is input.

The output correction circuit 80 adjusts the output O□ of the zero detection circuit 79 and the constant addition circuit 77 according to the overflow detection signal OVF output from the adder 75 and the underflow detection signal UNF output from the subtraction circuit 78. The selection circuit 81 selects either the output 02 of the output 02, and the shift circuit 76 shifts either the output of the selection circuit 81 or the data F given by the program according to the control signal S by the program. Selection circuit 82 for providing bit number instruction signal θ
and an increment circuit 83 which adds 1 to the subtraction circuit output Up when the overflow signal OVF is "1" and outputs a signal EOVF when the addition result LE also overflows, and the increment circuit M83 and the accumulation circuit 83. An exponent part correction circuit 85 inserted between the exponent part 16X of the prime number unit 16, a shift circuit 76, and the mantissa part 16 of the prime number unit 16
The operation of the mantissa part correction circuit 87 inserted between the input signal M and the two correction circuits 85 and 87 is controlled by the signals U N F and E.
It consists of a control circuit 89 that controls according to the OVF.

The adder/subtractor 15 having the above configuration operates as follows.

The respective outputs α and β of the two manual selection circuits 61 and 60 shown in FIG. 4(8) are floating point data, and their values are expressed by the following equation.

β=βH·2 Now, assuming that an addition operation is performed on two data α and β having the relationship αE>βE, the addition result Z is given by the following equation.

The comparison circuit 63 compares the magnitude of σE and βE, and selects the selection circuit 6
5 selects the larger exponent part data αE, the selection circuit 67 selects the mantissa data sieve corresponding to the smaller exponent part βE, and the selection circuit 68 selects the mantissa data sieve corresponding to the larger exponent part αE. A control signal is given to the subtraction circuit 64 to subtract the smaller exponent β P from the larger exponent α E. During execution of the addition operation, the 1 selection circuit 70 selects the output (αE-βE) from the subtraction circuit 64, and the shift circuit 69 selects the output βH from the selection circuit 67.
to the right by (αE-βE) bits (toward the lower bits)
It operates to shift 1-. As a result, the output IJM of the adder 75 that has performed the calculation of e^+es represents the mantissa part of equation (1). Therefore, the calculated value Z at this stage is expressed by the following equation.

is equal to the index value UE, and the normalization process can be expressed by the following equation.

The zero detection circuit 79 and the leftward shift circuit 76 are for normalizing the adder output UN so that its absolute value becomes the maximum. Figure 5 (A)! ,: As shown, the zero detection circuit 79 detects the number 01 of consecutive IIO11s (below the decimal point) following the sign bit of the data UM, and shifts the shift 1-.circuit 76'c data UN by 01 bits to the left (the most By shifting to the upper bit side), mantissa data LH having the maximum absolute value can be obtained. If UN is a negative number, it is only necessary to shift by the number of consecutive 1''s as shown in FIG. Perform the calculation and its output U
If no overflow occurs in the 7 data UN with E as the normalized exponent value, the output LE of the increment circuit 83 will be expressed as a two's complement number, assuming that the magnitude of γ in the normalized exponent part is 4 bits. Therefore, the value that γ can represent is limited to the range of [+7 (γΣ-8)]. Therefore, when normalizing the mantissa data, the detected value θ of the zero detection circuit is completely shifted to the left by the amount of data US. If you try to shift, the value of (γ ~ 01) on the exponent side becomes smaller than -8, which may cause an underflow in the subtraction circuit. At this time, when performing the operation of (γ - 01) From the subtraction circuit 78,
Signal indicating data underflow (borrow signal)
JNF is generated.

In the circuit of FIG. 4(B), when the signal U N F is generated, the selection circuit 81 selects the output θ2 of the constant addition circuit 77 instead of the input θ□, and the constant addition circuit 77 selects the output θ2 of the constant addition circuit 77. The value obtained by adding a constant "8" to the data γ is output as data θ.

In this way, for example, when the value of γ is "-5", θ2
Since the value of is "3", the shift 1- of the mantissa data UN is
The number of bits is limited to 3 bits, and the normalized value of the exponent remains at the minimum value r-8J.

The operation of setting the exponent part to "-8" when the signal UNF is generated is performed by an exponent part correction circuit 85, which will be explained later with reference to FIG.

The calculation result UN of the adder 75 is shown in FIG. 6(A).

When an overflow occurs as shown in (B).

The true sign of the data appears on the carry output, with the most significant bit of the number appearing in the position of the sign bit. Therefore, in this case, the overflow detection signal OVF stops the operation of the selection circuit 81 and the zero detection circuit 79, causes the shift circuit 76 to perform a 1-bit right shift operation, and causes the increment circuit 83 to perform a 1-bit right shift operation. It is only necessary to operate the data 2 as shown in the following equation.

An example of the shift circuit 76 that performs the above operation is shown in FIG. .2 bit shift 763 and 1
The switch SW, ~SW0 of each signal line of each shifter has a corresponding control bit θ.

When ~0° is 111 II, it is connected to the contact on the lower bit side. In addition, each switch SW of the 1-bit shifter 764
, are connected to the contacts on the upper bit side when the overflow detection signal OVF is 111 II, and the sign bit output lines L1. is connected to the carry signal input terminal 765 to realize the above-mentioned data shift operation to the right.

In the circuit shown in FIG. 4, when the overflow detection signal OVF of the adder 75 becomes Ll 1.11, an overflow may also occur in the calculation result of (y+1) by the increment circuit 83. In this case, the calculation result 2 (
= α + β), and if the product-sum calculation continues as it is, the absolute value of the output data obtained from the accumulator 16 will change as shown in Figure 8 (A), which is completely meaningless. value.

The control circuit 89 and the correction circuits 85 and 87 input the 5 calculation results Z.
When an overflow occurs, the circuit operates to fix the absolute value of the output data to the maximum positive or negative value as shown in Figure 8 (B). It is shown in FIG.

In FIG. 9, the exponent part correction circuit 85 has an input bit L
. -Two-person AND game 1-850 to 85 compatible with L.
3 and two manual OR gates 860 to 863, each bit signal is sent to the accumulator through these gates], 6
Output to the X side. Sign bit of exponent data ■4.
An inverted signal of the overflow detection signal EOVF output from the increment circuit 83 is input to the other input terminal of the AND gate 853 to which the overflow detection signal EOVF is input. A flow detection signal tJNF is input.

Also, A to which data bits r, , ... L2 are input
An inverted signal of the signal UNF is input to the other input terminal of each of the ND gates 1-850-852, and the OR gate 8
A signal EOVF is input to the other input terminals 60 to 862. Signals EOVF and UNF are 14 at the same time.
1.11, the output of the exponent correction circuit 85 is [011] when the signal EOVF is 141 II.
, ) =→-7, making the exponent part the maximum value. Also, when the signal UNF is ia ]-r+, (1,000)
=-8, satisfying the above-mentioned index value of 0-02.

On the other hand, the mantissa correction circuit 87 outputs the sign bits 1-Ll as they are, and the data bits ■, 4-F7 . .

2-man OR gates 871 to 87N and 2-man A
It is designed to be outputted via ND gates 881 to 88N. The other input of each OR game has a control circuit 89.
The output of AND game 1-891 is given, and each A, N
The other input terminal of the D gate is connected to the NAN of the control circuit 89.
The output of D gate 892 is detected. Signal EOV
When F is 1711+, the temporary part data is a positive value, that is, the sign pitch l-I,! .

If is u Opt, the outputs of the AND gate 891 and the NAND gate 892 are both 1″', and the output of the correction circuit 87 is the maximum positive value (011, 1...11.)
Also, if the sign bit LIS is #I I+, the output of the NAND gate 892 will be 7'0''.

The output of the correction circuit 87 is the maximum negative value ciooo...
00]. When the signal EOVF is "ON", these correction circuits 85, 87 output the input data I, C, L+ as they are as data LE'pLM'.

These output data L E"p LM' are cumulative m16
It is output to the A bus 27 via the switch circuit 17 and fed back to the selection circuit 61 of the adder/subtractor 15.

From the above explanation of the operation, it can be seen that in the digital signal processor to which the present invention is applied, the 1 multiplier 14 and the adder/subtractor 185 can each perform floating point operations. Here, X
Data input from path 21 or Y bus 22 to multiplier 14 and from multiplier 1-4 or A bus 27 to adder/subtractor (
When inputting data to AI, U) 15, the number of bits of the input data matches the number of delta pins 1 of the receiving circuit, so as shown in Figures 10 (A) and (B), there is a There is no change in bit position. However, X Pass 25,
Y bus 26. When the 16-bit data from the D bus 20 is taken into the adder/subtractor 15, the number of bits of the mantissa data does not match, so the input selection circuits 60 and 61 of the adder/subtractor input the mantissa data as shown in FIG. 10(C). Department input data M
It requires an operation to add 0" to the lower 4 bits of
In addition, when outputting the 20-bit adder/subtracter output obtained by the accumulator (ACC) 16 to the 16-bit D bus 20, the mantissa part M is output in the switch circuit 17 as shown in FIG. It is necessary to discard the lower 4 bits of data and convert it into data with 4 bits for the exponent and 12 bits for the mantissa.

In the digital signal processor to which the present invention is applied, the input selection circuit 60 performs the data conversion operation described above.
61 and the output switch circuit 17 are further improved so that the processor can also execute fixed-point operations by specifying a 5 program.

The fixed-point data x and y are multiplied by a mantissa data multiplication circuit 57 in the multiplier 4.

In this case, as shown in FIG. 11(A), the upper 12 bits of the 16-bit input data X, Y that enter the mantissa manual registers 53 and 54 are treated as valid data. On the other hand, when adding or subtracting fixed-point data, the shift operation of the shift circuits 69 and 76 in the adder/subtractor 15 is stopped according to a designation in the program, and the operation result of the mantissa part obtained in this state is used. The operation of the shift circuit 69 is stopped when an operation instruction for fixed-point data supplies the numerical value "0" to the data line E in FIG.
The control signal S7 may be generated to select the input from E. The operation of the shift circuit 76 is stopped when the fourth
The numerical value "0" data may be given to the data line F in FIG. 3(B), and the control signal S may be generated so that the selection circuit 82 selects the input from the hth data line F.

In addition and subtraction of the above fixed-point data, multiplication Jl11
4 or the A bus to the adder/subtractor], 57\, as shown in FIG. 11(B), 16-bit 1- data of the mantissa part can be sent in the same way as in the case of floating point arithmetic. Data input from the X path, Y bus, and D bus is
As shown in figure (C), all bits are put into the mantissa, and the accumulator (A
The mantissa data obtained in CC) is as shown in FIG. 11(D).

All bits are output through DX pass 20.

FIG. 12 shows a specific example of the input selection circuit 60 of the adder/subtractor having the bit conversion function described above. In this circuit diagram, P
, -P, , Y, ~Y, , D, -D, respectively, are P bus 24. Each bit of input data from Y bus 2G and D bus 20 is shown.

The indices #p a to P of data P are input to the switch 601, and the four output terminals of the switch 601 are input to the switch 601.
It is connected to terminals C6 to C1 of 03. Each bit of data Y, D] and the bit p<1=p1 of the mantissa part of data P. is input to the switch 602, and the second position of the switch 602]
The 2-bit output terminal is the output line β of the upper bit of data β
7-β4. The output terminals of the lower four bits are connected to terminals 04 to C7 of the switch 603 and the other input terminal of the switch 601. A switch 603 is an output line β of the lower bit of data β. 8 output terminals connected to ~β3 and 4 terminals 6 giving state 110 Fl
04 is a control signal S1. This is a logic circuit that generates drive signals 60A, 60B, 60G for the switches 601, 602, 603+7) based on the signals S, 60A, 60B, 60G.

Control signal S, 1? When the date and night to be selected is indicated, 5
Switches 601 and 602 are operated by signals 60A and 60B, and one of data P, Y, and D is selected.

At this time, if the control signal S instructs floating point arithmetic, the switch 603 connects the output line β. ~β, the terminal C6
-C5, output lines β, ~β.

to terminals C4 to C1 (when input data P is selected) or to terminal 604 (when input data Y or D is selected).

If control signal S2 instructs fixed-point arithmetic,
Output line β regardless of input data. ~β, is connected to the terminal 604, and β, ~β, are connected to the terminals C4 to C7.

FIG. 13 shows a specific circuit configuration of another input selection circuit 61. This circuit is similar to FIG. 12 except that there are two types of inputs, the A bus and the X bus. Explanation will be omitted.

FIG. 14' shows the switch circuit 1 connected to the accumulator 16.
7 shows a specific circuit configuration. In this circuit, the 20-bit output G, ~G, from the accumulator is connected to switch 171.
The 7 switch 171 inputted to the input terminal of the data bus 20 has 16 output terminals connected to each signal line ~D It is controlled by output signals 17A and 17B of 172. When the control signal S according to the program instruction indicates floating point arithmetic, switch 171. is the lower 4 bit signal line on the output side controlled by signal 17B. -D, the human power signal line 00
~ Connect to G3, and connect D0 to D3 for fixed-point arithmetic.
are connected to 64 to 64G.

According to the signal processing processor to which the present invention is applied, not only can the above-mentioned operations be performed on fixed-point data or floating-point data, but also the operation results obtained in floating-point format can be converted into fixed-point format data by program instructions. It is also possible to convert data learned in fixed-point format to floating-point format for performance. This feature is extremely advantageous when the signal processor exchanges data with external devices via the data bus 20 and input interfaces 30-33. External 1 connected to the signal processing processor!
Most of the gongs handle data in fixed-point display format,
This is because, if the floating point arithmetic results of the signal processing processor were to be output as they are, a special device for converting the data format would be required outside the processor.

Conversion from floating point display to fixed point display (hereinafter referred to as F
(referred to as LFX) is performed as follows.

First, the floating point representation data obtained in the accumulator 1.6 is A=αH・2, and the data yi=βH・2 with the value of the mantissa βM=O is stored at a specific address in the data memory 5 or 6. Store it. This AT1/S is made to correspond to the AT1/S part of the FLFX command word.6 Also, when this command word is executed, the selection circuit 8 selects the data y read from the -1- memory.
, to the Y bus 22, the selection circuit 60 selects the input from the Y bus, the selection circuit 61 selects the input from the A bus 27, and the 5 selection circuit 82 outputs the input data F (= ro
”), and the output switch 17 selects the input signal G4~Ga.
Various control signals are generated to connect and operate g to the data bus 20.

If you do this, when you execute the FLFX command, 2
An operation is performed between the two floating point data A and yi, and the accumulator 1.6 has been normalized using a reference value for the base and can be handled as a data bus.

Normally, it is not possible to accurately know the optimal value of βE for the internal calculation result A, so it is better to select the value of βE slightly larger. However, it must be noted that if the value of βE is too large, the precision of the fixed-point data will decrease. When executing FLFX, if the exponent part αE of the calculation result Z becomes larger than the exponent part βE of the conversion data y1 stored in the memory in advance, an overflow of the mantissa part of equation (6) occurs. In this case, the operation of the output correction circuit 80 described above allows the absolute value of the fixed-point data to be fixed at the maximum positive or negative value.

On the other hand, the operation of internally converting data in fixed point representation given from the outside into data in floating point representation can be performed as follows. First, an instruction is executed to transfer the fixed-point data input to the input register 3 to the accumulator 1G. In this command, the 16-bit fixed point display data D given to the selection circuit 60 via the data bus 20 is converted into the mantissa part βA by the operation of the selection circuit 60, and the 1 selection circuit 67, Shift circuit 69. Latch circuit 72. Adder 75. Shift circuit 76, correction circuit 8
7 to the mantissa part 16M of the accumulator 16. In this case, the shift circuits j869 and j76 and the adder 75 are each controlled to allow input data to pass through.

Next, convert from fixed-point display to floating-point display (hereinafter,
FXFI).

When this instruction is executed, the selection circuit 61 selects the accumulator output provided from the A bus 27, that is, the fixed point data A described above, as the output αH2αE.

Further, the 5 selection circuit 160 outputs the conversion data y2 specified by the address field of the FXFL instruction and read out from the memory 5 or 6 to the X bus 26 as an output β.

Select as βE. This conversion data y2 has a reference value in which, for example, the mantissa part β is zero and the exponent part βE is selected from a range of values [+7 to -8]. Unlike when executing other instructions, when executing the FXFL instruction, selection (i[1
62 generates a control signal S4 so that input βE is selected, and the two inputs of comparison circuit 63 are both set to βE. In this case, the board selection circuit 67 selects the input αH, and the selection circuit 68 selects the input βH. Further, the control signal S causes the selection circuit 7o to select the input data E=rO'', thereby suppressing the data shift operation of the rightward shift circuit 69.

As a result of the above control operation, the output of the latch circuit 71.72°73 is γ=βE*eA=(t, and the 8 data e^ and eB that become 8B"O are manually added to the adder 751 and the addition result UN(=CH ), the decimal point position is shifted by 0. bit under the action of the zero detection circuit 79 and the leftward shift i-times i% 76, and the result is expressed by .Data is obtained in the accumulator 16.

This formula shows that the data A-αN in fixed-point representation is the exponent βε
This means that each is normalized to a standard and displayed as a floating point number. Therefore, by using the data obtained by the accumulator 16 with the instruction F X F L, subsequent calculations can be performed in floating point format.

In this embodiment, the FXFL instruction is executed after setting the data in the input register 31 to the accumulator 16.
Fixed-point input data and conversion data y2 are transferred to X bus 2.
By inputting data to the adder/subtractor 15 using the D bus 20 and the D bus 20, the data can be converted to floating point representation with one instruction.

As described above, the digital signal processor to which the present invention is applied can handle fixed-point and floating-point image format data, and when an underflow occurs in the exponent part during normalization of floating-point display data, Since the normalization operation can be performed with the exponent value fixed to the minimum value, the calculation method can be automatically switched to floating-point calculation format when the internal calculation data value is large, and fixed-point calculation format when it is small. An extremely wide dynamic range can be obtained.

In other words, when the internal data of the adder/subtractor consists of 16 bits h for the mantissa part and 4 bits for jM number part as in the device of the embodiment, the numerical value in the range of exponent part γ [(-7 to -.8] can be expressed in two's complement notation. If all operations are processed in floating point format, the dynamic range will be 2-1 to 27, as shown by the diagonal lines in Figure 15, which is equivalent to 15 bits when converted to a pitch number of 4''. According to the present invention, when the normalized number of bits O for the mantissa of calculation data is in the range of (γ-θ) -8, the exponent LE after normalization is fixed to -8. It is designed to switch to decimal point calculation.Therefore, as shown in FIG. 15.

The dynamic range is 31 bits in total, fixed,
The range of numerical values that can be handled is significantly expanded compared to when only one type of floating is used.

In actual applications of digital signal processing processors, for example, as shown in the following equation, m times of product-sum operations are often repeated.

In the case of such operations, according to the processor to which the present invention is applied, data processing efficiency is improved by pipeline control that allows multiplication and addition/subtraction operations to proceed in parallel, making it possible to perform operations at variable speeds.

FIG. 16 is a time chart showing an example of parallel operation. In accordance with the instruction A fetched in advance in the instruction cycle 201, data is read from the data memory in the next cycle 202 and arithmetic operations are performed by the multiplier. In instruction cycle 203, addition and subtraction are performed between the multiplication result and the data (A bus output) of the accumulator, and the operation result is output to the accumulator in cycle 204.

The operations of these four steps are repeated in each instruction cycle with a one-step shift, and when the product-sum operation has been completed a predetermined number of times m, the operation result T is transferred to the data bus by instruction F.
0 and sent to the data memory 5 or external circuit.

The parallel operation of the processor by pipeline control is achieved by connecting the multiplier 14 and the adder/subtractor 15 in parallel, and by connecting the multiplier 14 and the adder/subtractor 15 in parallel. This is possible by arranging latch circuits 71 and 72 (corresponding to this in FIG. 4).

FIG. 17 shows an application example of the above-mentioned digital signal processing processor.
00 and a D/A converter 301 to connect to an analog line and function as a digital filter.

FIG. 18 shows a combination of the digital signal processor 100 and another data processing device 1011, such as a microcomputer MC86800 manufactured by Hitachi, Ltd.
A system configuration is shown in which data is exchanged via ll-D7 and data processing can be shared between two devices. This system configuration is suitable for applying the signal processor 100 to a communication line modem, an echo canceller, or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the overall configuration of a digital signal processor to which the present invention is applied, FIG. 2 is a diagram showing the detailed configuration of the multiplier 14, and FIGS. 3(A) and (B) 4 (A) and (B) are diagrams for explaining the bit format of the input data and the internal operation data of the adder 15, respectively.
) are diagrams showing the detailed configuration of the adder/subtractor 15 according to the embodiment of the present invention, FIGS. 5(A), (B) and FIGS. 6(A, ), (B
) is a diagram for explaining the operation of the shift circuit 76, FIG. 7 is a circuit diagram showing one embodiment of the shift circuit 76, and FIG.
), CB) are explanatory diagrams about data overflow,
Fig. 9 is a diagram showing a specific circuit configuration of the 14 parts 85°87.89 of the output correction circuit, and Figs. 0(A) to (D) show changes in floating point data in each part of the signal processing processor. A diagram showing the situation. 11(A) to (D) are diagrams showing changes in fixed-point data, FIG. 12 is a diagram showing a specific circuit configuration of the input selection circuit 60, and FIG. 13 is a diagram showing a specific circuit configuration of the input selection circuit 61. FIG. 14 is a diagram showing the circuit configuration of the output switch circuit 17.
15 is a diagram showing the dynamic range of the digital signal processing processor to which the present invention is applied; FIG. 16 is a time chart for explaining the characteristics of the operation of the processor; Figure 17 and 1st
FIG. 8 is a diagram showing a typical usage pattern of the above-mentioned signal processing processor. 2nd figure 4th figure (A) 4th figure early figure 10) Prisoner episode ■ Katana Ata~e・ [Tosha stop Jn-Kan Issen! , ToZs Buzu Jukou■Overwhelm■Rota-C・CB) Kuchishikasumi Sword Prisoner 7■''-Mema~. , c4 0I possible 7TZII Kano Kano - 匝~Ci fig. g, 411t7>l rule" (Rijin (7 anti + 111 - Hare flow stone 1 positive r6 i 1flB and 7110; It thousand?
Monthly soldier 1t! Figure 75

Claims (1)

[Scope of Claims] An addition/subtraction device that performs addition or subtraction of one or two floating point data, the first data pair consisting of the first and second floating point data, and the third and fourth floating point data. means for selectively selecting a second data pair consisting of decimal point data; means for performing addition/subtraction of the two data of the first data pair; and converting the third floating point data into fixed point data. and means for converting the third floating point data into fixed point data in response to the fourth floating point data. 2. The fourth floating point data above has a mantissa value of 0.
2. The addition/subtraction device according to claim 1, wherein the value of the exponent part is larger than the value of the exponent part of the third floating point data. 3. The fixed point data obtained by the above conversion is characterized in that the value of the mantissa part is obtained by normalizing the third floating point data in response to the value of the exponent part of the fourth floating point data. An addition/subtraction device according to claim 1 or 2.