JPH0357487B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an addition/subtraction device, which can be incorporated into, for example, a digital signal processor to realize a high-speed, high-precision product-sum calculation function that can process data such as audio and images in real time. Useful.

Applications of signal processing processors that can process digitized signals in real time are used in voice synthesis or analysis equipment, or in equipment such as modems, digital filters, codecs, and echo cancellers in the communications field. is being considered.

This signal processing processor is provided as an LSI with built-in program memory and dedicated multipliers and adders/subtractors for processing data at high speed, and can be adapted to various uses by changing the program.

When the above-mentioned signal processor is used, for example, for filter processing of an audio signal, the internal calculation data becomes a relatively large amplitude of 16 to 28 bits due to the product-sum calculation. For this reason, if the structure of the multiplier or adder/subtractor is a fixed-point data calculation type, the hardware scale will increase exponentially as the number of bits of calculation data increases, making it difficult to implement on an LSI. This problem can be solved by configuring the processor to operate on floating point data. However, if the multiplier and the adder/subtractor are connected by a data bus,
If we were to adopt the data processing method of conventional general-purpose computers, in which each device performs floating-point operations independently, the multiply-accumulate operation, which is the basic operation of a signal processing processor, would take time, making real-time processing of signals difficult. becomes.

The object of the present invention is to provide a signal with a new structure that is suitable for LSI implementation, can be used regardless of whether the data to be added/subtracted is floating point or fixed point, and can process digital signals at high speed in real time. An object of the present invention is to provide an addition/subtraction device useful for processing processors and the like.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a digital signal processor to which the present invention is applied, in which 1 is a memory for storing programs, 2 is a program counter for instructing the read address of the program memory 1, and 3 is the program memory. An instruction register 1 is connected to the instruction register 3, and a control circuit 4 generates various control signals S for operating the processor from the instruction word read into the instruction register 3. In this embodiment, the instruction word stored in the memory 1 is, for example,
It consists of 22 bits, each containing an operation code, data, address, or address control information. The program counter 2 and instruction register are connected to a 16-bit data bus (D bus) 20.

5 and 6 are memories for storing data, and 7 is a general-purpose register. One of the memories 5, 6 can be a random access memory (RAM) and the other can be a read only memory (ROM). In addition, each memory consists of multiple small-capacity ROMs.
Alternatively, it may be a complex of ROMs. The memory stores 16-bit data, and each data is read out to the 16-bit X bus 21 or Y bus 22 via the selection circuit 8. Registers 9 and 10 designate lower addresses of the data memories 5 and 7, respectively, and registers 11 and 12 designate upper addresses of the memories. Furthermore, register 11
gives the upper address of the data to be read to the X bus 21, and the register 12 gives the upper address of the data to read to the Y bus 22 or the address of the general-purpose register 7, and these registers receive the data from the instruction register 3. Address information is provided via bus 23.

14 is a floating point multiplier that calculates the product of two data given from the X bus and the Y bus 22 and outputs the result to the P bus 24. This multiplier has two inputs as described later. Contains registers to hold data X, Y, and is not operated on 2
The two data X and Y are output as they are to the X bus 25 and Y bus 26.

Reference numeral 15 denotes a floating-point operation type adder/subtractor, which performs calculations using the output data X, Y, P of the multiplier 14 and the data D, A of the data buses 20, 27 as input, and sends the result to the accumulator 16. Output.
17 is a switch circuit that outputs the floating point data latched in the accumulator 16 to a 20-bit data bus (A bus) 27, and also converts the above data into 16-bit data and outputs it to the D bus 20;
Reference numeral 18 denotes a status codeless register connected to the multiplier 14 and adder/subtractor 15 and storing status codes related to the results of these operations.

30 is an output register for outputting 16-bit data on the data bus 20 in parallel to external terminals _D0 to _D15 , and 31 is for capturing 16-bit data from the external terminals to the data bus 20 in parallel. is the input register of Further, 32 is a 16-bit shift register for taking in serial input data from the terminal SI in synchronization with the input clock of the terminal SICK while the input pulse of the terminal SIEN is "1", and 33 is the input pulse of the terminal SOEN. This shows a 16-bit shift register for serially outputting data to the terminal SO in synchronization with the input clock of the terminal SOCK during the period when is "1". These two shift registers are each connected in parallel with the data bus 20 for 16 bits.

35 is a register that controls the operating state of the processor; 36 is a counter that is set to the number of repetitions when a repeat instruction causes the processor to repeatedly execute a certain instruction; and 37 is a status register that indicates the internal state of the processor. .
The contents of the registers 35 and 37 can be written and read from the outside via the data bus 20 and terminals _D0 to _D15 , respectively.

40 is a control circuit for controlling interrupts to processor operations and input/output operations;
The shift registers 32 and 33 are enabled at the rising edge of the SIEN and SOEN input signals, interrupt the program at the falling edge of each signal, and the registers 30 and 33 are enabled at the rising edge of the input/output signal to the terminal IE.
31 and interrupts the program at the falling edge of the signal. 41 is a function control circuit that controls the processor operation according to signals from an external control device (for example, a microcomputer); for example, a DMA transfer mode acknowledgment signal is sent from the terminal TXAK, and a parallel input/output data A signal indicating the transfer direction, a signal indicating that this processor has been selected by an external device from terminal CS,
Test operation mode specification signal from terminal TEST,
Receives a reset signal from RST and an operation control signal from an external device from terminals F _0-3 , respectively.
Outputs parallel data transfer request signal from TxRQ.
The terminal Bit I/O indicates a bidirectional input/output terminal for inputting and outputting data one bit at a time. 42 is a clock pulse generation circuit, which receives a basic clock from an external circuit via the terminal OSC, generates various internal clocks necessary for processor operation based on this, and also outputs the internal and external clocks of the processor to the terminal SYNC. Outputs the clock for system synchronization.

Next, according to FIGS. 2, 3, and 4, the multiplier 14
The adder/subtractor 15 will be further explained.

The multiplier 14 has an X bus 2 as shown in FIG.
1, 16-bit data of Y bus 22 is input. These data are given from memories 5 and 6, general register 7, or data bus 20. As shown in Figure 3A, these data have the exponent part in the lower 4 bits and the mantissa part in the upper 12 bits, and the most significant bits of each part shown with diagonal lines, that is, 2 ³ and 2 ¹⁵ . The bit in this position is the sign bit. Also, the decimal points are 2 ¹⁵ and 2 ¹⁴
It is between. As shown in FIG. 2, the exponent data and mantissa data given from the X bus 21 and Y bus 22 are held in registers 51, 52, 53 and 54, respectively, and the exponent data in registers 51 and 52 are added together. The sum is added by the circuit 55 and output to the P bus 24 via the 4-bit output register 56. On the other hand, the mantissa data of the registers 53 and 54 are input to a multiplication circuit 57 having a circuit configuration similar to that of normal fixed-point arithmetic, and the multiplication result is sent to the P bus 24 via the output register 58. Output. That is, the calculation output of the multiplier 14 is input to the adder/subtractor 15 as 20-bit data consisting of the lower 4 bits of the exponent part and the higher 16 bits of the mantissa part, as shown in FIG. 3B. still,
The outputs of registers 52 and 54 are sent to the X bus 25, and the outputs of registers 51 and 53 are sent to the Y bus 26, and each is sent to the adder/subtractor 1 as 16-bit data.
given to 5.

FIGS. 4A and 4B show the configuration of an adder/subtractor 15 according to an embodiment of the present invention. As shown in FIG _. 4A, data D, P, be done. Further, the data A and X are input to the selection circuit 61, and one data designated by the control signal _S2 is selected. Here, the input data D, X, and Y are shown in Figure 3A, respectively.
It is 16 bit data. As will be described later, when these 16-bit data are specified, the selection circuits 60 and 61 select these data as shown in FIG. 3B.
The configuration is such that it is converted to 20-bit data and output. This bit conversion is performed on input data D, X, Y
differs depending on whether fixed-point data or floating-point data, and the conversion operation is specified by control signal _S3 . This allows the floating-point type adder/subtractor to process input data in fixed-point representation. In addition, the control signals S ₁ , S ₂ , S ₃ ...Sn
is output from the control circuit 4 in response to the instruction word in the program.

The output data from the selection circuit 60 is β (exponential part β _E ,
the mantissa part β _M ), and the output data from the selection circuit 61 as α
(Exponent part α _E , mantissa part α _M ), the exponent part data α _E is inputted to the comparison circuit 63 via the selection circuit 62, and is compared in magnitude with the exponent part data β _E. Moreover, these exponent part data α _E and β _E are respectively input to the subtraction circuit 6
4 and is also input to the selection circuit 65. The mantissa data α _M is passed through a negation circuit 66 to a selection circuit 67,
68, and the mantissa data β _M is directly input to selection circuits 67 and 68. Negate circuit 66
In the case of this embodiment, is provided to realize the subtraction of data α and β by the ALU 75 having an adder configuration, and in the case of an addition operation, data α _M passes through the negation circuit. The selection circuits 65, 67, and 68 each select one of the two inputs according to the output signal of the comparison circuit 63. The output of the selection circuit 65 is latched by a latch circuit 71, the output of the selection circuit 67 is latched by a latch circuit 72 via a shift circuit 69, and the output of the selection circuit 68 is latched by a latch circuit 73 by a timing signal C. The subtraction circuit 64 is also controlled by the output of the comparison circuit 63, and operates to subtract the smaller one of the inputs α _E and β _E from the larger one according to the comparison result.
The shift circuit 69 shifts the input data to the right by the number of bits corresponding to the output of the subtraction circuit 64 obtained via the selection circuit 70. The operation of the shift circuit 69 can also be controlled by another data E input to the selection circuit 70, and the number of shift bits is selected by the control signal _S7 .

As shown in FIG. 4B, the outputs e _A and e _B of the latch circuits 72 and 73 are input to a fixed-point arithmetic type adder (ALU) 75 operated by the control signal S _B , and the addition result U _M is The signal is applied to a leftward shift circuit 76.
On the other hand, the output γ of the latch circuit 71 is
7 and one input terminal of the subtraction circuit 78. 79 is a zero detection circuit that determines the output U _M of the adder 75, and when the output U _M of the adder given in complement representation is a positive number, "0" following the sign bit at the top of U _M is detected. ”Count the number of consecutive bits. If U _M is a negative number, count the number of consecutive "1" bits following the sign bit. The output θ ₁ of the zero detection circuit 79 is applied to the shift circuit 76 via an output correction circuit 80 provided for data normalization and overflow prevention, and determines the number of bits to shift data by this shift circuit. The output θ ₁ of the zero detection circuit 79 is also input to the other input terminal of the subtraction circuit 78, and the output U _E of this subtraction circuit is input to the output correction circuit 80.
It is input to the exponent part 16X of the accumulator 16 via. The mantissa part 16M of the accumulator 16 includes the shift circuit 7 corrected by the output correction circuit 80.
The output data L _M ' from 6 is input.

The output correction circuit 80 outputs the overflow detection signal OVF output from the adder 75 and the subtraction circuit 78.
The output θ ₁ of the zero detection circuit 79 and the constant addition circuit 7 according to the underflow detection signal UNF output from the
A selection circuit 81 for selecting one of the outputs θ ₂ and 7
and a selection circuit 82 which supplies either the output of the selection circuit 81 or the data F given by the program as a shift bit number instruction signal θ to the shift circuit 76 in response to a control signal _S3 by the program, and an overflow signal OVF. An increment circuit 83 which adds 1 to the subtraction circuit output U _E when it is "1" and outputs a signal EOVF when the addition result L _E also overflows, and an exponent of the increment circuit 83 and the accumulator 16. an exponent part correction circuit 85 inserted between the exponent part 16X, a mantissa part correction circuit 87 inserted between the shift circuit 76 and the mantissa part 16M of the accumulator 16, and the two correction circuits 8
It consists of a control circuit 89 that controls the operations of 5 and 87 in accordance with signals UNF and EOVF.

The adder/subtractor 15 having the above configuration operates as follows.

Two input selection circuits 61, 6 shown in FIG. 4A
The respective outputs α and β of 0 are floating point data, and their values are expressed by the following equation.

α=α _M・2〓 ^E β=β _M・2〓 ^E …(1) Now, suppose we are performing an addition operation on two data α and β that have the relationship α _E > β _E , then the addition result Z
is given by Z=α _M・2〓 ^E +β _M・2〓 ^E = [α _M +β _M・2 ^-( 〓 ^E- 〓 ^E) ]・2〓 ^E …(2).

The comparison circuit 63 compares the magnitudes of α _E and β _E , causes the selection circuit 65 to select the larger exponent part data α _E , and causes the selection circuit 67 to select the mantissa data corresponding to the smaller exponent part β _E. The selection circuit 6 selects data β _M.
8 selects the mantissa data α _M corresponding to the larger exponent part α _E , and a control signal is given to the subtraction circuit 64 to subtract the smaller exponent β _E from the larger exponent α _E. During execution of the addition operation, the selection circuit 70 selects the output (α _E - β _E ) from the subtraction circuit 64, and the shift circuit 69 selects the output β _M from the selection circuit 67 (α _E - β _E ). Just the bits to the right (toward the lower bits)
It operates to shift to. As a result, the respective outputs of the latch circuits 71, 72, 73 are γ=α _E , e _A =
β _M ·2 ⁻⁽ 〓 ^E− 〓 ^E) , e _B = α _M , and the output U _M of the adder 75 that has performed the operation of e _A +e _B represents the mantissa part of equation (1). Therefore, the calculated value Z at this stage is expressed by the following equation.

Z= _UM ·2〓 (3) The zero detection circuit 79 and the leftward shift circuit 76 are for normalizing the adder output _UM so that its absolute value becomes the maximum. As shown in FIG. 5A, the zero detection circuit 79 detects the number θ ₁ of consecutive 0s (below the decimal point) following the sign bit of the data U _M , and the shift circuit 76 converts the data U _M to θ ₁ By shifting just one bit to the left (toward the most significant bit), mantissa data L _M with the maximum absolute value can be obtained. If U _M is a negative number, it is only necessary to shift by the number of consecutive "1"s as shown in FIG. 5B. In this case, for the exponent part data γ, the subtraction circuit 78 performs the calculation (γ−θ ₁ ), and the output U _E
Let be the normalized index value. If no overflow occurs in the data U _M , the output L _E of the increment circuit 83 is the normalized exponent value U _E
The normalization process can be expressed by the following equation.

Z=[U _M・2〓 ¹ ]・2 ⁽ 〓 ^- 〓 ¹⁾ =L _M・2 ^LE …(4) If the size of γ in the exponent part is 4 bits, γ can be expressed by two's complement representation. The value that can be expressed is [+7γ
-8]. Therefore, when normalizing the mantissa data, if you try to completely shift the data U _M to the left by the value θ ₁ detected by the zero detection circuit, the value of (γ − θ ₁ ) on the exponent part will be −8. , which may cause an underflow in the subtraction circuit. At this time, a signal (borrow signal) UNF indicating data underflow is generated from the subtraction circuit 78 that performs the calculation of (γ-θ ₁ ). Fourth
In the circuit of Figure B, when the above signal UNF is generated,
The selection circuit 81 replaces the input θ ₁ with the constant addition circuit 77
The constant addition circuit 77 selects the output θ _{2 of}
It is configured to output as . In this way, for example, when the value of γ is "-5", the value of θ ₂ is "3", so the number of shift bits of the mantissa data U _M is limited to 3 bits, and after normalization of the exponent part, The value remains at the minimum value "-8". The operation to set the exponent part to "-8" when the signal UNF occurs will be performed later in the 9th step.
This is performed by an exponent part correction circuit 85, which will be explained in the figure.

If an overflow occurs in the calculation result U _M of the adder 75 as shown in Figures 6A and B, the true sign of the data appears in the carry output, and the most significant bit of the numerical value appears in the sign bit position. There is.
Therefore, in this case, the overflow detection signal
By OVF, selection circuit 81 and zero detection circuit 79
, the shift circuit 76 is caused to shift right by 1 bit, and the increment circuit 83 is caused to shift to the right by 1 bit.
It is sufficient to perform the operation of U _E (=γ)+1 and manipulate the data Z as shown in the following equation.

Z=[U _M ·2 ⁻¹ ]·2 ⁽ 〓 ⁺¹⁾ (5) An example of the shift circuit 76 that performs the above operation is shown in FIG. This circuit consists of an 8-bit shifter 761, a 4-bit shifter 762, a 2-bit shift 763, and a 1-bit shifter 764, each corresponding to each bit θ ₃ to _{θ 0} of the shift bit number instruction data θ. The switches SW ₃ to _{SW 0} of the signal line are connected to the contacts on the lower bit side when the corresponding control bits θ ₃ to θ ₀ are “1”.
In addition, each switch SW ₀ of the 1-bit shifter 764
is connected to the contact on the upper bit side when the overflow detection signal OVF is "1", and the output line _L13 of the sign bit is connected to the carry signal input terminal 765, realizing the above-mentioned 1-bit right shift operation of the data. .

In the circuit shown in FIG. 4, when the overflow detection signal OVF of the adder 75 becomes "1", an overflow may also occur in the calculation result of (γ+1) by the increment circuit 83. In this case, it means that an overflow has occurred in the calculation result Z (= α + β), and if the product-sum calculation continues as it is, the absolute value of the output data obtained from the accumulator 16 will be as shown in FIG. 8A. It changes and becomes a completely meaningless value.

The control circuit 89 and the correction circuits 85 and 87 are circuits that operate to fix the absolute value of the output data to the maximum positive or negative value, as shown in FIG. 8B, when the above-mentioned overflow occurs in the calculation result Z. can be,
A specific example of the configuration is shown in FIG.

In FIG. 9, the exponent part correction circuit 85 includes a two-input AND gate 85 corresponding to input bits _L0 to _L3 .
0 to 853 and two-input OR gates 860 to 863, and each bit signal is outputted to the accumulator 16X via these gates. The inverted signal of the overflow detection signal OVF output from the increment circuit ₈₃ is input to the other input terminal of the AND gate 853 to which the sign bit L3 of the exponent part data is input, and the other input terminal of the OR gate 863 is input. An underflow detection signal UNF from the subtraction circuit 78 is input. Also, AND gates 850 to 8 to which data bits L ₀ to _{L 2} are input
The other input terminal of each of 52 is connected to the signal UNF.
The inverted signal of
The signal EOVF is input to the other input terminal of 2. Since the signals EOVF and UNF cannot become "1" at the same time, the output of the exponent correction circuit 85 is
When the signal EOVF is "1", [0111]=+7, making the exponent part the maximum value. Also, when the signal UNF is "1", [1000] = -8, and the aforementioned θ = θ ₂
Satisfies the index value when .

On the other hand, the mantissa correction circuit 87
Outputs _L19 as is, and outputs data bits _L4 to _L18 to 2-input OR gates 871 to 87N, 2-inputs, respectively.
It is configured to output via AND gates 881 to 88N. The output of the AND gate 891 of the control circuit 89 is given to the other input of each OR gate, and the output of the NAND gate 892 of the control circuit 89 is given to the other input terminal of each AND gate. When the signal EOVF is “1”, the mantissa data is a positive value, that is, the sign bit _L19 is “0”.
Then AND gate 891 and NAND gate 892
Both outputs become "1", and the output of the correction circuit 87 becomes the maximum positive value [0111...11]. Also, if the sign bit _L19 is “1”, the NAND gate 892
Since the output of the correction circuit 87 becomes "0", the output of the correction circuit 87 becomes the negative maximum value [1000...00]. Signal EOVF
When is "0", these correction circuits 85 and 87 output the input data L _E and L _M as they are as data L _E ' and L _M '. These output data L _E ′, L _M ′ are sent to the A bus 2 via an accumulator 16 and a switch circuit 17.
7 and fed back to the selection circuit 61 of the adder/subtractor 15.

From the above description of the operation, it can be seen that in the digital signal processor to which the present invention is applied, the multiplier 14 and the adder/subtractor 15 can each perform floating point operations. Here, data input from the X bus 21 or Y bus 22 to the multiplier 14 and data input from the multiplier 14 or A bus 27 to the adder/subtractor (ALU) 15 are based on the number of bits of the input data and the data of the receiving circuit. Since the number of bits matches, the first
As shown in Figures A and B, there is no change in bit position between data. However, when the 16-bit data from the X bus 25, Y bus 26, and D bus 20 is taken into the adder/subtractor 15, the number of bits of the mantissa data does not match. As shown in FIG. 10C, it is necessary to add "0" to the lower 4 bits of the mantissa input data M. Also, the accumulator (ACC)
When outputting the 20-bit adder/subtractor output obtained in step 16 to the 16-bit D bus 20, the lower 4 bits of the mantissa M are discarded in the switch circuit 17 as shown in FIG. part 4 bits,
Requires an operation to convert the mantissa to 12-bit data.

The digital signal processing processor to which the present invention is applied includes input selection circuits 60 and 61 and an output switch circuit 17 that perform the above-described data conversion operation.
This has been further improved so that the processor can also perform fixed-point operations according to program specifications.

Multiplication of fixed point data X and Y is performed in a mantissa data multiplication circuit 57 within the multiplier 14. In this case, as shown in FIG. 11A, the mantissa input register 5 of the 16-bit input data
The upper 12 bits of bits 3 and 54 are treated as valid data. On the other hand, when adding or subtracting fixed-point data, the shift operations of the shift circuits 69 and 76 in the adder/subtractor 15 are stopped according to a designation in the program, and the operation result of the mantissa part obtained in this state is used. The operation of the shift circuit 69 is stopped by controlling the fixed-point data arithmetic instruction to give the numerical value "0" to the data line E in FIG. 4A, and the selection circuit 70 to select the input from the data line E. The signal _S7 may be generated. To stop the operation of the shift circuit 76, a numerical value "0" is given to the data line F in FIG. 4B, and a control signal _S3 is generated so that the selection circuit 82 selects the input from the data line F. do it.

In addition and subtraction of the above fixed-point data, the data input from the multiplier 14 or the A bus to the adder/subtractor 15 is as shown in FIG. Bye. Data input from the X bus, Y bus, and D bus puts all bits into the mantissa part as shown in Figure 11C, and the mantissa data obtained by the accumulator (ACC) is shown in Figure 11D. Thus, all bits are output to the D bus 20.

FIG. 12 shows a specific example of an input selection circuit 60 for an adder/subtractor having the above-mentioned bit conversion function. In this circuit diagram, P ₀ to P ₁₉ , Y ₀ to _{Y 15} , and D ₀ to D ₁₅ represent each bit of input data from the P bus 24, Y bus 26, and D bus 20, respectively. The exponent parts P ₀ to _{P 3} of P are input to the switch 601, and the four output terminals of the switch 601 are connected to the terminals C ₀ to C ₃ of the switch 603. Data Y,
Each bit of D and the mantissa bit _P4 of data P
P ₁₉ is input to switch 602, and switch 60
The output terminals of the upper 12 bits of the data β are connected to the output lines β ₈ to _{β 19} of the upper bits of the data β, and the output terminals of the lower 4 bits are connected to the terminals C ₄ to C ₇ of the switch 603 and the other input terminal of the switch 601. It is connected to the. The switch 603 has eight output terminals connected to the output lines β ₀ -β ₈ of the lower bits of the data β, and four terminals 604 that give the state "0". 605 is based on control signals S ₁ and S ₃ given from the control circuit 4 according to command words of the program.
Drive signal 60 for switches 601, 602, 603
This is a logic circuit that generates A, 60B, and 60C.

When data to be selected is specified by the control signal _S1 , the switch 60 is activated by the signals 60A and 60B.
1, 602 operates, and either data P, Y, or D is selected. At this time, if the control signal _S3 instructs floating point arithmetic, the switch 603
connects output lines β ₀ to _{β 3} to terminals C ₀ to C ₃ , and connects output lines β ₀ to _{β 7} to terminals C 0 to C 3.
to the terminals C ₄ to C ₇ (when input data P is selected) or to the terminal 604 (when input data Y or D is selected).
If the control signal S ₂ indicates fixed-point arithmetic, the output lines β ₀ to _{β 3} will be connected to terminal 6 regardless of the input data.
04, β ₄ to β ₇ are connected to terminals C ₄ to C ₇ .

FIG. 13 shows a specific circuit configuration of another input selection circuit 61. This circuit is the 12th circuit, except that there are two types of inputs: A bus and X bus.
It is the same as the figure, and the explanation will be omitted.

FIG. 14 shows a specific circuit configuration of the switch circuit 17 connected to the accumulator 16. In this circuit, the 20-bit output G ₀ -G ₁₉ from the accumulator is input to the input terminal of switch 171. The switch 171 connects each signal line D ₀ to _{D 15} of the data bus 20.
The connection between the input terminal and the output terminal is the output signal 1 of the logic circuit 172.
Controlled by 7A and 17B. When the control signal _S3 according to the program command indicates floating point arithmetic, the switch 171 is controlled by the signal 17B to connect the lower 4 bits of the output side signal lines D0 _{to D3 to} the input signal lines G0 _{to D3} .
Connect with G ₃ and D ₀ to D ₃ for fixed-point arithmetic
Connect to G ₄ ~ G ₇ . Signal 17A controls output of upper bit data to data bus 20.

According to the signal processing processor to which the present invention is applied, it is not only possible to perform operations on fixed-point data or floating-point data as described above, but also to convert the operation results obtained in floating-point format into fixed-point format data according to program instructions. It is also possible to convert data given in fixed-point format to floating-point format and perform calculations on it. This feature is extremely convenient when the signal processor exchanges data with external devices via the data bus 20 and input/output interfaces 30-33. This is because many of the external devices connected to the signal processing processor handle data in a fixed-point display format, and if the floating-point calculation results of the signal processing processor were to be output as they are, the data would be stored outside the processor. This is because a special device is required to convert the format.

Conversion from floating point representation to fixed point representation (hereinafter referred to as FLFX) is performed as follows.

First, when the floating point representation data obtained in the accumulator 16 is A=α _M・2〓 ^E , the exponent part satisfies the relationship α _E < β _E and the value of the mantissa part β _M = 0. The data y ₁ =β _M ·2〓 ^E is stored at a specific address in the data memory 5 or 6. This address is made to correspond to the address part of the FLFX instruction word. Furthermore, when this instruction word is executed, the selection circuit 8 outputs the data _y1 read from the memory to the Y bus 22, and the selection circuit 60
selects the input from the Y bus, and the selection circuit 61
selects the input from the A bus 27, and the selection circuit 82
selects the input data F (="0"), and generates various control signals so that the output switch 17 connects the input signals G ₄ to _{G 19} to the data bus 20.

By doing this, when the FLFX instruction is executed, an operation will be performed between the two floating point data A and _y1 , and the accumulator 16 will have Z=A+ _y1 =[0+α _M・2 ^{- (} 〓 ^E- 〓 ^E) 〕・2〓 ^E …(6) is obtained. This data is normalized using ^2〓E as the reference value of the exponent part, and the data bus 2
The mantissa data α _M ·2 ⁻⁽ 〓 ^E− 〓 ^E) output as 0 can be handled as fixed-point data.

Normally, it is not possible to accurately know the optimal value of β _E for the internal calculation result A, so it is better to select a slightly larger value for β _E. However, it must be noted that if the value of β _E is made too large, the precision of fixed-decimal data will decrease. When executing FLFX above, if the exponent part α _E of the calculation result Z becomes larger than the exponent part β _E of the conversion data y ₁ stored in the memory in advance, the mantissa part of equation (6) overflows. will occur. In this case, the operation of the output correction circuit 80 described above allows the absolute value of the fixed-point data to be fixed at the maximum positive or negative value.

On the other hand, the operation of internally converting data in fixed point representation given from the outside into data in floating point representation can be performed as follows. First, an instruction to transfer fixed-point data input to the input register 31 to the accumulator 16 is executed. In this command,
The 16-bit fixed-point display data D supplied to the selection circuit 60 via the data bus 20 is converted into a mantissa part β _M by the operation of the selection circuit 60, and then sent to the selection circuit 67, shift circuit 69, and latch circuit. 72, the adder 75, the shift circuit 76, and the correction circuit 87 to input the mantissa part 16M of the accumulator 16. In this case, the shift circuits 69, 76 and adder 75 are each controlled to allow input data to pass through.

Next, execute an instruction to convert from fixed-point representation to floating-point representation (hereinafter referred to as FXFL). When this instruction is executed, the selection circuit 61 selects the accumulator output provided from the A bus 27, that is, the fixed point data A described above, as the outputs α _M and β _E.
Further, the selection circuit 60 selects the memory 5 or 6 from the y bus 26 specified by the address part of the FXFL instruction.
The conversion data y ₂ read out is selected as the outputs β _M and β _E. This conversion data y ₂ has, for example, a mantissa part β _M of zero and an exponent part β _E selected from a range of values [+7 to -8] and has a certain reference value. Unlike when executing other instructions, when executing the FXFL instruction, the selection circuit 62 generates a control signal S ₄ to select the input β _E , and both inputs of the comparison circuit 63 are set to β _E. In this case, the mantissa selection circuit 67 inputs α _M as
The selection circuit 68 selects the input β _M. In addition, input data _E =
"0" is selected to suppress the data shift operation of the rightward shift circuit 69.

By the above control operation, the latch circuits 71, 72,
The outputs of 73 are γ=β _E , e _A =α _M , and e _B =0. Data e _A and e _B are input to adder 75 and the addition result is
The decimal point position of U _M (=α _M ) moves by θ ₁ bit under the operation of the zero detection circuit 79 and the leftward shift circuit 76, and as a result, Z = [α _M・2〓 ¹ ]・2 ⁽ 〓 ^E- 〓 ¹⁾ …(7) Data is available to accumulator 16.
This formula means that data A=α _M in fixed point representation is normalized based on the exponent β _E and is represented in floating point. Therefore, by using the above data obtained by the accumulator 16 with the instruction FXFL, subsequent calculations can be performed in floating point format.

In this embodiment, the FXFL instruction is executed after the data in the input register 31 is set in the accumulator 16, but the fixed-point input data and conversion data _y2 are transferred using the X bus 25 and the D bus 20. By inputting the data into the adder/subtractor 15, the data can be converted to floating point representation with one instruction.

As mentioned above, the digital signal processor to which the present invention is applied can handle data in both fixed point and floating point formats, and when normalizing floating point display data, underflow occurs in the exponent part. When the exponent value is fixed to the minimum value, normalization operation can be performed, so the calculation method can be automatically switched to floating point calculation format if the internal calculation data value is large, and fixed point calculation format if it is small. This allows an extremely wide dynamic range to be obtained.

That is, when the internal data of the adder/subtractor consists of a mantissa part of 16 bits and an exponent part of 4 bits as in the device of the embodiment, the exponent part γ [+7 to -8] is expressed in two's complement notation.
Can handle numbers in the range. If all operations are processed in floating point format, the dynamic range will be 2 ^-8 to 2 ⁷ , which is shown with diagonal lines in Figure 15.
This corresponds to 15 bits when converted to the number of bits. According to the present invention, when the normalized number of bits θ for the mantissa part of the calculation data is in the range of (γ-θ)<-8, by fixing the normalized exponent L _E to -8, It is now possible to switch to fixed-point arithmetic. Therefore, as shown in FIG. 15, the dynamic range is 31 bits in total, and the range of numerical values that can be handled is significantly expanded compared to when only fixed or floating is used.

In actual applications of digital signal processing processors, for example, as shown in the following equation, m product-sum operations are often repeated.

T= _n 〓 ⁱ⁼¹ ai×bi …(8) In the case of such an operation, according to the processor to which the present invention is applied, the data is Processing efficiency is improved and calculations can be performed at the conversion level.

FIG. 16 is a time chart showing an example of parallel operation. In the next cycle 202, data is read from the data memory according to the instruction A pre-fetched in the instruction cycle 201, and the multiplier performs an operation. In the instruction cycle 203, addition and subtraction between the multiplication result and the accumulator data (A bus output) are executed.
The result of the operation is output to the accumulator in cycle 204. The operations of these four steps are repeated in each instruction cycle with a one-step shift, and when the product-sum operation has been completed a predetermined number of times m, the operation result T is output to the data bus 20 by the instruction F, and the operation result T is output to the data memory 5 or Sent to external circuit.

The parallel operation of the processor by pipeline control is achieved by connecting the multiplier 14 and the adder/subtractor 15 in parallel, and by placing the register (register) that temporarily holds data in a position where the time required for each operation of multiplication and addition/subtraction is balanced. This is made possible by arranging latch circuits 71 and 72 (corresponding to this in FIG. 4).

FIG. 17 shows an application example of the digital signal processing processor described above. Here, a case is shown in which the processor 100 is connected to an analog line via an A/D converter 300 and a D/A converter 301, and functions as a digital filter.

FIG. 18 shows the digital signal processing processor 1.
00 is combined with another data processing device 101, such as a microcomputer MCS6800 manufactured by Hitachi, Ltd., and data is exchanged via terminals D ₀ to _{D 7} so that data processing can be shared between the two devices. Shows the system configuration. This system configuration includes a signal processing processor 100, a communication line modem,
Alternatively, it is suitable for application to an echo canceller, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the overall configuration of a digital signal processing processor to which the present invention is applied, and FIG. 2 is a diagram showing the detailed configuration of a multiplier 14.
Figure 3 A and B are input data and adder/subtractor 1, respectively.
5. FIGS. 4A and 4B are diagrams showing the detailed configuration of the adder/subtractor 15 according to the embodiment of the present invention. FIGS. 5A, B, and 6A , B are diagrams for explaining the operation of the shift circuit 76, FIG. 7 is a circuit diagram showing one embodiment of the shift circuit 76, FIGS. 8A and B are diagrams for explaining data overflow, and FIG. 9 is an output diagram. Correction circuit 1
Figures 10A to 10D are diagrams showing how floating point data changes in each part of the signal processing processor, and Figures 11A to D are fixed point data. 12 is a diagram showing the specific circuit configuration of the input selection circuit 60, FIG. 13 is a diagram showing the specific circuit configuration of the input selection circuit 61, and FIG. 14 is the output FIG. 15 is a diagram showing a specific circuit configuration of the switch circuit 17, FIG. 15 is a diagram showing the dynamic range of the digital signal processing processor to which the present invention is applied, and FIG. 16 is a diagram for explaining the operation characteristics of the above processor. The time charts of FIGS. 17 and 18 are diagrams showing typical usage patterns of the above-mentioned signal processing processor, respectively.

Claims (1)

[Scope of Claims] 1. An addition/subtraction device that performs addition or subtraction of two floating point data, the first data pair consisting of first and second floating point data, and the third and fourth floating point data. means for selectively selecting a second data pair consisting of data; means for performing addition/subtraction of the two data of the first data pair; and converting the third floating point data into fixed point data. and means for converting the third floating point data into fixed point data in response to the fourth floating point data. 2. The fourth floating point data has a mantissa value of 0 and an exponent value larger than the exponent value of the third floating point data. Addition and subtraction device according to range 1. 3. The fixed point data obtained by the above conversion is characterized in that the value of the mantissa part is obtained by normalizing the third floating point data in response to the value of the exponent part of the fourth floating point data. An addition/subtraction device according to claim 1 or 2.