JPH03226831A - 2n fold arithmetic circuit - Google Patents

Abstract

PURPOSE:To constitute the circuit so that a large number of steps of an instruc tion and many registers are unnecessary by constituting it so that an arithmetic shift instruction can be used at the time of executing 2<n> folds or 1/2<n> folds in a DSP for handling the data of a floating point format. CONSTITUTION:In a digital signal processing circuit (DSP) for handling the data of a floating point format, the number (n) of shifts designated by an arith metic shift instruction is inputted to an adding part 2, addition and subtraction are executed at the time of executing 2<n> folds and 1/2<n> folds, respectively, and a result of addition becomes an exponent of the data of the floating point format loaded to an accumulator 1. Accordingly, even in the case of the data of the floating point format, 2<n> folds 1/2<n> folds can be executed by an arithmetic shift instruction. In such a way, in the same way as the case of data of a fixed point format, the operation of 1/2<n> folds and 2<n> folds can be executed without having an instruction of three steps of the arithmetic shift and three registers.

Description

[Detailed Description of the Invention] [Summary] Regarding the 2'' multiplication circuit for floating point format data, when multiplying by 2'' or 1/2'' in a DSP that handles floating point format data, an arithmetic shift instruction is used. Usable 2
For the purpose of providing a multiplication circuit, the exponent of the floating-point format data loaded into the accumulator and the exponent n when multiplied by 2'' are input to the addition section, and the addition result is added to the floating-point format data loaded into the accumulator. Configure it so that it is an index of the data.

[Industrial application field]

The present invention uses a digital signal processing circuit (hereinafter referred to as DSP) to convert data in floating point format to 2" or 1/2".
The present invention relates to a 2-gax arithmetic circuit which can be multiplied by an arithmetic shift instruction in the same way as in the case of fixed-point format data.

DSPs are currently broadly classified into those that handle fixed-point format data and those that handle floating-point format data, and these are selected depending on the required accuracy and dynamic range.

Most of the arithmetic instructions are the same for both, but the arithmetic shift instructions, which are used to multiply fixed-point format data by 2 or 1/2'' and require fewer registers, have fewer steps. , there is no point in using it for data in floating point format.

On the other hand, in various signal processing, in order to simplify the hardware, things that approximate 2r' times or 1/2'' times are converted to 2' times or 1/2'' times. There are many algorithms that multiply by 1/2', and even in the case of floating point format data, it is desirable to be able to multiply by 2" or 1/2" using an arithmetic shift instruction.

[Conventional technology]

Figure 3 shows the representation of data in fixed-point format and the arithmetic shift and shift instructions for multiplying by 2'', and Figure 4 shows the representation of data in an example of floating-point format and the instruction for multiplying by 2n'. The fifth diagram shown in the figure is a conventional example of an addition circuit for floating-point format data.

Data in fixed-point format is expressed as a fixed-point number in two's complement representation, as shown in Figure 3(A)(a), and the beginning is a sign bit. ) as shown.

When fixed-point format data is arithmetic shifted to the right, the third
As shown in Figure (B), extending the sign and shifting it by n bits is equivalent to multiplying the original value by 1/27, and arithmetic left shifting by n bits means changing the original value by 2''. It's equivalent to multiplying.

The command for multiplying by 2″ is shown in Figure 3 (C).
Then, (1) load data multiplied by 2'' into the accumulator, (2) shift n bits to the left, and (3) load from the accumulator to memory, which can be done in 3 steps.

Of course, when multiplying by 1/2'', it is possible to do so by changing the left shift to an n-bit shift to the right.

As shown in Figure 4 (A) (a), floating point format data consists of a sign bit, an exponent e in the exponent part, and a mantissa f in the mantissa part, and the exponent is offset to make it a positive number. The value e is obtained by adding the value a (for example, 127).

This can be expressed numerically as shown in FIGS. 4(A) and (b).

In this case, there is no point in performing an arithmetic shift, and the instructions for multiplying by 20 are as shown in Figure 4 (B): (1) Load multiplicand register A with data multiplied by 2n; (2) 2
”Load the double value into multiplier register B, (3) Multiply, (4
) Loading the multiplication result into register P involves 4 steps, which is one more step than in the case of arithmetic shift, and also requires registers A, B, and P, which increases the number of registers.

Here, for the addition circuit of floating point format data, the fifth
Let me explain using a diagram.

In FIG. 5, data X in the first floating point format loaded into the accumulator 1 and data Y in the second floating point format loaded into the register 3 are added.
The sign of Y is input to selector 4, and the exponents of The selected exponent is input to the selector 12 and input to the subtracter 2, the difference between the exponents is determined by the subtracter 6, and the determined value is input to the right shift section 9.

In addition, the mantissas of X and Y are input to selector 7.8, and
Then select the larger exponent and input it to the adder 1■, use the selector 7 to select the smaller exponent and input it to the right shift section 9, and use the subtracter 6 to manually shift it to the right by the difference in exponents.
It is input to the inversion control section 10, and when it becomes subtraction, it is inverted and controlled.
Input to adder 11.

The adder 11 performs addition when performing addition, inputs carry input 1 and performs addition during subtraction, inputs the addition result to complementer 13, and inputs the sign to selector 12.

In the complementer 13, when the addition result in the adder 11 is negative, it is complemented, and when it is positive, it is inputted to the left shift section 16 and the bias encoder 14.

In the Brioliichi encoder 14, find where the first 1 is and change the value input to the left shift section 16 to 1. f
Shift it to the left so that it has the form , and output it as the mantissa.

Also, this value to be shifted to the left is set to the priority encoder 1.
4 to the subtracter 2, subtracts it from the exponent input from the selector 5, and outputs it as an exponent.

The selector 12 selects the code from the adder 11 when the exponents of X and Y are equal, and selects the code from the selector 4 when the exponents of X and Y are not equal, and outputs it as a code.

The sign, exponent, and mantissa of the output addition result are loaded into the accumulator l.

[Problem to be solved by the invention]

However, as explained above, in DSPs that handle conventional floating point data,
When multiplying, an arithmetic shift instruction cannot be used, and when multiplying by 2'' or 1/2'', the number of instruction steps is large and many registers are required.

The present invention aims to provide a 2'' arithmetic circuit that can use an arithmetic shift instruction when multiplying by 2'' or 1/2' in a DSP that handles data in floating point format.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

As shown in FIG.
be the exponent of the floating-point format data loaded into .

[For production]

According to the present invention, the shift number n specified by the arithmetic shift instruction is input to the adder 2, and when multiplied by 20, the shift number n is inputted to the adder 2.
When multiplying by 2', subtract and add the result to accumulator 1.
This is the exponent of the floating point format data loaded into the fixed point format data by 2'' or 1/2n
When multiplying, it can be executed with the 3-step instruction shown in FIG. 3(C), and the register can also be executed if there is an accumulator, so no register is required.

〔Example〕

FIG.

In Fig. 2, the difference from the conventional adder circuit in Fig. 5 is as follows.
In addition to addition, in order to perform 1/2n times or -1i9-2'' times operations, subtraction is performed by selecting either the output of the Brioliarity encoder 14 or the shift number n specified by the arithmetic shift instruction. a selector 15 that selects and outputs whether the sign of the output of the adder circuit is the sign of the data loaded into the accumulator 1; and a selector 17 that selects and outputs whether the sign of the output of the adder circuit is the sign of the data loaded into the accumulator 1, and the mantissa of the output of the adder circuit or the mantissa of the data loaded into the accumulator l. A selector 18 is provided to select and output either of the following:
The selector 17 selectively outputs the shift number n specified by the arithmetic shift instruction, the selector 17 selectively outputs the sign of the data loaded into the accumulator 1, and the selector 18 selectively outputs the mantissa of the data loaded into the accumulator 1. This point will be explained below, focusing on this different point.

When using an arithmetic shift instruction, the exponent of accumulator 1 is forcibly input to subtracter 2 through selector 5.

The selector 15 selectively outputs the shift number n specified by the arithmetic shift instruction and inputs it to the subtracter 2, and the selector 1718 selectively outputs the sign and mantissa loaded into the accumulator 1.

Then, in the same way as when multiplying fixed-point format data by 1/2" times 2", as shown in Figure 3 (C), (1) Load the data to be multiplied by 2" (or 1/2") into the accumulator. , (2) Shift n for 1/2'' times, -n shift for 2fi times, (3) When a load instruction is issued from the accumulator to memory, it is loaded into accumulator 1 by subtractor 2. n is subtracted from or added to the data index, replaced with the data index loaded into accumulator 1, and loaded into memory.

That is, as in the case of fixed-point format data, operations of 172'' and 2' can be performed without the need for a three-step instruction for 0 arithmetic shift and three registers.

[Effects of the Invention] As explained in detail above, according to the present invention, when multiplying floating-point format data by 1/2'' or 2'', the three steps of arithmetic shift are performed as in the case of fixed-point format data. instructions and three registers, 1/2” times, 2
・It has the effect of making it possible to perform double calculations.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention; Fig. 3 is a diagram showing fixed-point format data representation and arithmetic shift and shift instructions for multiplying by 2''; Fig. 4 is a block diagram of the present invention.
Figure 5 is a diagram showing an example of the representation of floating point data and an instruction for multiplying it by 2''. Figure 5 is a conventional example of an addition circuit for floating point data. In the figure, 1 is an accumulator, and 2 is an adder. , subtractor, 3 is a register, 4.5, 7, 8.12 15 17 18 is a selector, 6 is a subtracter, 9 is a right shift section, 10 is an inversion control section, 11 is an adder, 13 is a complementer, 14 is a priority encoder, and 16 is a left shift section.

Claims (1)

[Claims] Adder unit (
2) and uses the addition result as an exponent of floating point format data loaded into the accumulator (1).