JPS645500B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data modem (modulator/demodulator) constructed using a signal processing processor having a floating point arithmetic function.

[Background of the invention]

As shown in FIG. 1, the modem modulates data or facsimile signals consisting of a signal series of "1" and "0" into a signal form suitable for the voice telephone circuit (transmission section), and sends it out to the voice line. Demodulates the signal from the voice line (receiver) and restores the original “1” and “0”
It has the function of converting into a signal sequence.

Recently, a method has begun to appear in which the modem is configured with a processor dedicated to signal processing.

The signal processing processor is configured as an LSI with built-in program memory and dedicated multipliers and adders/subtractors for processing data at high speed.By changing the program, it can be used to create digital filters, codecs, and echo cancellers. It can be adapted to various uses such as, and has become an effective means for configuring modems.

The function of the modem will be explained using FIG.

In FIG. 1, “1” is the data or facsimile signal input to the output terminal 1000;
The signal consisting of a binary series of “0” is the scrambler 1
001 and subjected to predetermined code conversion by a differential encoder 1002. The output of the differential encoder is decomposed into two-dimensional data in the X-axis and Y-axis directions, passes through low-pass filters 1003 and 1004 to remove unnecessary components, and is converted into a carrier wave of a specific frequency by modulation circuits 1005 and 1006. Multiplication is performed in adder 10
At step 07, the X-axis and Y-axis components are added.
From the scrambler 1001 to the adder 1007 are executed by digital calculations, and a signal suitable for the audio line is outputted to the output terminal 1010 through a D/A (digital-to-analog converter) 1008 and an analog low-pass filter 1009.

On the other hand, in the receiving section, an analog signal transmitted through the audio circuit enters an input terminal 1013, passes through an analog band filter 1014, is amplified to a predetermined amplitude level by an AGC (automatic gain control) circuit 1015, and is amplified to a predetermined amplitude level by an A/D (analog - digital converter)
At step 1016, the signal is converted into a digital signal. One side of this digital signal is input to the power calculation circuit 1017 to obtain a control signal for the AGC circuit 1015, and the other side is input to the demodulation circuit 1 to demodulate the input signal.
018 and 1019, and the waveforms of the X-axis and Y-axis components are obtained. Low-pass filter 1020, 102
1, each waveform is shaped, and the automatic equalizer 1
At 023, the distorted waveform on the audio line is compensated, and the waveform equal to the original transmission signal is input to the identification judgment circuit 1024, which passes through the differential decoder 1025 and the desk lamp 1026 and converts it into the original transmission data or transmission facsimile signal. A binary series signal of equal "1" and "0" is obtained at the output terminal 1027. The timing extraction circuit 1022 has a function of obtaining A/D sampling pulses, and usually includes low-pass filters 1020 and 1.
The sampling pulse is extracted from the output signal of 021.

Further, the automatic equalizer 1023 is connected to the identification determination circuit 10.
The characteristics of the control signal obtained from 24 automatically follow changes in the characteristics of the audio circuit.

As explained above, the modem is 1021, 102
Signal processing calculation parts such as filters, modulation/demodulation circuits, automatic equalizers, etc. indicated by 9 and 1011, 1017, 1
Its functions are divided into a signal conversion section such as a scrambler and a differential code decoder, which are denoted by 028.

As described above, the modem has a signal processing calculation section as its central function, and is a device to which a signal processing processor can be fully applied.

However, if a conventional signal processor is applied to a modem as is, the range of numbers that can be handled (dynamic range) is narrow, making design difficult, and in some cases it may not be possible to realize a modem.

This is because conventional signal processing processors use a fixed point format and cannot have a wide dynamic range.

Let us briefly discuss the problems with modem configurations when using conventional fixed-point signal processing processors.

As shown in FIG. 1, the modem includes various filter circuits.

For example, the transfer characteristic H(Z)≡H ₁ (Z)・H ₂ (Z)・H ₃ (Z) …(1) H _i (Z) (i=1, 2, 3) is the transmission of each partial filter. Let us consider the case where a digital filter having the following characteristics is operated in a fixed-point arithmetic format.

In filter design, a filter with the characteristic H(Z) is usually not constructed directly as it is, but is decomposed into each factor H _i (Z) (for example, a Biquad filter) and the circuits are connected in cascade.

In this case, as shown in Figure 2, H ₁ (Z), H ₂
(Z), H ₃ (Z) and when connecting in cascade in the order of H ₂
(Z), H ₁ (Z), and H ₃ (Z) are connected in cascade in this order, the signal level diagram of the filter is different.
In the A-type configuration, the signal level at point b decreases, so care must be taken in designing the S/N (signal component to rounding noise). Furthermore, in the B-type configuration, it is necessary to design it so that no signal overflow occurs at point b. A filter can be constructed if the range of numerical values to be handled as shown in the figure can be expressed in fixed-point representation, but if the dynamic range is narrow and the above level diagram cannot be realized, the filter cannot be realized.

As described above, when a modem is configured using a fixed-point signal processor with a narrow dynamic range, the parameters of the filter that can be realized are limited.

[Eye of invention]

An object of the present invention is to solve the above-mentioned problems when configuring a modem with a signal processing processor.

[Summary of the invention]

In order to achieve the above object, the present invention is characterized in that a modem is configured using a floating point signal processor with a wide dynamic range, and there are no restrictions on the parameters that can be realized.

More specifically, the digital signal processor forming a part of the present invention includes means for supplying first and second data each consisting of an exponent display section and a mantissa display section, and means for supplying the first and second data. floating point data multiplication means for adding together the exponent display parts and multiplying the mantissa display parts to output an operation result;
floating-point data addition/subtraction means to which the calculation result of the multiplication means is supplied as one input; data accumulation means for holding the calculation result of the addition/subtraction means; and the data supply means, the multiplication means, and the addition/subtraction means. A connected first data bus, a second data bus for inputting the output of the accumulating means to the adding/subtracting means, and between the accumulating means and the first and second data buses; and a control means for controlling the operation of each of the above elements according to a program.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a signal processing processor which is a part of a modem of the present invention will be described with reference to the drawings.

The relationship between the signal processor and other components of the modem will be explained later with reference to FIG.

FIG. 3 is an overall configuration diagram of a digital signal processor used in a modem according to the present invention, in which 1 is a memory for storing programs, 2 is a program counter for instructing the read address of the program memory 1, and 3 is the above-mentioned program counter. Program memory 1
instruction register connected to , 4 is instruction register 3
This is a control circuit that generates various control signals S for operating the processor from command words read out. In this embodiment, the instruction word stored in the memory 1 consists of, for example, 22 bits, each containing an operation code, data, address or address control information. Program counter 2
and instruction register 3 are connected to a 16-bit data bus (D bus) 20.

5 and 6 are memories for storing data, and 7 is a general-purpose register. One of the memories 5, 6 can be a random access memory (RAM) and the other can be a read only memory (ROM). In addition, each memory consists of multiple small-capacity ROMs.
Alternatively, it may be a composite of RAM. The memory stores 16-bit data, and each data is read out to the 16-bit X bus 21 or Y bus 22 via the selection circuit 8. Registers 9 and 10 designate lower addresses of the data memories 5 and 7, respectively, and registers 11 and 12 designate upper addresses of the memories. Furthermore, register 11
gives the upper address of the data to be read to the X bus 21, and the register 12 gives the upper address of the data to read to the Y bus 22 or the address of the general-purpose register 7, and these registers receive the data from the instruction register 3. Address information is provided via bus 23.

14 is a floating point multiplier that calculates the product of two data given from the X bus 21 and the Y bus 22 and outputs the result to the P bus 24. Input data X,
It includes a register to hold Y, and the two unoperated data X and Y are directly transferred to the X bus 25 and Y.
Output to bus 26.

Reference numeral 15 denotes a floating point arithmetic type adder/subtractor, which performs calculations using the output data X, Y, P of the multiplier 14 and the data D, A of the data buses 20, 27 as input, and sends the results to the accumulator 16. Output. 1
7 is a switch circuit that outputs the floating point data latched in the accumulator 16 to a 20-bit data bus (A bus) 27, and also converts the above data into 16-bit data and outputs it to the D bus 20; 1
A state code register 8 is connected to the multiplier 14 and the adder/subtractor 15 and stores a state code related to the results of these operations.

30 is an output register for outputting 16-bit data on the data bus 20 in parallel to external terminals _D0 to _D15 , and 31 is for capturing 16-bit data from the external terminals to the data bus 20 in parallel. is the input register of Further, 32 is a 16-bit shift register for taking in serial input data from the terminal SI in synchronization with the input clock of the terminal SICK while the input pulse of the terminal SIEN is "1", and 33 is the input pulse of the terminal SOEN. This shows a 16-bit shift register for serially outputting data to the terminal SO in synchronization with the input clock of the terminal SOCK during the period when is "1". These two shift registers are each connected in parallel with the data bus 20 for 16 bits.

35 is a register that controls the operating state of the processor; 36 is a counter that is set to the number of repetitions when a repeat instruction causes the processor to repeatedly execute a certain instruction; and 37 is a status register that indicates the internal state of the processor. .
The contents of the registers 35 and 37 can be written and read from the outside via the data bus 20 and terminals _D0 to _D15 , respectively.

40 is a control circuit for controlling interrupts to processor operations and input/output operations;
The shift registers 32 and 33 are enabled at the rising edge of the SIEN and SOEN input signals, interrupt the program at the falling edge of each signal, and the registers 30 and 33 are enabled at the rising edge of the input/output signal to the terminal IE.
31 and interrupts the program at the falling edge of the signal. 41 is a function control circuit that controls the processor operation according to signals from an external control device (for example, a microcomputer); for example, a DMA transfer mode acknowledgment signal is sent from the terminal TXAK, and a parallel input/output data A signal indicating the transfer direction, a signal indicating that this processor has been selected by an external device from terminal CS,
Test operation mode specification signal from terminal TEST,
Receives a reset signal from RST and an operation control signal from an external device from terminals F _0-3 , respectively.
Outputs parallel data transfer request signal from TxRQ.
The terminal Bit I/O indicates a bidirectional input/output terminal for inputting and outputting data one bit at a time. 42 is a clock pulse generation circuit, which receives the basic clock from an external circuit via the terminal OSC, generates various internal clocks necessary for processor operation based on this, and also outputs the internal operation of the processor and external clocks to the terminal SYNC. Outputs the clock for system synchronization.

Next, according to FIGS. 4, 5, and 6, the multiplier 14
The adder/subtractor 15 will be further explained.

The multiplier 14 has an X bus 2 as shown in FIG.
1, 16-bit data of the Y bus 22 is input. These data are given from memories 5 and 6, general register 7, or data bus 20. As shown in FIG. 5A, in these data, the lower 4 bits are the exponent part, the upper 12 bits are the mantissa part, and the most significant bit of each part is shown with diagonal lines, that is, 2 ³ . ^{2 15} . The bit in this position is the sign bit. Also, the decimal point is between 2 ¹⁵ and 2 ¹⁴ . As shown in FIG. 4, the exponent data and mantissa data given from the X bus 21 and the Y bus 22 are held in registers 51, 52, 53 and 54, respectively, and the exponent data in registers 51 and 52 are added together. The sum is added by the circuit 55 and output to the P bus 24 via the 4-bit output register 56. On the other hand, the mantissa data of the registers 53 and 54 are input to a multiplication circuit 57 having a circuit configuration similar to that of normal fixed-point arithmetic, and the higher 16 bits of the multiplication result are transferred to the P bus 2 through the output register 58.
4 is output. That is, the calculation output of the multiplier 14 is input to the adder/subtracter 15 as 20-bit data consisting of the lower 4 bits of the exponent part and the higher 16 bits of the mantissa part, as shown in FIG. 5B. Note that the outputs of registers 52 and 54 are sent to the X bus 25, and the outputs of registers 51 and 53 are sent to the Y bus 26, and each is sent to the adder/subtractor 1 as 16-bit data.
given to 5.

The configuration of the adder/subtractor 15 is shown in FIGS. 6A and 6B.

As shown in FIG. 6A, the adder/subtractor has bus 2.
0, 24 to 27, data D, P, X,
Y and A are input. Among these, data P,
Y and D are input to the selection circuit 60, and one data designated by the control signal _S1 is selected. Further, the data A and X are input to the selection circuit 61 and the control signal S ₂
One piece of data specified by is selected. Here, the input data D, X, and Y are each 16-bit data shown in FIG. 5A. As described later, when these 16-bit data are specified,
The selection circuits 60 and 61 select these data as shown in FIG.
It is configured to convert and output the 20-bit data shown in . This bit conversion differs depending on whether the input data D, X, Y are fixed point data or floating point data, and the conversion operation is specified by the control signal _S3 . This allows the floating-point type adder/subtractor to process input data expressed in fixed-point numbers. Furthermore, the control signal S ₁ ,
S ₂ , S ₃ . . . S _o are output from the control circuit 4 in response to command words in the program.

The output data from the selection circuit 60 is β (exponential part β _E ,
the mantissa part β _M ), and the output data from the selection circuit 61 as α
(instruction part α _E , mantissa part α _M ), the exponent part data α _E is inputted to the comparison circuit 63 via the selection circuit 62 and compared in magnitude with the exponent part data β _E. Moreover, these exponent part data α _E and β _E are respectively input to the subtraction circuit 6
4 and is also input to the selection circuit 65. The mantissa data α _M is passed through a negation circuit 66 to a selection circuit 67,
68, and the mantissa data β _M is directly input to selection circuits 67 and 68. Negate circuit 66
In the case of this embodiment, is provided to realize subtraction between data α and β using the ALU 75 having an adder configuration described later, and in the case of an addition operation, data α _M passes through the negate circuit. do. The selection circuits 65, 67, and 68 each include the comparison circuit 6.
One of the two inputs is selected depending on the output signal of No. 3. The output of the selection circuit 65 is the latch circuit 71.
Then, the output of the selection circuit 67 is latched via a shift circuit 69 to a latch circuit 72, and the output of the selection circuit 68 is latched to a latch circuit 73 using a timing signal C. The subtraction circuit 64 is also controlled by the output of the comparison circuit 63, and operates to subtract the smaller one of the inputs α _E and β _E from the larger one according to the comparison result. The shift circuit 69 shifts the input data to the right by the number of bits corresponding to the output of the subtraction circuit 64 obtained via the selection circuit 70. The operation of this shift circuit 69 is controlled by the selection circuit 70.
The selection of the number of shift bits is performed by the control signal _S7 .

The outputs e _A and e _B of the latch circuits 72 and 73 are inputted to a fixed-point arithmetic type adder (ALU) 75 operated by a control signal S8, as shown in FIG. _6B , and the addition result U _M is The signal is applied to a leftward shift circuit 76.
On the other hand, the output γ of the latch circuit 71 is
7 and one input terminal of the subtraction circuit 78. 79 is a zero detection circuit that determines the output U _M of the adder 75, and when the output U _M of the adder given in complement representation is a positive number, the “0” bit following the sign bit at the top of U _M is detected. Count the number of consecutive pieces. If U _M is a negative number, count the number of consecutive "1" bits following the side bit.
The output θ ₁ of the zero detection circuit 79 is applied to the shift circuit 76 via an output correction circuit 80 provided for data normalization and overflow prevention, and determines the number of bits to shift data by this shift circuit. The output θ ₁ of the zero detection circuit 79 is also input to the other input terminal of the subtraction circuit 78, and the output U _E of this subtraction circuit is sent to the exponent part 16X of the accumulator 16 via the output correction circuit 80. is input. The mantissa part 16M of the accumulator 16 includes an output correction circuit 80.
The output data L' _M from the shift circuit 76 corrected in the above is input.

The output correction circuit 80 outputs the overflow detection signal OVF output from the adder 75 and the subtraction circuit 78.
The output θ ₁ of the zero detection circuit 79 and the constant addition circuit 7 according to the underflow detection signal UNF output from the
A selection circuit 81 for selecting one of the outputs θ ₂ and 7
and a selection circuit 82 which supplies either the output of the selection circuit 81 or the data F given by the program as a shift bit number instruction signal θ to the shift circuit 76 in response to a control signal _S9 by the program, and an overflow signal OVF. An increment circuit 83 which adds 1 to the subtraction circuit output U _E when it is "1" and outputs a signal EOVF when the addition result L _E also overflows, and an exponent of the increment circuit 83 and the accumulator 16. an exponent part correction circuit 85 inserted between the exponent part 16x, a mantissa part correction circuit 87 inserted between the shift circuit 76 and the mantissa part _16M of the accumulator 16, and the two correction circuits 8
It consists of a control circuit 89 that controls the operations of 5 and 87 in accordance with signals UNF and EOVF.

The adder/subtractor 15 having the above configuration operates as follows.

Two input selection circuits 61, 6 shown in FIG. 6A
The respective outputs α and β of 0 are floating point data, and their values are expressed by the following equation.

α=α _M・2〓 ^E β=β _M・2〓 ^E …(3) Now, assuming that we are performing an addition operation on two data α and β that have a relationship of α _E > β _E , the addition result Z
is given by Z=α _M・2〓 ^E +β _M・2〓 ^E = [α _M +β _M・2 ^-( 〓 ^E- 〓 ^E) ]・2〓 _E …(3).

The comparison circuit 63 compares the magnitudes of α _E and β _E , causes the selection circuit 65 to select the larger exponent part data α _E , and causes the selection circuit 67 to select the mantissa data corresponding to the smaller exponent part β _E. The selection circuit 6 selects data β _M.
8 selects the mantissa data α _M corresponding to the larger exponent part α _E , and a control signal is given to the subtraction circuit 64 to subtract the smaller exponent β _E from the larger exponent α _E. During execution of the addition operation, the selection circuit 70 selects the output (α _E - β _E ) from the subtraction circuit 64, and the shift circuit 69 selects the output β _E from the selection circuit 67 (α _E - β _E ). Just the bits to the right (toward the lower bits)
It operates to shift to. As a result, the outputs of the latch circuits 71, 72, 73 are γ=α _E , e _A =
β _M ·2 ⁻⁽ 〓 ^E− 〓 ^E) , e _B = α _M , and the output U _M of the adder 75 that has performed the operation of e _A +e _B represents the mantissa part of equation (1). Therefore, the calculated value Z at this stage is expressed by the following equation.

Z=U _M ·2 ^r (4) The zero detection circuit 79 and the leftward shift circuit 76 are for normalizing the adder output U _M so that its absolute value becomes maximum. As shown in Figure 7A,
The zero detection circuit 79 detects the number θ ₁ of consecutive “0”s (below the decimal point) following the sign bit of the data U _M , and the shift circuit 76 shifts the data U _M by θ ₁ bits to the left (most significant bit side). ), the mantissa data L _M with the maximum absolute value can be obtained.
If U _M is a negative number, it is only necessary to shift by the number of consecutive "1"s as shown in FIG. 7B. In this case, for the exponent part data γ, the subtraction circuit 78 performs the calculation (γ-θ ₁ ), and the output U _M is taken as the normalized exponent value. If no overflow occurs in the data U _M , the output L _E of the increment circuit 83 will be equal to the normalized exponent value U _E , and the normalization process can be expressed by the following equation.

Z=[U _M・2〓 ¹ ]・2 ^(r- 〓 ¹⁾ =L _M・2 ^LE …(5) If the size of the exponent part γ is 4 bits, γ can be expressed by two's complement representation. The value obtained is [+7γ−
8]. Therefore, when normalizing the mantissa data above, if we try to completely shift the data U _M to the left by the detected value θ ₁ of the zero detection circuit, we get
The value of (γ-θ ₁ ) on the exponent side may become smaller than -8, causing an underflow in the subtraction circuit. At this time, the subtraction circuit 7 that performs the calculation of (γ−θ ₁ )
From 8 onwards, a signal (borrow signal) indicating data underflow is generated as UNF. In the circuit of FIG. 6B, when the signal UNF is generated, the selection circuit 81 selects the output θ ₂ of the constant addition circuit 77 in place of the input θ ₁ , and the constant addition circuit 77 selects the data γ of the exponent part. The value obtained by adding the constant "8" is output as data θ ₂ . If we do this, for example, when the value of γ is "-5", the value of θ ₂ will be "3", so the number of shift bits of the mantissa data U _M will be 3.
The normalized value of the exponent remains at the minimum value "-8". The operation of setting the exponent part to "-8" when the signal UNF occurs is performed by an exponent part correction circuit 85, which will be explained later with reference to FIG.

If an overflow occurs in the calculation result U _M of the adder 75, as shown in FIGS. 8A and B, the true sign of the data appears in the carry output, and the most significant bit of the numerical value appears in the sign bit position. There is. Therefore, in this case, the overflow detection signal
By OVF, selection circuit 81 and zero detection circuit 79
, the shift circuit 76 is caused to shift right by 1 bit, and the increment circuit 83 is caused to shift to the right by 1 bit.
It is sufficient to perform the operation of U _E (=γ)+1 and manipulate the data Z as shown in the following equation.

Z=[U _M・2 ^-1 ]・2 ⁽ 〓 ⁺¹⁾ ...(6) An example of the shift circuit 76 that performs the above operation is shown in the ninth
As shown in the figure. This circuit consists of an 8-bit shifter 761, a 4-bit shifter 762, a 2-bit shifter 763, and a 1-bit shifter 764, each corresponding to each bit θ ₃ to _{θ 0} of the shift bit number instruction data θ. The switches SW ₃ to _{SW 0} of the signal line are connected to the contacts on the lower bit side when the corresponding control bits θ ₃ to θ ₀ are “1”.
In addition, each switch SW ₀ of the 1-bit shifter 764
is connected to the contact on the upper bit side when the overflow detection signal OVF is "1", and the output line _L19 of the sign bit is connected to the carry signal input terminal 765, realizing the above-mentioned 1-bit right shift operation of the data. .

In the circuit shown in FIG. 6, when the overflow detection signal OVF of the adder 75 becomes "1", an overflow may also occur in the calculation result of (γ+1) by the increment circuit 83. In this case, it means that an overflow has occurred in the calculation result Z (= α + β), and if the product-sum calculation continues as it is, the absolute value of the output data obtained from the accumulator 16 will be as shown in FIG. 10A. It changes and becomes a completely meaningless value.

When the above-mentioned overflow occurs in the calculation result Z, the control circuit 89 and the correction circuits 85 and 87
As shown in FIG. B, this is a circuit that operates to fix the absolute value of output data to the maximum positive or negative value, and a specific example of its configuration is shown in FIG.

In FIG. 11, the exponent part correction circuit 85 includes a two-input AND gate 8 corresponding to input bits _L0 to _L3 .
50-853 and 2-input OR gate 860-863
Each bit signal is output to the accumulator 16x via these gates. AND gate 853 into which the sign bit _L3 of the exponent part data is input
An increment circuit 83 is connected to the other input terminal of
An inverted signal of the overflow detection signal EOVF outputted from the subtraction circuit 78 is inputted to the other input terminal of the OR gate 863, and an underflow detection signal UNF from the subtraction circuit 78 is inputted to the other input terminal of the OR gate 863. Furthermore, AND gates 850 to 850 to which data bits L ₀ to L ₂ are input
The other input terminal of each of the 852 has a signal
The inverted signal of UNF is input, and the OR gate 860~
The signal EOVF is input to the other input terminal of 862. Signals EOVF and UNF are “1” at the same time
Therefore, when the signal EOVF is "1", the output of the exponent part correction circuit 85 becomes [0111]=+7, making the exponent part the maximum value. Also, the signal UNF
When is "1", [1000]=-8, which satisfies the exponent value when θ=θ ₂ described above.

On the other hand, the mantissa correction circuit 87
Outputs _L19 as is, and outputs data bits _L4 to _L18 to 2-input OR gates 871 to 87N, 2-inputs, respectively.
It is configured to output via AND gates 881 to 88N. The output of the AND gate 891 of the control circuit 89 is given to the other input of each OR gate, and the output of the NAND gate 892 of the control circuit 89 is given to the other input terminal of each AND gate. When the signal EOVF is “1”, the mantissa data is a positive value, that is, the sign bit _L19 is “0”.
Then AND gate 891 and NAND gate 892
Both outputs become "1", and the output of the correction circuit 87 becomes the maximum positive value [0111...11]. Furthermore, if the sign bit _L19 is "1", the output of the NAND gate 892 is "0", and therefore the output of the correction circuit 87 is the maximum negative value [1000...00]. When the signal EOVF is "1", these correction circuits 85 and 86 output the input data L _E and L _M as they are as data L' _E and L' _M. These output data L' _E and L' _M are output to the A bus 27 via the accumulator 16 and the switch circuit 17, and are fed back to the selection circuit 61 of the adder/subtractor 15.

From the above explanation of the operation, it can be seen that in the digital signal processing processor that forms part of the configuration of the present invention, the multiplier 1
4 and the adder/subtractor 15 can each perform floating point operations. Here, data input from the X bus 21 or Y bus 22 to the multiplier 14 and from the multiplier 14 or the A bus 27 to the adder/subtractor (ALU) 1
Since the number of input data bits and the number of data bits of the receiving circuit match when inputting data to the circuit 5, there is no change in the bit position between the data, as shown in FIGS. 12A and 12B. However, X bus 2
5. When the 16-bit data from the Y bus 26 and the D bus 20 is taken into the adder/subtractor 15, the number of bits of the mantissa data does not match, so the input selection circuits 60, 61 of the adder/subtractor input the 16-bit data as shown in FIG. As shown, it is necessary to add "0" to the lower 4 bits of the mantissa input data M. Also, when outputting the 20-bit adder/subtractor output obtained from the accumulator (ACC) 16 to the 16-bit D bus 20,
In the switch circuit 17, as shown in FIG. 12D, it is necessary to discard the lower 4 bits of the mantissa part M and convert it into data of 4 bits for the exponent part and 12 bits for the mantissa part.

In the digital signal processing processor that forms part of the configuration of the present invention, in order to facilitate implementation of a modem, an input selection circuit 60 that performs the data conversion operation described above for the purpose of increasing the dynamic range;
61 and the output switch circuit 17 are further devised,
The processor can also perform fixed-point operations as specified by the program.

Multiplication of fixed point data X and Y is performed in a mantissa data multiplication circuit 57 within the multiplier 14.
In this case, as shown in FIG. 12A, the mantissa input register 53,
The upper 12 bits of 54 are treated as valid data. On the other hand, when adding or subtracting fixed-point data, the shift operation of the shift circuits 69 and 76 in the adder/subtractor 15 is stopped according to the exponent in the program.
The mantissa calculation result obtained in this state is used. The operation of the shift circuit 69 is stopped by controlling the fixed point data arithmetic instruction to give the numerical value "0" data to the data line E in FIG. 6A, and the selection circuit 70 to select the input from the data line E. The signal _S7 may be generated. To stop the operation of the shift circuit 76, a numerical value "0" is given to the data line F in FIG. 6B, and a control signal _S9 is generated so that the selection circuit 82 selects the input from the data line F. do it.

In addition and subtraction of the above fixed-point data, the data input from the multiplier 14 or the A bus to the adder/subtractor 15 is as shown in FIG. Bye. Data input from the X bus, Y bus, and D bus puts all bits into the mantissa part as shown in Figure 13C, and the mantissa data obtained by the accumulator (ACC) is shown in Figure 13D. Thus, all bits are output to the D bus 20.

FIG. 14 shows a specific example of an input selection circuit 60 for an adder/subtractor having the above-mentioned bit conversion function. In this circuit diagram, P ₀ to P ₁₉ , Y ₀ to _{Y 15} , and D ₀ to D ₁₅ represent each bit of input data from the P bus 24, Y bus 26, and D bus 20, respectively, and among these, the data P The exponent parts P ₀ to _{P 3} of are input to the switch 601,
The four output terminals of switch 601 are
3 terminals _C0 to _C3 . Each bit of data Y and D and bits P ₄ to _{P 19} of the mantissa part of data P are input to switch 602, and the output terminal of the upper 12 bits of switch 602 is connected to the output line β ₈ to β ₁₉ of the upper bit of data β. The output terminals of the lower 4 bits are connected to terminals C ₄ -C ₇ of switch 603 and the other input terminal of switch 601.
The switch 603 has eight output terminals connected to the output lines β ₀ -β ₈ of the lower bits of the data β, and four terminals 604 that give the state "0".
605 is a control circuit 4 according to the command word of the program.
Based on control signals S ₁ and S ₂ given from
This is a logic circuit that generates 60B and 60C.

When data to be selected is specified by the control signal _S1 , the switch 60 is activated by the signals 60A and 60B.
1, 602 operates, and one of data P, Y, and D is selected. At this time, if the control signal _S2 instructs floating point arithmetic, the switch 603
Output lines β ₀ to β ₃ to terminals C ₀ to C ₃ , output lines β ₄ to _{β 7} to terminals C ₄ to C ₇ (when input data P is selected)
Alternatively, it operates to connect to terminal 604 (if input data Y or D is selected). If the control signal S ₂ indicates fixed-point arithmetic, then
Output lines β ₀ to _{β 3} are terminals 604 regardless of input data.
, β ₄ to β ₇ are connected to terminals C ₄ to _{C 7} .

FIG. 15 shows a specific circuit configuration of another input selection circuit 61. This circuit is the 14th circuit, except that there are two types of inputs: A bus and X bus.
It is the same as the figure, and the explanation will be omitted.

FIG. 16 shows a specific circuit configuration of the switch circuit 17 connected to the accumulator 16. In this circuit, the 20-bit output G ₀ -G ₁₉ from the accumulator is input to the input terminal of switch 171. The switch 171 has 16 output terminals connected to each signal line D ₀ to _{D 15} of the data bus 20, and the connection between the input terminal and the output terminal is the output signal 17 of the logic circuit 172.
It is controlled by A and 17B. When the control signal _S2 according to the program command indicates floating point arithmetic, the switch 171 is controlled by the signal 17B to connect the lower 4 bits of the output side signal lines _D0 to _D3 to the input signal lines _G0 to _G3.
and connect D ₀ to _{D 3} for fixed-point arithmetic.
Connect to G ₄ ~ G ₇ . Signal 17A is data bus 2
Controls output of upper bit data to 0.

According to the signal processing processor that forms a part of the data modem of the present invention, it is possible not only to perform operations on fixed-point data or floating-point data as described above, but also to convert the operation results obtained in floating-point format into fixed-point data according to program instructions. It is also possible to perform calculations by converting fixed-point format data into floating-point format data. This feature is extremely convenient when the signal processor exchanges data with external devices via the data bus 20 and the input/output interfaces 30-33. When configuring a modem using a signal processing processor, the external device handles data in a fixed-point display format, and if the floating-point calculation results of the signal processing processor are output as they are, the processor's This is because a special device for converting the data format is required externally.

Conversion from floating point representation to fixed point representation (hereinafter referred to as FLFX) is performed as follows.

First, when the floating-point representation data obtained by the accumulator 16 is A=α _M・2〓 ^E , the exponent part satisfies the relationship α _E < β _E and the mantissa part has the value β _M = 0. Data y ₁ =β _M ·2〓 ^{E having the value y 1 =β M·2〓 E} is stored at a specific address in the data memory 5 or 6. This address is made to correspond to the address part of the FLFX instruction word. Further, when this instruction word is executed, the selection circuit 8 outputs the data y read from the memory to the Y bus 22, and the selection circuit 8 outputs the data y read from the memory to the Y bus 22.
0 selects the input from the Y bus, and selects the selection circuit 6.
1 selects the input from the A bus 27, and the selection circuit 8
2 selects the input data F (="0"), and generates various control signals so that the output switch 17 connects the input signals G ₄ to _{G 19} to the data bus 20.

By doing this, when the FLFX instruction is executed, an operation will be performed between the two floating point data A and _y1 , and the accumulator 16 will have Z=A+ _y1 =[0+α _M・2 ^{- (} 〓 ^E- 〓 ^E) 〕・2〓 ^E …(7) is obtained. This data is normalized using ^2〓E as the reference value of the exponent part, and the data bus 2
The mantissa data α _M ·2 ⁻⁽ 〓 ^E− 〓 ^E) output as 0 can be handled as fixed-point data.

Normally, it is not possible to accurately know the optimal value of β _E for the internal calculation result A, so _modem designers
It is better to choose a slightly larger value. However, it must be noted that if the value of β _E is made too large, the precision of fixed-decimal data will decrease.
When executing FLFX above, if the exponent part α _E of the calculation result Z becomes larger than the exponent part β _E of the conversion data y ₁ stored in the memory in advance, the mantissa part of equation (7) overflows. will occur. In this case, the absolute value of the fixed-point data can be fixed to the maximum positive or negative value by the operation of the output correction circuit 80 described above.

On the other hand, for example, the operation of internally converting fixed-point data given from an A/D into floating-point data can be performed as follows. First of all,
An instruction to transfer the fixed-point data input to the input register 31 to the accumulator 16 is executed. In this command, 16-bit fixed-point display data D given to the selection circuit 60 via the data bus 20
is converted into the mantissa part β _M by the operation of the selection circuit 60, and the selection circuit 67 and the shift circuit 6
9, latch circuit 72, adder 75, shift circuit 7
6. Mantissa part 1 of accumulator 16 via correction circuit 87
6 Have _M input. In this case, the shift circuit 69,
Each adder 75 is controlled to allow input data to pass through.

Next, execute an instruction to convert from fixed-point representation to floating-point representation (hereinafter referred to as FXFL). When this instruction is executed, the selection circuit 61 selects the accumulator output provided from the A bus 27, that is, the fixed point data A described above, as the outputs α _M and α _E. Further, the selection circuit 60 selects the conversion data y ₂ read out to the Y bus 26 from the memory 5 or 6 specified by the address part of the FXFL instruction as the outputs β _M and β _E. This conversion data y ₂ is, for example, the mantissa part β _M
is zero, and the exponent part β _E is selected from the range of values [+7 to -8] and has a certain reference value. Unlike when executing other instructions, when executing the FXFL instruction, the selection circuit 62 generates a control signal S ₄ to select the input β _E , and both inputs of the comparison circuit 63 are set to β _E.
In this case, the mantissa selection circuit 67 inputs α _M as
The selection circuit 68 selects each of the inputs β _M , and the exponent part selection circuit 65 selects the input β _E. Further, the control signal _S7 causes the selection circuit 70 to select input data E=“0”, thereby suppressing the data shift operation of the rightward shift circuit 69.

By the above control operation, the latch circuits 71, 72,
The outputs of 73 are γ=β _E , e _A =α _M , and e _B =0. Data e _A and e _B are input to adder 75 and the addition result is
The decimal point position of U _M (=α _M ) moves by θ ₁ bit under the operation of the zero detection circuit 79 and the leftward shift circuit 76, and as a result, Z = [α _M・2〓 ¹ ]・2 ⁽ 〓 ^E- 〓 ¹⁾ ...The data expressed by (8) is obtained in the accumulator 16. This formula shows that fixed-point data A = α _M is the exponent β _E
This means that it has been normalized to the standard and displayed as a floating point number. Therefore, with the instruction FXFL, accumulator 1
By using the above data obtained in step 6, subsequent calculations can be performed in floating point format, and filter calculations with a wide dynamic range can be performed.

Note that the data in the input register 31 is once transferred to the accumulator 1.
6, the FXFL instruction was executed, but by inputting fixed-point input data and conversion data _y2 to the adder/subtractor 15 using the X bus 25 and D bus 20, it was possible to float with one instruction. It can also be designed to convert data to decimal point representation.

As mentioned above, the digital signal processor that forms part of the data modem of the present invention can handle data in both fixed-point and floating-point formats, and moreover, when normalizing floating-point display data, there is an underflow in the exponent part. When this occurs, a normalization operation can be performed that fixes the exponent value to the minimum value, so if the internal calculation data value is large, the calculation method is automatically switched to floating point calculation format, and if it is small, the calculation method is automatically switched to fixed point calculation format. It is possible to obtain an extremely wide dynamic range, and it can be sufficiently applied to data modems.

That is, when the internal data of the adder/subtractor consists of a mantissa part of 16 bits and an exponent part of 4 bits, the exponent part .gamma. can handle values in the range of [+7 to -8] in two's complement representation. If all operations are processed in floating point format, the dynamic range will be 2 ^-8 to ²⁷ as shown by hatching in FIG. 17, which corresponds to 15 bits when converted to the number of bits. According to the present invention, when the normalized number of bits θ for the mantissa part of the calculation data is in the range of (γ-θ)<-8, by fixing the normalized exponent L _E to -8, It is now possible to switch to fixed-point arithmetic. Therefore, as shown in FIG. 17, the dynamic range is 31 bits in total, and the range of numerical values that can be handled is significantly expanded compared to when only one of the fixed and floating types is used.

FIG. 18 is a time chart showing an example of parallel operation. In the next cycle 202, data is read from the data memory according to the instruction A pre-fetched in the instruction cycle 201, and the multiplier performs an operation. In the instruction cycle 203, addition and subtraction between the multiplication result and the accumulator data (A bus output) are executed.
The result of the operation is output to the accumulator in cycle 204. The operations of these four steps are repeated in each instruction cycle with a one-step shift, and when the product-sum operation has been completed a predetermined number of times m, the operation result T is output to the data bus 20 by the instruction F, and is sent to the data memory 5 or externally. sent to the circuit.

The parallel operation of the processor by pipeline control is achieved by connecting the multiplier 14 and the adder/subtractor 15 in series, and by placing the register (sixth This is made possible by arranging latch circuits 71 and 72 (corresponding to this in the figure).

By configuring a modem using the floating point signal processor as described above, not only can cascaded filters be easily configured, but also an automatic equalizer can be easily realized, as shown above.

An automatic equalizer that has the function of automatically estimating the amount of distortion from a waveform distorted by a voice telephone line and returning it to the original distortion-free waveform includes a transversal filter as shown in Fig. 19 in its main part. There is.

In FIG. 19, the input signal X _o input to the output terminal 1400 is output to each one sampling delay circuit 1200.
-1,1200-2,...1200-(N-1)
, the output of each delay circuit is each coefficient
Multiplication circuit 1100-1, 11 with C ₁ , C ₂ ..., C _N
00-2, 1100-3, ..., 1100-N, and the respective outputs are sent to adder 1.
300 and an output Y _o as shown in the following equation is obtained at the output terminal 1500.

Y _o = _N 〓 ⁱ⁼¹ Ci・X _o-i+1 …(9) As shown in Fig. 1, each coefficient C ₁ , C ₂ , … C _N
The value changes according to voice line fluctuations.

The above equation is a case where the product-sum operation is repeatedly executed N times, and when N is large and the dynamic range of the operation is narrow, overflow often occurs.

Even in such calculations, if the modem is configured using a floating-point signal processing processor, overflows are less likely to occur in the automatic equalizer, and high-performance automatic equalization characteristics can be obtained.

FIG. 20 shows an embodiment of a data modem configuration according to the present invention using the floating point signal processor described above.

In FIG. 20, the transmitting section A is an example in which the function corresponding to the transmitting section in FIG. 1 is realized using the above-mentioned floating point signal processing processor, and the receiving section B is an example in which the function corresponding to the receiving section in FIG. 1 is realized. This is an example.

In FIG. 20A, the binary signal series of "1" and "0" inputted to the input terminal 1000 is converted into 8-bit parallel data by the serial/parallel conversion circuit 1510.
This parallel data is transmitted via the data bus 1600.
It is connected to a data input/output terminal 1506 of a microcomputer MCS6800 manufactured by Hitachi, Ltd., for example. Furthermore, microcomputer 1
A fixed frequency oscillator and a fixed frequency oscillator 506 are connected via a data bus 1600 to the data memory and program memory 1505 of the microcomputer, and to the floating point signal processor 1502 and D/A converter 1503 described above. It is connected to a programmable timer 1507 consisting of a variable frequency dividing circuit. D/A
On the other hand, 1503 converts the serial signal from the serial output terminal of signal processing processor 1502 into an analog signal, and the output signal is passed through analog low-pass filter 1009 and output to output terminal 1010 of the modem.

As explained earlier, the signal processing processor 15
02 processes the function of block 1012 consisting of the low-pass filter and modulation circuit in FIG.
will be processed.

Similarly, in the hardware configuration of the modem receiver shown in FIG. 20B, the analog signal input to the input terminal 1013 passes through the analog band filter 1014,
The signal is input to the AGC circuit 1015. AGC circuit 10
The output of 15 is converted into a digital signal by A/D 1016. Floating point signal processing processor 1508 receives the serial signal from A/D 1016 at its serial signal input terminal and internally processes it. The microcomputer 1513 controls the modem receiving section and as described above, the
The functions of blocks 1028 and 1030 are realized. Further, the microcomputer 1513 is connected via a parallel data bus 1601 to a programmable timer 1515 consisting of a parallel-to-serial conversion circuit 1507, a microcomputer data memory and program memory 1512, a fixed frequency oscillator, and a variable frequency dividing circuit. teeth
It is connected to a latch circuit 1514 for providing a control signal for the AGC circuit via a data bus. A programmable timer regenerates the A/D 1016 sampling pulses.

As indicated above, the signal processing processor 150
8 implements the functional block 1029 shown in FIG. 1B.

As explained above, the data modem according to the present invention realizes functions suitable for signal calculation processing such as a filter and an automatic equalizer using a floating point calculation signal processing processor, and utilizes the wide dynamic range of its internal calculations. By using this method, we can obtain an automatic equalizer with the same performance, and furthermore, we can obtain a filter that is easy to design, and by assigning functions that are not suitable for signal processing calculations to the microcomputer, we can perform modem functions by combining the signal processing processor and the microcomputer. An optimal modem can be realized by sharing the functions.

[Brief explanation of drawings]

FIG. 1 is a modem configuration diagram showing the functions of the modem, FIG. 1A shows a modem transmitting section, and FIG. 2B shows a modem receiving section. FIG. 2 is a diagram showing the cascade connection configuration of digital filters and the input/output signal levels of each filter, and FIG. 3 is a block diagram showing an example of the overall configuration of a floating-point signal processing processor used in the modem of the present invention. 4 is a diagram showing the detailed configuration of the multiplier 14, FIGS. 5A and 5B are diagrams for explaining the bit formats of input data and internal calculation data of the adder/subtractor 15, respectively. Diagrams showing the detailed configuration of the adder/subtractor 15, FIG. 7A, B and FIG. 8A,
B is a diagram for explaining the operation of the shift circuit 76;
FIG. 9 is a circuit diagram showing one embodiment of the shift circuit 76, FIGS. 10A and B are explanatory diagrams regarding data overflow, and FIG. 11 is a specific diagram of some elements 85, 87, and 89 of the output correction circuit. A diagram showing the circuit configuration,
12A to 12B are diagrams showing changes in floating point data in each part of the signal processing processor,
13A to 13D are diagrams showing changes in fixed-point data, FIG. 14 is a diagram showing a specific circuit configuration of the input selection circuit 60, and FIG. 15 is a diagram showing the input selection circuit 61.
16 is a diagram showing a specific circuit configuration of the output switch circuit 17, FIG. 17 is a diagram showing the dynamic range of the digital signal processing processor, and FIG. 19 is a diagram showing a transversal filter which is a main part of an automatic equalizer, and FIG. 20 is a configuration diagram of a modem showing one embodiment of the present invention. . 1000, 1013...Input terminal, 1001...Scrambler, 1002...Differential encoder, 1003,
1004, 1020, 1021...low-pass filter,
1005, 1006...Modulation circuit, 1007...Adder, 1008...D/A converter, 1009...Analog low-pass filter, 1010, 1027...Output terminal, 1014...Band filter, 1015...AGC
Circuit, 1016... A/D converter, 1017... Power calculation circuit, 1018, 1019... Demodulation circuit, 10
22...Timing extraction circuit, 1023...Auto equalizer, 1024...Identification judgment circuit, 1025...Differential decoder, 1026...Descrambler, 1, 5, 6...
Memory, 2... Program counter, 3... Instruction register, 4... Control circuit, 7... General purpose register, 8... Selection circuit, 9, 10, 11, 12... Register, 14
...Floating point type multiplier, 15...Floating point type adder, 16...Accumulator, 17...Switch circuit,
18...Code register, 30...Output register, 3
1... Input register, 32, 33, 35... Shift register, 36... Counter, 37... Status register, 40... Control circuit, 41... Function control circuit, 42... Clock pulse generation circuit.

Claims (1)

[Claims] 1. A first signal converter that converts a data signal to be transmitted into a first digital signal, and a first signal converter that receives the first digital signal and performs signal processing including at least filtering and modulation. a transmitting unit having a signal calculation unit; a second signal conversion unit that converts the output of the first signal processing calculation unit into a transmission signal; and converts the received signal of the transmission signal into a second digital signal; a third signal converter that inputs the output of the third signal converter and performs signal processing including at least demodulation, filtering, and equalization; In a data modem comprising a receiving section having a fourth signal converting section that converts the data signal to the same signal as the data signal to be transmitted, the first and second signal calculating sections each have an exponent display section and a mantissa display section. become the first and second
means for supplying data; floating-point data multiplication means for adding the exponent display parts of the first and second data together and multiplying the mantissa display parts to output an operation result; and the operation of the multiplication means. floating-point data addition/subtraction means to which a result is supplied as one input; data accumulation means for holding the result of the calculation by the addition/subtraction means; a second data bus for inputting the output of the accumulating means to the adding/subtracting means, and switching means connected between the accumulating means and the first and second data buses. and a first signal processing processor having a control means for controlling the operation of each of the above elements according to a program, and a plurality of external terminals connected to the first data bus via an input register and an output register. wherein the first and fourth signal converters are configured with a second signal processing processor that operates independently of the first signal processing processor and is connected to the plurality of external terminals. A data modem using a signal processing processor characterized by: 2. A data modem using a signal processing processor as described in item 1, wherein the second signal processing processor is a processor that handles data in fixed-point representation. 3 In the description of paragraph 1, the first
The signal processing processor has coefficients Ci (i=1,...N),
A data modem using a signal processing processor is characterized in that, when the input sample value is X _o , Y _o = _N 〓 ⁱ⁼¹ CiX _o-1+1 performs program processing for performing the function of a transversal filter.