JPS60167551A - Data modem using signal processor - Google Patents

Abstract

PURPOSE:To obtain an automatic equalizer of high performance and also a filter which is easily designed by realizing a function suited to the signal processing of the filter, the automatic equalizer, etc. for a data MODEM by a floating decimal point arithmetic signal processor and making use of a wide dynamic range of the internal operation. CONSTITUTION:A digital signal processor performs a floating decimal point operation by a multiplier 14 and adder/subtractor 15. When the 16-bit data are fetched to the adder/subtractor 15 from an X bus 25, a Y bus 26 and a D bus 20 respectively, the lower 4 bits of input data of a mantissa part must be added with ''0'' through an input selection circuit of the adder/subtractor 15 since no coincidence is obtained for the number of bits of the data of the mantissa part. Furthermore some contrivances are given to an input selection circuit which converts data to increase a dynamic range as well as to an output switching circuit 17 in the digital signal processor in order to realize an MODEM easily. Thus the processor can perform also a fixed decimal point operation by the designation of a program.

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a data modem (modulator/demodulator) configured using a signal processing processor with a floating point arithmetic function. [Background of the Invention] As shown in FIG. 1, a modem modulates data or facsimile signals consisting of II I H and "o" signal series into a signal form suitable for a voice telephone circuit (transmission section) to transmit voice signals. and demodulates the signal from the voice line (
It has the function of converting the modem into the original ']", "O" signal sequence by converting it into the original ']", "O" signal sequence.Recently, a method of configuring this modem with a processor dedicated to signal processing has begun to appear.The signal processing processor is a program・It is configured as an LSI with a built-in dedicated multiplier and adder/subtractor to process memory and data at high speed.
C) The functions of the Yumu modem, which can be adapted to various uses such as an echo canceller and is an effective means for configuring a modem, will be explained with reference to FIG. In FIG. 1, the data or facsimile signal input to the input terminal 1000 is r 1.71゜rr.
A signal consisting of an On binary series is randomized by a scrambler 1001 and subjected to predetermined code conversion by a differential encoder 1002. The output of the differential encoder is so1+. The two-dimensional data is decomposed in the Y-axis and Y-axis directions, passes through low-pass filters 1003 and 1004 to remove unnecessary components, and is multiplied by a carrier wave of a specific frequency in modulation circuits 1005 and 1006. Y in each adder 1007
Axis and Y-axis components are added. From the scrambler 1001 to the adder 1007 are executed by digital operations, and D
/A (digital-to-analog converter) 1008. After passing through an analog low-pass filter 1009, a signal suitable for an audio line is output to an output terminal 1010. On the other hand, in the receiving section, an analog signal transmitted through the audio circuit enters an input terminal 1013, passes through an analog bandpass filter 1014, and enters an AGC (automatic gain control) circuit 101.
The signal is amplified to a predetermined amplitude level at step 5 and converted into a digital signal by an A/D (analog-to-digital converter) 1016. This digital signal is connected to the AGC circuit 10 on one side.
15 control signals are input to the power calculation circuit 1017, and the other is input to the demodulation circuit 10 to demodulate the input signal.
18. 1019, the Y-axis and Y-axis component waveforms are obtained. 6 Low-pass filters 1020° 4-1021 shape each waveform, and the automatic equalizer 1
At 023, the waveform distorted by the audio line is compensated and a waveform equal to the original transmission signal is input to the identification determination circuit 1024.
Differential decoder 1025. r equal to the original transmitted data or transmitted facsimile signal through desk lamp 1026
A binary sequence signal of r 1 u and rr Q n is obtained at the output terminal 1027. The timing extraction circuit 1022 is A
/D sampling pulse is extracted from the output signal of one normal low-pass filter 1020, 1021. Furthermore, the automatic equalizer 1023 automatically follows the characteristic of the control signal obtained from the discrimination determination circuit 1024 in accordance with the characteristic variation of the audio circuit. As explained above, the modem has a signal processing operation section such as a filter, a modulation/demodulation circuit, an automatic equalizer, etc. indicated by 1021° 1029, and a signal conversion section such as a scrambler, differential code decoder, etc. indicated by 1011° 1017.1028. Its functions are divided into In this way, the main function of a modem is the signal processing calculation section.
This is a device to which a signal processing processor can be fully applied. However, if a conventional signal processor is applied as is to a modem, the range of numerical values that can be handled (dynamic range) is narrow, making design difficult, and in some cases it may not be possible to realize a modem. This is because conventional signal processors use a fixed-point format and cannot have a wide dynamic range. Let us briefly discuss the problems with modem configurations when using conventional fixed-point signal processors. As shown in FIG. 1, the modem includes various filter circuits. For example, the transfer characteristic H(Z)EHl(Z)・H2(Z)・H3(Z) −1
Let us consider that a digital filter having the following equation (1,)YHt(Z) (+=1.2.3) is the transfer characteristic of each partial filter) is operated in a fixed-point arithmetic format. In filter design, we usually do not construct a filter with the characteristic H(Z) directly, but instead calculate each factor Ht (z).
(For example, Bjquad filter, etc.) and the circuits are connected in cascade. In this case, as shown in FIG. 2, H1(Z). The signal level diagram of the filter is different when connecting in cascade in the order of H2 (z), I-(3 (z) and when connecting in cascade in the order of 82 (Z), H1 (Z), H3 (Z) .In the A-type configuration, the signal level at point b decreases, so S/
N (signal component vs. rounding noise) must be taken into consideration when designing. Furthermore, in the B-type configuration, it is necessary to design it so that no signal overflow occurs at point b. If the range of numerical values to be handled as shown in the figure can be expressed in fixed-point representation, a filter can be constructed, but if the dynamic range is narrow and the above level diagram cannot be realized,
A filter would not be possible. 7- In this way, when a modem is configured using a fixed-point signal processor with a narrow dynamic range, the parameters of the filter that can be realized are limited. [Object of the Invention] An object of the present invention is to solve the above-mentioned problems when a modem is configured with a signal processing processor. [Summary of the Invention] In order to achieve the above object, the present invention is characterized in that a modem is configured using a floating point signal processor with a wide dynamic range, and there are no restrictions on the parameters that can be realized. More specifically, the digital signal processor forming a part of the present invention includes a first . means for supplying the second data; floating-point data multiplication means for adding the exponent display parts of the second data and multiplying the mantissa display parts to output the calculation result; a decimal point data addition/subtraction means, a data accumulation means for holding the calculation result of the addition/subtraction means, a first data bus connected to the data supply means, the multiplication means, and the addition/subtraction means; a second data bus for inputting the output of and control means for controlling the operation of the controller. [Embodiments of the Invention] Hereinafter, embodiments of a signal processing processor that is a part of the modem of the present invention will be described with reference to the drawings. The relationship between the signal processor and other components of the modem will be explained later with reference to FIG. FIG. 3 is an overall configuration diagram of a digital signal processor used in a modem according to the present invention, in which 1 is a memory for storing programs, 2 is a program counter, and 3 is a program counter for instructing the read address of the program memory. ”
2. Instruction register connected to program memory 1; 4;
is a control circuit that generates various control signals S for operating the processor from the instruction word read into the instruction register 3. In this embodiment, the instruction word stored in the memory 1 consists of, for example, 22 bits, each containing an operation code, data, address or address control information. The program counter 2 and instruction register 3 are connected to a 16-bit data bus (D bus) 20. 5.6 is a memory for storing data, and 7 is a general-purpose register. Memory 5.6 has one side for random access.
Memory (RAM), the other is read-only memory (ROM)
It can be done. Further, each memory may be a composite of a plurality of small capacity ROMs or RAMs. The memory stores 16-bit data, and each data is read out to the 16-bit X bus 21 or Y bus 22 via the selection circuit 8. 9 and 10 are registers specifying lower addresses of the data memories 5 and 7, respectively;
11 and 12 are registers that designate the upper address of the memory. Note that the register 11 gives the upper address of the data to be read to the X bus 21, and the register 12 gives the upper address of the data to read to the Y bus 22 or the address of the general-purpose register 7, and these registers are given instructions. Address information is given from register 3 via data bus 23. 14 is a floating point multiplier that multiplies the two data - given from the X bus 21 and the Y bus 22, and outputs the result to the P bus 24. Two input data X. It includes a register for holding Y, and the two unoperated data X and Y are directly transferred to the X bus 25. Output to Y bus 26. Reference numeral 15 denotes a floating point arithmetic type adder/subtractor, which receives the output data X, Y, P of the multiplier 14 and a data bus 20.2.
The data D and A of No. 7 are input, and the calculation is performed, and the result is output to the accumulator 16. 17 outputs the floating point data latched by the accumulator 16 to the 20-bit data bus (A bus) 27-11=, and also converts the above data into 16-bit data and outputs it to the D bus 20. A switch circuit 18 is a state code register connected to the multiplier 14 and the adder/subtractor 15, and stores a state code related to the results of these operations. 30 is an output register for outputting 16-bit data on the data bus 20 to the external terminal D O-D 16 in parallel; 31 is for capturing 16-bit data from the external terminal to the data bus 20 in parallel. is the input register of Further, 32 is a 16-bit shift register for taking in serial input data from the terminal SI in synchronization with the input clock of the terminal 5ICK while the input pulse of the terminal 5IEN is '1'', and 33 is the input pulse of the terminal 5OEN. shows a 16-bit shift register for serially outputting data to the terminal SO in synchronization with the input clock of the terminal 5OCK during the period II IH. 35 is a register for controlling the operating state of the processor, 36 is a counter to which the number of repetitions is set when the processor is caused to repeatedly execute an instruction by a repeat instruction, and 37 is a register for controlling the operating state of the processor. indicates a status register indicating the internal state of the processor.The contents of registers 35 and 37 are data bus 20 and 37, respectively.
Terminal. -Dl, it is possible to write and read from the outside. 40 is a control circuit for controlling interrupts to processor operations and input/output operations; for example, terminals 5IEN, 5O
The shift registers 32 and 33 are made operational by the rising edge of the input signal to EN, and the program is interrupted by the falling edge of each signal. Also, the registers 30 and 31 are activated by the rising edge of the input/output signal to the terminal IE, and their It operates to interrupt the program at the falling edge. 41 is a function control circuit that controls processor operation according to signals from an external control device (for example, a microcomputer); for example, a DMA transfer mode acknowledgment signal is sent from the terminal TXAK, and a parallel input/output data A signal indicating the transfer direction, a signal indicating that an external device has selected this processor from terminal C8, and a signal specifying the test operation mode from terminal TEST. Receives a reset signal from R8T, receives an operation control signal from an external device from terminal F o-a, and receives terminal T x
A parallel data transfer request signal is output from RQ. Terminal Bit Ilo indicates a bidirectional input/output terminal for inputting/outputting data one bit at a time. 42 is a clock pulse generation circuit, which receives a basic clock from an external circuit via a terminal O8C, generates various internal clocks necessary for processor operation based on this, and also receives a basic clock from an external circuit through a terminal O8C.
'Outputs the clock for synchronizing the internal operation of the processor and the external system to YNC. Next, the multiplier 14 and the adder/subtractor 15 will be further explained with reference to FIGS. 4, 5, and 6. The multiplier 14 receives 16-bit data from the X bus 21° bus 22 as shown in FIG. These data are stored in memories 5, 6 . It is given from the general-purpose register 7 or the data bus 20. As shown in FIG. 5(A), the lower 4 bits of this data are the exponent part, and the higher 12 bits are the mantissa part. The bit in this position is the sign bit. Also, the decimal point is between 216 and 214. As shown in Figure 4,
The exponent data and mantissa data given from the bus 21 and the Y bus 22 are held in registers 5, 52, 53, and 54, respectively, and the exponent data in registers 51, 52 are added by the adder circuit 55. It is output to the P bus 24 via a 4-bit output register 56. On the other hand, the mantissa data in the registers 53 and 54 are input to a multiplication circuit 57 having a circuit configuration similar to that of normal fixed-point arithmetic, and the multiplication result is sent to the P bus 24 via the output register 58. Output. In other words, the calculation output of the multiplier 14 is input to the adder/subtractor 15 as 20-bit data consisting of the lower 4 bits of the exponent part and the higher 16 bits of the mantissa part, as shown in FIG. 5(B). . Note that the outputs of registers 52 and 54 are sent to the X bus 25, and also to the register 51.
．． The output of 53 is sent to Y bus-15-26, each containing 16 bits of data and 2.0 bits of data.
．． 24 to 27, data D, P, and X. Y and A are input. Among these, data P. Y and D are input to a selection circuit 60 and a control signal S is input. One piece of data specified by is selected. Further, the data A and X are input to the selection circuit 61, and one data designated by the control signal S2 is selected. Here, input data D
, X, and Y are each 16-bit data shown in FIG. 5(A). As will be described later, when these 16-bit data are designated, the selection circuits 60 and 61 are configured to convert these data into 20-bit data as shown in FIG. 5(B) and output it. . This bit conversion differs depending on whether the input data D, X, Y are fixed point data or floating point data, and the conversion operation is specified by the control signal S3. This allows the floating-point type adder/subtractor to process input data in fixed-point representation. Note that -16=control signal S1. S2. S3...Sn are output from the control circuit 4 in response to command words in the program. Let us assume that the output data from the selection circuit 60 is β (exponent part β, mantissa part βM), and the output data from the selection circuit 61 is α (indication part α, mantissa part αM). Exponent data α. is connected to the comparison circuit 63 via the selection circuit 62
and is compared in size with the exponent data β. Also, these exponent data α. , β and are also input to a subtraction circuit 64 and a selection circuit 65, respectively. Mantissa data α7
is input to the selection circuit 67.68 via the negation circuit 66, and the mantissa data β7 is directly input to the selection circuit 67.68. In this embodiment, the negation circuit 66 outputs data α and β.
This is provided in order to realize subtraction with ALU 75 having an adder configuration, which will be described later.In the case of an addition operation, the data αW passes through the negation circuit. The selection circuits 65, 67, and 68 each select one of the two inputs according to the output signal of the comparison circuit 63. The output of the selection circuit 65 is latched by a latch circuit 71, the output of the selection circuit 67 is latched by a latch circuit 72 via a shift circuit 69, and the output of the selection circuit 68 is latched by a latch circuit 73 using a timing signal C. The subtraction circuit 64 is also controlled by the output of the comparison circuit 63, and inputs α9. β. It operates by subtracting the smaller one from the larger one. The shift circuit 69 shifts the input data to the right by the number of bits corresponding to the output of the subtraction circuit 64 obtained via the selection circuit 70. This shift circuit 69
The operation is also controlled by another data E input to the selection circuit 70, and the number of shift bits is selected by the control signal S7. The outputs 6A+8B of the latch circuits 72 and 73 are shown in FIG.
), the addition result UM is input to a fixed-point arithmetic type adder (ALU) 75 operated by the control signal S8.
is applied to the leftward shift circuit 76. On the other hand, the output γ of the latch circuit 71 is input to one input terminal of a constant addition circuit 77 and a subtraction circuit 78. 79 is a zero detection circuit that judges the output UM of the adder 75, and when the output UM of the adder given in complement representation is a positive number, the zero detection circuit 79 judges the output UM of the adder 75. Count the number of consecutive pieces. If U, , I are negative numbers, count the number of consecutive <"i" bits following the above side bits. Output 01 of the zero detection circuit 79 is output by an output correction circuit 80 provided for data normalization and overflow prevention.
is applied to the shift circuit 76 via the shift circuit 76 to determine the number of bits to shift the data by the shift circuit. In addition, the output θ□ of the zero detection circuit 79 is also input to the other input terminal of the subtraction circuit 78, and the output UE of this subtraction circuit is sent to the exponent part of the accumulator 16 via the output correction circuit 80. Input to 16X. The mantissa part 16M of the accumulator 16 receives the output data L' from the shift circuit 76 corrected by the output correction circuit 80. The output correction circuit 80 outputs a zero detection circuit 79 according to the overflow detection signal ○VF outputted from the adder 75 and the underflow detection signal UNF outputted from the subtraction circuit 78.
A selection circuit 81 selects either the output θ1 of the constant adder circuit -19=77 output 0 A selection circuit 82 supplies one of the above to the shift circuit 76 as a shift bit number instruction signal O, and an overflow signal OvF.
is "1", 1 is added to the subtraction circuit output UE, and when this addition result LE also overflows, the signal EOV
an increment circuit 83 that outputs F; an exponent correction circuit 85 inserted between the increment circuit 83 and the exponent part 16x of the accumulator 16; a shift circuit 76 and the mantissa part 16M of the accumulator 16; A control circuit 8 that controls the operations of the mantissa correction circuit 87 inserted between the two correction circuits 85 and 87 and the two correction circuits 85 and 87 according to the signals UNF and EOVF.
It consists of 9. The adder/subtractor 15 having the above configuration operates as follows. The respective outputs α and β of the two input selection circuits 61 and 60 shown in FIG. 6(A) are 120− data in floating point representation, and their values are expressed by the following equation. Now α. 〉β. Two data α in the relationship. Assuming that an addition operation of β is performed, the addition result 2 is given by: The comparison circuit 63 compares the magnitude of α and β9, and selects the selection circuit 6.
5 selects the larger exponent part data α□, and the selection circuit 67 selects the smaller exponent part β. The selection circuit 68 selects the larger exponent α6 and the corresponding mantissa data α7, and the subtraction circuit 64 selects the larger exponent α9 to the smaller exponent β. Give a control signal to pull the yaw. During execution of the addition operation, the selection circuit 70 selects the output (α9−β) from the subtraction circuit 64, and the shift circuit 69 selects the output β from the selection circuit 67.
9 to the right (in the direction of the lower bits) by (α or -β9) bits. As a result, the latch circuit 7
1,72.73 each -(α.-β2) The output is γ=αE + eIL ”β7・2eB-α7
Then, the output U of the adder 75 that performed the operation of e188
M represents the mantissa part of equation (1). Therefore, the calculated value 2 at this stage is expressed by the following equation. The zero detection circuit 79 and the leftward shift 1 circuit 76 are for normalizing the adder output UM so that its absolute value becomes maximum. As shown in FIG. 7(A), the zero detection circuit 79
If the number 01 of consecutive "o"s (below the decimal point) following the sign bit of the data UM is detected by , and the shift circuit 76 shifts the data UM by O□ bits to the left (to the most significant bit side), the absolute value is the maximum mantissa data L
M is obtained. If UM is a negative number, it is only necessary to shift the number of consecutive +11 rr as shown in FIG. 7(B). In this case, for the exponent part data γ, the subtraction circuit 7
8 to calculate (γ-01), and use the output U as the normalized exponent value. If no overflow has occurred in the data UM, the output E of the increment circuit 83 will be equal to the normalized exponent value UE, and the normalization process is performed using the following formula: % The size of the exponent part γ is 4 bits. Then, the value that γ can represent using two's complement representation is limited to the range [+7>γ>−8]. Therefore, when normalizing the mantissa data, if you try to completely shift the data UM to the left by the value θ1 detected by the zero detection circuit, the value of (γ-01) on the exponent part will be -8. , which may cause an underflow in the subtraction circuit. At this time(
A signal (borrow signal) UNF indicating data underflow is generated from the subtraction circuit 78 that performs the calculation of γ-01). In the circuit of FIG. 6(B), when the signal UNF is generated, the selection circuit 8 selects the output θ2 of the constant addition circuit 77 in place of the input θ1, and the constant addition circuit 77 selects the data γ of the exponent part. The value obtained by adding the constant "8" to is data 0□
It should be output as . In this way, for example, when the value of γ is "-5", the value of θ2 is "3", so the number of shift bits of the mantissa data UM is limited to 3 bits, and the number of shift bits of the mantissa data UM after normalization is The value remains at the minimum value "-8". The operation of setting the exponent part to "-8" when the signal UNF occurs is performed by an exponent part correction circuit 85, which will be explained later with reference to FIG. 1J. The calculation result UM of the adder 75 is shown in FIG. 8(A). As shown in (B), if overflow occurs, =2
4- The true sign of the data appears at the carry output, and the most significant bit of the number appears at the sign bit position. Therefore, in this case, the operation of the selection circuit 81 and the zero detection circuit 79 is stopped by the overflow detection signal OVF,
The shift circuit 76 is caused to perform a 1-bit right shift 1~ operation, the increment circuit 83 is caused to perform an operation of U□(=γ)+1,
Data 2 may be manipulated as shown in the following equation. An example of the shift circuit 76 that performs the above operation is shown in FIG. This circuit operates on each bit 03 to θ of the shift bit number instruction data θ. It consists of an 8-bit shifter 761, a 4-bit shifter 762, a 2-bit shifter 763, and a 1-bit shifter 764, and the switches SW'a to SWo of each signal line of each thick are controlled by the corresponding control. Bits 03-θ. When is rr i rr, it is connected to the contact on the lower bit side. In addition, a 1-bit shifter 764
Each switch SWo receives an overflow detection signal OVF.
When is LL+, II, it is connected to the contact on the upper bit side, and the output line 1-18 of the sign bit is connected to the carry signal input terminal 765, realizing the above-described 1-bit right shift operation of the data. In the circuit of FIG. 6, when the overflow detection signal OVF of the adder 75 becomes 1111+, an overflow may also occur in the calculation result of (γ+1) by the increment circuit 83. In this case, the calculation result Z (=α
10β) means that an overflow occurred.

[7. If the product-sum operation is continued as it is, the absolute value of the output data obtained by the accumulator 16 will change as shown in FIG. 10(A), and will become a completely meaningless value. The control circuit 89 and the correction circuits 85 and 87 operate to fix the absolute value of the output data to the maximum positive or negative value when the above-mentioned overflow occurs in the calculation result 2, as shown in FIG. 10(B). FIG. 11 shows a specific example of its configuration. In FIG. 11, the exponent part correction circuit 85 includes two-man power AND gates 850 to 85 corresponding to input bits Lo to L3.
3 and two manual OR gates 860 to 863, and each bit signal is outputted to the accumulator 16x side through these gates. The other input terminal of the AND gate 853 to which the sign bit L3 of the exponent part data is input is an overflow detection signal E output from the increment circuit 83.
The inverted signal of OVF is input, and the underflow detection signal UNF from the subtraction circuit 78 is input to the other input terminal of the ○R game 1-863. Further, an inverted signal of the signal UNF is input to the other input terminal of each of AND gates 1-850 to 852 to which data bit LO-L2 is input, and OR gates 1-860
The signal EOVF is input to the other input terminal of 862. Signals EOVF and UNF are 111 gg at the same time.
Therefore, when the signal EOVF is "I", the output of the exponent part correction circuit 85 becomes [0111]=+7, making the exponent part the maximum value. Also, the signal UNF is 111
When H, [1000] = -8, and the above 0 = 0
Satisfies the exponent values of 2 and 27-ki. On the other hand, the mantissa correction circuit 87 outputs the sign bit L11 as it is and converts it into data bits 4 to Li. 2-man OR gates 871 to 87N and 2-man A
It is designed to be outputted via ND gates 881 to 88N. The output of the AND gate 891 of the control circuit 89 is given to the other input of each OR gate, and the output of the NAND gate 891 of the control circuit 89 is given to the other input terminal of each AND gate.
92 outputs are given. When the signal EOVF is "1", the mantissa data is a positive value, that is, the sign bit L
If 1.9 is '0'', AND gate 891 and NAND
The outputs of the gates 892 are both 1", and the output of the correction circuit 87 is the maximum positive value (O] 11... bow 1). Also, if the sign bit LiO is tz 1 sr, then NAN
Since the output of the D gate 892 is II OII, the output of the correction circuit 87 is the negative maximum value (1000...00)
becomes. When the signal EOVF is 'o', these correction circuits 85 and 86 output the input data L E +L M as they are as data F,), T-). 28- These output data L'Y, L' The signal is outputted to the A bus 27 via the accumulator 16 and the switch circuit 17, and is fed back to the selection circuit 61 of the adder/subtractor 15. From the above operation description, it can be seen that the digital signal processing that forms part of the configuration of the present invention In the processor, a multiplier 14 and an adder/subtracter 1
It can be seen that 5 can perform floating point operations. Here, data input from the X bus 21 or Y bus 22 to the multiplier 14 and data input from the multiplier 14 or A bus 27 to the adder/subtractor (ALU) 15 are based on the number of bits of input data and the receiving side port. Since the data bit numbers are the same, there is no change in bit position between the data, as shown in FIGS. 12(A) and 12(B). However, X bus 25. Y
Bus 26. When the 16-bit data from the D bus 20 is taken into the adder/subtractor 15, the number of bits of the mantissa data does not match, so the input selection circuits 60 and 61 of the adder/subtractor input the mantissa data as shown in FIG. 12(C). It is necessary to add 0'' to the lower 4 bits of the input data M. Also, the 20-bit adder/subtracter output obtained by the accumulator (ACC) 16 is output to the 16-bit D bus 20. In this case, as shown in FIG. 12(D), the switch circuit 17 discards the lower 4 bits of the mantissa part M, and replaces the 4 bits of the exponent part,
This requires an operation to convert the mantissa to 12-bit data. The digital signal processor that forms part of the configuration of the present invention includes an input selection circuit 60, 61 that performs a double data conversion operation and an output switch for the purpose of increasing the dynamic range in order to facilitate implementation of a modem. The circuit 17 has been further improved so that the processor can also perform fixed-point operations according to program specifications. Multiplication of fixed point data X and Y is performed in a mantissa data multiplication circuit 57 within the multiplier 14. In this case, as shown in FIG. 2(A), the upper 12 bits of the 16-bit input data X, 2 that enter the mantissa input registers 53 and 54 are treated as valid data. On the other hand, when adding or subtracting fixed-point data, the shift operation of shift 1 to circuit 69.76 in the adder/subtractor 15 is stopped according to the exponent in the program, and the result of operation of the mantissa obtained in this state is used. . The operation of the shift circuit 69 is stopped when an operation instruction for fixed-point data gives the numerical value "0" to the data line E in FIG. 6(A), and the selection circuit 70 selects the input from the data line E. The control signal S7 may be generated at the same time. To stop the operation of the circuit 76 to shift 1,
The numerical value "0" data may be applied to the data line F in FIG. 6(B), and the control signal Sf3 may be generated so that the selection circuit 82 selects the input from the data line F shown in FIG. 6(B). In addition and subtraction of the above fixed point data, the data input from the multiplier 14 or the A bus to the adder/subtractor 15 is the 13th
As shown in Figure (B), the 16-bit data of the mantissa can be sent in the same way as in the case of floating point arithmetic. X bus,
■Data input from the bus and D bus puts all bits into the mantissa as shown in Figure 13 (C), and the mantissa data obtained by the accumulator (ACC) is shown in Figure 13 (D). As shown, all bits are output to the D bus 20. FIG. 14 shows a specific example of the input selection circuit 60 of the adder-31=subtracter equipped with the above-mentioned bit conversion function. In this circuit diagram, P o+P1□, Y O-'Y15w D o-
Dta is P bus 24. Y bus 26. D bus 20
The exponent part Po-P3 of the data P is input to the switch 601,
The four output terminals of switch 601 are connected to terminal Co-Ca of switch 603. Each bit of data Y, D and bit P of the mantissa part of data P
4 to Pill are input to switch 602, and switch 6
The output terminals of the upper 12 bits of 02 are connected to the output lines β8 to β□8 of the upper bits of the data ρ, and the output terminals of the lower 4 bits are connected to the terminals C4 to C7 of the switch 603 and the other input terminal of the switch 601. has been done. The switch 603 has eight output terminals connected to the output lines β0 to β8 of the lower bits of the data β, and four output terminals that provide the state rr On.
terminals 604. 605 is a control signal S□+ given from the control circuit 4 according to the command word of the program.
This is a logic circuit that generates drive signals 60A, 60B, and 60G for the switches 601, 602, and 603 based on the logic circuit 32-. When data to be selected is specified by the control signal S1, the switches 601 and 602 are operated by the signals 60A and 60B, and one of the data P, Y, and D is selected. At this time, if the control signal S2 instructs floating point arithmetic,
The switch 603 connects the output lines β0 to β3 to terminals co-C3.
, output lines β4 to β7 are connected to terminals C4 to C7 (input data P
is selected) or to terminal 604 (when input data Y or D is selected). If the control signal S2 instructs fixed-point arithmetic, the output lines β0 to β3 are connected to the terminals 604 and the output lines β4 to β7 are connected to the terminals C4 to C7, regardless of the input data. FIG. 15 shows a specific circuit configuration of another input selection circuit 61. This circuit is the same as that shown in FIG. 14 except that there are two types of inputs, the A bus and the X bus, and a description thereof will be omitted. FIG. 16 shows a switch circuit 17 connected to an accumulator 16.
The specific circuit configuration is shown below. In this circuit, the 20-bit outputs from the accumulator GO to G1 . ] is switch 17
1 input terminal is input. The switch 171 has 16 output terminals connected to each of the signal lines DO to D15 of the data bus 20, and the connections between the input terminals and the output terminals are controlled by output signals 17A and 17B of the logic circuit 172. When the control signal S2 according to the program command indicates floating point arithmetic, the switch 171 is controlled by the signal 17B to connect the lower 4 bits of the output side signal lines DO to D3 to the input signal line G □
-03 for fixed-point calculations]. ~
Connect D3 to G4-G7. Signal 17A controls output of upper bit data to data bus 20. According to the signal processing processor that forms part of the data modem of the present invention, it is possible not only to perform operations on fixed-point data or floating-point data as described above, but also to convert the operation results obtained in floating-point format into fixed-point data according to program instructions. It is also possible to perform calculations by converting fixed-point format data into floating-point format data. This function allows the signal processing processor to connect the data bus 20 and the input/output interfaces 30 to
This is extremely convenient when exchanging data with an external device via 33. When configuring a modem using a signal processing processor, the external device handles data in a fixed-point display format, and if the floating-point calculation result of the signal processing processor described in item 1 is output as is, This is because a special device for converting the data format is required outside the processor. Conversion from floating point display to fixed point display (hereinafter referred to as F
(referred to as LFX) is performed as follows. First, when the floating point representation data obtained by the accumulator 16 is αE A=α7·2, the exponent part is α. A data line 1=βW·35−βE 2 which satisfies the relationship 〈β and whose mantissa has a value βヮ=0 is stored at a specific address in the data memory 5 or 6. This address is made to correspond to the address part of the instruction word of FLFX. When this command is executed, the selection circuit 8 outputs the data y read from the memory to the Y bus 22, the selection circuit 60 selects the input from the Y bus, and the selection circuit 61 outputs the data y read from the memory to the A bus. 27, the selection circuit 82 selects the input data F (=rO''), and various control signals are generated so that the output switch 17 operates to connect the input signals G4 to G01B to the data bus 20. If you do this, when you execute the FLFX command, 2
An operation is performed between two floating point data A and yl,
In the accumulator 16, z=A+y. −(β2−αE) βE = [0+α7·2]·2 (7) The calculation result of βE is obtained. This data has been normalized using 2 as a reference value for a part of the exponent 36, and the data of the mantissa output to the data bus 20 = (β or -αE) αya/2 can be handled as fixed-point data. Normally, it is not possible to accurately know the optimal value of βE for the internal calculation result A, so it is better for the modem designer to select a slightly larger value for β6. However, β. It must be noted that if the value of is set too large, the precision of fixed-decimal data will decrease. When executing the above F L F X, the exponent part β of the conversion data y1 stored in the memory in advance
The exponent part α of the operation result 2 than Yu. If it becomes larger, an overflow of the mantissa in equation (7) will occur. In this case, the operation of the output correction circuit 80 described above allows the absolute value of the fixed-point data to be fixed at the maximum positive or negative value. On the other hand, for example, the operation of internally converting fixed-point data given from an A/D into floating-point data can be performed as follows. First. An instruction to transfer the fixed-point data input to the input register 31 to the accumulator 16 is executed. In this instruction, the bit position of 16-bit fixed point display data D given to the selection circuit 60 via the data bus 20 is converted into the mantissa part βW by the operation of the selection circuit 60 in 1.
7, shift circuit 69, latch circuit 72. Adder 75. The signal is input to the mantissa part 16M of the accumulator 16 via the shift circuit 76 and the correction circuit 87. In this case, shift 1 to circuit 69 and adder 75 are each controlled to allow input data to pass through. Next, convert from fixed-point display to floating-point display (hereinafter,
FXFL). When this instruction is executed, the selection circuit 61 outputs the accumulator output given from the A bus 27, that is, the fixed-point data A described above, α7. α. Select as. Further, the selection circuit 60 selects the conversion data y2 specified by the address part of the F X F L instruction and read from the memory 5 or 6 to the Y bus 26 as the output β8°β. In this conversion data y2, for example, the mantissa part β7 is zero and the exponent part β
9 has a reference value selected from the range of values [+7 to -8]. Unlike when executing other instructions, the selection circuit 62 receives input β when executing the FXFL instruction. The comparison circuit 63 generates a control signal S4 to select
Both inputs are β. shall be. In this case, the mantissa selection circuit 67 selects the input α7, the selection circuit 68 selects the input βヮ, and the exponent selection circuit 65 selects the input β. let them choose. In addition, the input data E is input to the selection circuit 70 by the control signal S7.
= Select rOJ and suppress the data shift 1 to operation of the rightward shift circuit 69. Due to the above control operation, the output of the latch circuits 71, 72, 73 becomes γ=βE le A= αMle B = O
becomes. The data eA and 8.3 are input to the adder 75, and the addition result UM (-αM) is shifted by 01 bits in the decimal point position under the operation of the zero detection circuit 79 and the leftward shift 1-circuit 76. The accumulator 16 obtains data expressed as θ1 (β.-〇,) z=[α7.2].2 (8)39-. This formula is
Data A = αヮ in fixed decimal point representation is exponent β. This means that it has been normalized to the standard and displayed as a floating point number. Therefore, by using the data obtained by the accumulator 16 with the instruction FXFL, subsequent calculations can be performed in floating point format, and filter calculations with a wide dynamic range can be performed. Although the FXFL instruction was executed after the data in the input register 31 was once stored in the accumulator 16, the fixed-point input data and conversion data y2 were transferred to the X bus 25 and the D bus 2.
By inputting 0 to the adder/subtractor 15, it is also possible to design data conversion to floating point representation with one instruction. As mentioned above, the digital signal processor that forms part of the data modem of the present invention can handle fixed-point and floating-point image format data, and moreover, when normalizing floating-point display data, there is an underflow in the exponent part. When it occurs,
Since the normalization operation can be performed with the exponent value fixed to the minimum value, the calculation method can be automatically switched to floating-point calculation format when the internal calculation data 40= is large, and to fixed-point calculation format when it is small. , it is possible to obtain an extremely wide dynamic range, and it can be sufficiently applied to data modems. In other words, the internal data of the adder/subtractor has a mantissa part of 16 bits 1-
When one exponent part consists of 4 bits, the exponent part γ can handle numerical values in the range [+7 to -8] in two's complement representation. If all operations are processed in floating-point format, the dynamic range is as follows, according to the diagonal lines in Figure 17, when the normalized number of bits O for the mantissa of the operation data is in the range , by fixing the exponent L2 after normalization to -8, it is possible to switch to fixed-point arithmetic. Therefore, as shown in Figure 17, the dynamic range is 31 bits in total, and fixed and floating The range of numerical values that can be handled is significantly expanded compared to the case where only one of the two is used. In cycle 202, data is read from the data memory and arithmetic is performed by the multiplier.Instruction cycle 203
Then, addition and subtraction are performed between the multiplication result and the accumulator data (A bus output), and the operation result is output to the accumulator in cycle 204. The operations of these four steps are repeated in each instruction cycle with a one-step shift, and when the product-sum operation has been completed a predetermined number of times m, the operation result T is transferred to the data bus 2 by instruction F.
and sent to the data memory 5 or an external circuit. The parallel operation of the processor by pipeline control is achieved by connecting the multiplier 14 and the adder/subtracter 15 in series, and by the fact that the register (sixth This is possible by arranging latch circuits 71 and 72 (corresponding to this in the figure). If a modem is configured using the floating point signal processor as described above, it is not only possible to easily configure a cascade connection of filters, but also to easily realize an automatic isolator, as shown above. The first automatic equalizer has the function of automatically estimating the amount of distortion from the waveform distorted by the voice telephone line and returning it to the original undistorted waveform.
The main part includes a 1 Herans universal filter as shown in FIG. In FIG. 19, an input signal X is input to an input terminal 1400. are each 1 sampling delay circuit 120〇−+, 1200
-2. ...1200-(N-1), and the output of each delay circuit is each coefficient C1, C2..., C
Multiplication circuit with N 1100-1゜110CI-2, ] 1
00-3. ..., multiplied by 1100-N,
The respective outputs are added by an adder 1300 to produce an output Y as shown in the following equation. is obtained at the output terminal 1500. As shown in Fig. 1, each coefficient C,,C2,...43
- CN L:): Its value changes according to voice line fluctuations. The above formula is a case where the product-sum operation is repeatedly executed N times,
When N is large and the dynamic range of calculation is narrow, overflow often occurs. Even in such calculations, if the model 11 is configured using a floating-point calculation type signal processor, overflow is less likely to occur in the automatic equalizer, and high-performance automatic equalization characteristics can be obtained. FIG. 20 shows an embodiment of a data modem configuration according to the present invention using the floating point signal processor described below. In FIG. 20, the transmitting section (A) is an example in which the function corresponding to the transmitting section in FIG. 1 is realized using the above floating point signal processing processor, and the receiving section (B) corresponds to the receiving section in FIG. This is an example of realizing this function. '''l input to input terminal 1000 in Fig. 20(A)
The binary signal series of
510, it is converted into 8-bit parallel data. This parallel data is connected to a data input/output terminal 1506 of a microcomputer MC36800 manufactured by Hitachi, Ltd., for example, through a data bus 1600. Further, the microcomputer 1506 connects the microcomputer data memory and program memory 1505 . and a programmable timer 1507 consisting of a fixed frequency oscillator and a variable frequency divider circuit for producing sampling pulses for the floating point signal processor 1502 and D/A converter 1503 described above. D/Al3O
3, on the other hand, converts the serial signal from the serial output terminal of the signal processing processor 1502 into an analog signal, and the output signal is passed through an analog low-pass filter 1009 and outputted to the output terminal 1010 of the modem. As described above, the signal processing processor 1502 processes the function of block 1012 consisting of a low-pass filter and modulation circuit in FIG. 1(A), and the function of block 1011 is processed by the microcomputer 1506. Similarly, in the hardware configuration of the modem receiver shown in FIG. 20(B), the analog signal input to the input terminal 1013 passes through the analog bandpass filter 1014, and
5 is input. The output of the AGC circuit 1015 is A/D
1016, it is converted into a digital signal. Floating point signal processor 1508 receives the serial signal from A/D 1016 at its serial signal input terminal and internally processes it. The microcomputer 1513 controls the controller 1 of the modem receiving section and as described above, the controller 1513 shown in FIG.
The functions of blocks 1028 and 1.030 in B) are realized. In addition, the microcomputer 1513 connects the parallel to serial conversion circuit 1.507 via the parallel data bus 1601.
, a data memory and a program memory 1512 of the microcomputer, a programmable timer 1515 consisting of a fixed frequency oscillator and a variable frequency dividing circuit, and a latch circuit 1514 for providing a control signal for the AGC circuit via a data bus. It is connected to the. A programmable timer regenerates the A/D 1016 sampling pulses. As shown above, the signal processing processor 1508 implements the functional block 1029 shown in FIG. 1(B). As explained above, the data modem according to the present invention realizes functions suitable for signal calculation processing such as filters and automatic isolators using a floating-point signal processing processor, and utilizes the wide dynamic range of its internal calculations. , by obtaining a high-performance automatic equalizer, and furthermore by obtaining a filter that is easy to design, and by assigning functions that are not suitable for signal processing calculations to a microcomputer, the modem function can be combined with a signal processing processor and a microcomputer. It is possible to realize an optimal modem by dividing the functions between the two.

[Brief explanation of drawings]

Figure 1 is a modem configuration diagram showing the functions of the modem, Figure 1 (A
) shows a modem transmitter, and FIG. 2(B) shows a modem receiver. FIG. 2 is a diagram showing the cascade connection configuration of digital filters and the input/output signal levels of each filter, and FIG. 3 is a block diagram showing an example of the overall configuration of a 47-floating point signal processor used in the modem of the present invention. 4 is a diagram showing the detailed configuration of the multiplier 14, and FIGS. 6(A) and (B) are diagrams showing the detailed configuration of the adder/subtractor 15, FIG. 7(A), (B) and FIG. 8(A),
(B) is a diagram for explaining the operation of the shift circuit 76, FIG. 9 is a circuit diagram showing one embodiment of the shift circuit 76, and FIG.
Figure (A). (B) is an explanatory diagram about data overflow, No. 11
The figure shows a specific circuit configuration of some elements 85.87°89 of the output correction circuit, and FIGS. 12(A) and 12(B) show changes in floating point data in each part of the signal processing processor. 13(A) to 13(D) are diagrams showing changes in fixed-point data, and FIG. 14 is an input selection circuit 6.
15 is a diagram showing a specific circuit configuration of the input selection circuit 61, FIG. 16 is a diagram showing a specific circuit configuration of the output switch circuit 17, and FIG. 17 is a diagram showing a specific circuit configuration of the output switch circuit 17. 18 is a diagram showing the dynamics of a digital signal processing processor, FIG. 18 is a time chart 1 to 1 to explain the operation characteristics of the above-mentioned processor, and FIG. 19 is a transversal filter which is the main part of an automatic equalizer. FIG. 20 is a configuration diagram of a modem showing one embodiment of the present invention. 1000.1013...Input terminal, 1001-X scrambler, 10o2...Differential encoder, 1003°100
4.1020.1021...Low pass filter, 1005
．． 1006 peak modulation circuit, 1007-...adder, 100
8...D/A converter, 1009-analog low-pass filter, 1010.1027 output terminal, 1014...bandpass filter, 1o15...AGC circuit, 1016...
A/D converter, 1o17...Power calculation circuit, 1018
, 101.9-Demodulation circuit, I O22... Timing extraction circuit, 1o23... Automatic equalizer, 1024... Identification determination circuit, 1o25... Differential decoder, 1026...
Descrambler, I, 5.6...Memory, 2...Program counter, 3...Instruction register, 4...Control circuit, 7...General purpose register, 8...Selection circuit, 9.10
, 11.12. Register, I4... Floating point type multiplier, 15... Floating point type adder, 16...
Accumulator, 17...Switch circuit, 18...Code register, 30...Output register, 31...Input register, 32, 33.35...Shift register, 36...
Counter, 37...Status register, 40...
・Control circuit, 41 ・Function control circuit, 42 ・
...Clock pulse generation circuit. D rI”””E 13th 0

Claims (1)

[Claims] (1) A first signal converter that converts a data signal to be transmitted at a low rate into a first digital signal, and a first signal converter that receives the first digital signal and performs signal processing including at least filtering and modulation. a transmitting unit having a signal calculation unit; a second signal conversion unit that converts the output of the first signal processing calculation unit into a transmission signal; and converts the received signal of the transmission signal into a second digital signal; a third signal converting section that receives the output of the third signal converting section and performs signal processing including at least demodulation, filtering, and equalization, and transmits the output of the second signal calculating section. a data modem comprising a receiving section having a fourth signal converting section that converts the data signal into the same signal as the data signal to be processed, wherein the first and second signal calculating sections each include an exponent display section and a mantissa display section. means for supplying first and second data; floating-point data multiplication means that adds the exponent display parts of the second data and multiplies the mantissa display parts to output the calculation result; and floating-point data to which the calculation result of the multiplication means is supplied as one input. a first data bus connected to the data supply means, the multiplication means, and the addition/subtraction means; "Second for inputting to the second addition/subtraction means
data bus, the accumulation means, and the first data bus. a switching means connected between the second data bus and a control means for controlling the operation of each of the above elements according to a program;
``2.The first signal processing processor includes a plurality of external terminals via an input register and an output register connected to the first data bus, and the first and fourth signal converters are configured as ``- 1. A data modem using a signal processing processor, comprising: a second signal processing processor that operates independently of the first signal processing processor; and a second signal processing processor connected to the first signal processing processor through a plurality of external terminals. 2. A data modem using a signal processing processor according to item 1, wherein the second signal processing processor is a processor that handles data in fixed-point representation. 3. In the description of item 1, the first signal processing processor of the second calculation unit has a coefficient C1 (i=1°...N), and when the input sample value is Xn, Yo-Σ Ci x, -, +1
A data modem using a signal processing processor, characterized in that it performs program processing to perform the function of a transversal filter.