JPS59117638A - Operating device - Google Patents

Abstract

PURPOSE:To execute a square root calculation by a small number of steps, by inputting and outputting data between three registers and an arithmetic circuit. CONSTITUTION:The value deriving a square root is set to the second register 2. Upper two bits of the second register 2 are set to the first register 1, and the data of second register 2 is shifted upward by two bits. Constant 01 is set to the third register 3. Data of the first register and data of the third register are subjected subtraction in an arithmetic device 4. If data of the first register is larger than or equal to data of the third register, upper two bits of the second register are set to lower two bits of the first register, and output data of a selecting circuit 5 is set to remaining upper bits of the first register. The square root extracting arithmetic for two bits is executed in every one step.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an arithmetic device, and particularly to square root arithmetic.

[Prior art]

In conventional arithmetic circuits, in the calculation of a square root, a shift operation, a subtraction operation, a correction operation of the subtraction result, a setting operation of the square root, etc. are performed by a microprogram or software. Therefore, 3 to 6 steps are required to perform square root calculation for every 2 bits, and high-speed calculation processing is not possible.

[Purpose of the invention]

In the calculation of the square root, the present invention uses a method of square rooting each two binary bits by subtraction.

The carry (down) signal that is the output of the arithmetic unit indicates the magnitude relationship between two input data during a subtraction operation.Therefore, as in the past, the subtraction result is set in a register and the magnitude relationship is checked by the sign or minus of the data. 2. Determine the data to be set in different registers depending on the magnitude relationship based on the carry (down) signal, instead of 2.
By performing the bit shift operation at the same time as the arithmetic operation, υ
The object of the present invention is to provide a high-speed arithmetic device that can perform square root calculation in one step, which conventionally required 3 to 6 steps.

[Structure of the invention]

The apparatus of the present invention includes at least three registers, a first register, a second register, and a third register; When the data in the third register is subtracted from the data in the third register by the arithmetic unit, it is determined whether the data in the register is greater than or equal to the data in the third register by the carry (carry down) signals output from the arithmetic unit. a selection circuit that selects the output data of the arithmetic unit when the arithmetic unit is selected, and selects the output data of the first logic register when it is not selected; means for inputting the most significant two bits of the second register into the two least significant bits of the register, means for shifting the contents of the second register upward by two bits, and a constant logical value for the two least significant bits of the third register. When inputting °o1°, the value determined by the carry (carry down) signal for the third bit from the lowest register, that is, the output data of the third register when the output data of the third register is subtracted from the output data of the first register, is the output of the third register. Data is the third
Logical value + if greater than or equal to register output data
11@If it is smaller, input the logical value 9P, and for the 4th bit or higher from the lowest register of the 3rd register, input the value shifted by 1 bit upwards from the 3rd lowest bit of the output data of the 3rd register. It is equipped with the means.

[Explanation of Examples]

Next, an arithmetic circuit for calculating a square root according to the present invention will be explained in detail with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention.

In this embodiment, the first Lujistar 1. Second register 2, third register 3, arithmetic circuit 4, and selection circuit 5゜6.7 and 8
Contains.

The operation of this embodiment is as follows.

First, clear the second register l in the figure, and
A value for which the square root is to be found is set, and data is set in the third register 3 as a constant with the lowest two bits being n0111 and all other bits being II□I+.

Next, the selection circuit 6 selects the data of the first register outputted from the first selection circuit 5 and the data of the most significant two bits of the second register 2, and sets the second register 1K. At the same time, the selection circuit 7 selects the output data of the second register 2 in the upper direction.
The pit-shifted data is selected and set in the second register 2.

From then on, as will be described later, the selection data of the selection circuit 5 and the data of the 3rd bit from the bottom of the third register 3 are determined by the magnitude relationship between the output data of the register 1 and the output data of the third register 3. It is automatically determined, and the square root calculation proceeds as described below.

First, the output data of the third register 3 is subtracted from the output data of the register 1 by the arithmetic unit 4.

At this time, the carry (down) signal 9 output from the arithmetic unit 4 determines whether the output data of the register 1 is greater than or equal to the output data of the third register 3, and if the data is greater or equal, the selection circuit 5 selects and outputs the output data of the arithmetic unit 4, sends the most significant two bits of the second register 2 to the lowest two bits via the selection circuit 6, and outputs the output of the selection circuit 5 to the lowest three bits and above. Input the data into Lujistar 1. On the other hand, in the third register 3, the lowest two bits are the constant "01'1" via the selection circuit 8, and the third bit from the lowest is the value determined from the carry (down) signal 9. The logic Jl+ is inputted, and data shifted by one bit in the upper direction from the third bit from the lowest order of the output data of the third register 3 is inputted to the fourth bit and above from the lowest order.

Then, the output data of the second register 2 is input to the second register 2 by shifting two bits upwards through the selection circuit 7, but the two least significant bits may be undefined.

If the output data of the register 1 is smaller than the output data of the third register 3, the logical value of the carry (down) signal 9 output from the arithmetic unit 4 is
This is reversed when the output data of the third register 3 is greater than or equal to the output data of the third register 3. Therefore, the first Rujista 1
It is determined by the carry (downgrade) signal 9 that the output data of is smaller than the output data of the third register 3, and the selection circuit 5
selects and outputs the register 1, and sends the two most significant bits of the second register 2 to the two least significant bits through the selection circuit 6.
Then, the output data of the selection circuit 5 is inputted to the register 1 in the least significant three bits and above. On the other hand, the lowest two bits are stored in the third register 3 via the selection circuit 8 as a constant II (1
1If, and the third bit from the bottom is the logic It□It, which is the value determined from the above carry (down) signal 9.
Then, data obtained by shifting the output data of the third register 3 by one bit in the upper direction from the third bit from the lowest order is inputted to the fourth bit and above from the lowest order. Then, the output data of the second register 2 is input to the second register 2 by shifting two bits upwards through the selection circuit 7, but the two least significant bits may be undefined. With the operation described above, a 2-bit square root operation is executed in each step, that is, each time a clock signal to the register is output.

The above calculation is an Ishikawa version of Newton's iteration formula, and by repeating this,
The result of the square root of the value initially set in the second register is obtained at the third or higher bit from the bottom of the third register.

〔Effect of the invention〕

As explained above, the present invention has the effect of speeding up the calculation because it can always perform the square root calculation on 2 bits at a time in 1 step, whereas the conventional method required 3 to 6 steps. .

[Brief explanation of the drawing]

The figure shows a block diagram of one embodiment of the invention. In the figure, 1... second register, 2...
...Second register, 3...Third register, 4.
... Arithmetic circuit, 5.6, 7.8 ... Selection circuit.

Claims (1)

[Scope of Claims] At least three registers, a first register, a second register, and a third register; an arithmetic unit receiving output data from at least the first register and the third register among the registers; When the third register notator is subtracted from the data in the register with the operator's finger, the carry (lower digit) output from the arithmetic unit indicates that the data in the register is greater than or equal to the data in the third register. (G) A selection circuit that selects the output data of the corner fl ie K H mouthpart when it is determined by the signal, and selects the output data of the first Lujistor when it is not determined; means for inputting the third bit or more from the lowest register and inputting the highest two bits of the second register into the lowest two bits of the second register; means for shifting the contents of the second register q by two bits in the upper direction; The lowest 2 bits of the 3rd register are set to the constant logical value ``01''.
” For the 3rd bit from the least significant input, the value determined by the carry (down) signal is the output of the 2nd register when the output data of the 3rd register is subtracted from the output data of the 1st register. If the data is greater than or equal to the output data of the third register, input the logical value 11111; if it is smaller, input the logical value 110 If. An arithmetic processing device comprising: means for inputting a value shifted by one focus in an upward direction from the third bit of