JPS5856032A - Pipeline arithmetic device - Google Patents

Abstract

PURPOSE:To prevent the prolongation of operation time due to an overflow, by providing a selector which supplies either a maximum or a minimum, expressed by the number output bits of an adder, to a latch register as the sum in case of the overflow. CONSTITUTION:An adder 11 calculates the sum of data inputted to terminals A dnd B, and supplies the most significant digit bit to a digit overflow detecting circuit 13 through a line 16 while supplying the sum to a selector 14 through a line 15. This circuit 13 is further supplied with the most significant digit bit of input data through a line 17 and also supplied with the most significant digit bit of a latch register 12 which holds the sum output through a line 18. The output of the circuit 13 is supplied as a selection signal to the selector 14, which is further supplied with the normal addition result output of the adder 11 through a line 15. Constant data, i.e. a maximum value X'7FFF' and minimum value X'8000', expressed by the output bit width of the adder 11 are supplied through lines 19 and 20 respectively.

Description

[Detailed description of the invention] The present invention relates to a pipeline arithmetic device.

The concept of "pipeline" processing at the logic circuit level has existed for a long time, and is often seen when speeding up arithmetic processing.In particular, it is used to speed up and economically process multiplications that involve multiple additions. suitable for

By the way, in the pipeline arithmetic device as described above, when fixed-point format data is sequentially added, a problem of overflow occurs. To deal with this, the following methods have conventionally existed.

(1) Perform calculations in floating point mode.

(2) If an overflow occurs during an operation, store it as a status, check the status when the operation is completed, and if there is an overflow, shift down all operand data by 1 bit (arithmetic write shift). ) and perform the calculation again.

This operation is performed until there are no overflows, and the final result is shifted up (arithmetic left shift).

The above example (2) will be briefly explained using the conventional configuration example of the pipeline arithmetic device shown in FIG. In the figure, 1 is an adder, 2 is a latch register, and 3 is an overflow detection circuit. In the above configuration, first, the contents of latch register 2 are cleared prior to calculation.

Input data (e.g. multiplier output) is latch clock LC
The signals are sequentially supplied to adder l in synchronization with , and are added. As an example here, we will deal with a data format as shown in Figure 2. The data is expressed in 16 bits, and the MSB S is a sign, L7 indicates the Δ-enlarged number point position, and negative numbers are expressed as two's complement (2's complement). By inputting the most significant bits of the number and the sum, this combination trap outputs overflow information.

The above arithmetic unit will be described below as being controlled by a microprogram.

At the end of the calculation, overflow information is checked according to the microprogram. If there is an overflow, the calculation is instructed to be corrected and the following method is used. That is, after all input data has been processed by one bit to the right, one-digit overflow is checked, and if there is overflow, the input data is shifted down again. In this way, the operation was repeated until there was no overflow, the output of the latch register 2 was taken out, and the result was obtained by performing an arithmetic shift (upshift) to the left by the number of downshifts.

However, this method has drawbacks such as certain pits being discarded, resulting in lower accuracy and longer computation time when overflowing by one digit. Furthermore, method (1) also has the disadvantage of complicating the hardware.

The present invention has been made based on the above-mentioned circumstances, and it obtains an overflow signal as a selection signal between an adder and a latch register, and selects either the maximum value or the minimum value that can be expressed by the number of output bits of the adder. is supplied to the latch register as the sum in case of overflow.

An object of the present invention is to provide a pipe 2-in arithmetic device which prevents a delay in calculation time due to a one-digit shift when performing pipeline calculations on fixed-point format data by inserting a selector.

Hereinafter, the present invention will be explained in detail using FIG. 3 and subsequent figures.

FIG. 3 is a block diagram showing an embodiment of the present invention. In FIG. 1, 11 is an adder and 12 is a latch register.

Adder 11 adds the data input to terminals A and B, and supplies the resulting value to selector 14 via line 15, and the most significant pit to overflow detection circuit J3 via line 16f. The overflow detection circuit 13 is also supplied with the most significant bit of the input data via the 2-in 17f, and further via the line 18 with the most significant bit of the latch register 12 in which the sum output is held. The output of the camellia overflow detection circuit 13 is supplied as a selection signal to the selector I4. As data input to the selector 14, the combined output of the addition result from the adder 11 is supplied via the line 15, and the data is expressed by the output bit width of the adder 11.
Maximum value of 7 (X' 7 FFF').

Constant data of the minimum value (x'5ooo' ) is supplied via the respective twin J9.20. Furthermore, line 21
．． Each signal propagating through the latch clock LC
, the reset signal RAT.

The table below shows the correspondence between the selection signal of the selector 14 and the output data.

Table 4 is a conceptual diagram showing an example of the operation when the digits are out of order, and shows an example of the operation in the case of combination φ5 in the table.

In FIG. 5, the horizontal axis shows the original value of the adder A+H, and the vertical axis shows the output value of the device of the present invention. The description of the overlapping parts will be omitted, and the description will focus on the selection operation by the selector 14.

According to the present invention, if an overflow occurs during calculation, the value closest to the calculation result at that time is output from the selector 14,
It is supplied as an input to latch register 2 to continue the operation. In the data format shown in FIG. 2, when the decimal point position is set at the right end, the range of numerical values N that can be expressed is 2-1≧N≧-2.

As mentioned above, the correspondence graph shown in Figure 5 shows the correspondence between the true value of the adder (11;) A+B) (horizontal axis) and the manual data of the latch register 12 (vertical axis). Nine things are true. This graph clearly shows
, 2m''-1≧A+B≧-i'', the output of the adder 1 is directly (through) supplied as the input to the latch register 20, and overflow occurs.
21-1, "2-1."-2"" are respectively supplied as inputs to the latch register 12. That is, the combinations shown in the table above5. When φ6, the maximum value x
'7prp (2-1), minimum value x'5ooo<(-
2”) will be output.

FIG. 4 shows a conceptual diagram of the operation when an overflow occurs. Here, the true value is “211” force ζ In this case “2
11-1" is output. In calculations performed by a pipeline, it is often sufficient that the relative magnitude relationship of the results obtained is clear, and from this, the implementation of the present invention is effective. .

As mentioned above, according to the present invention, there is no need to make the hardware complicated in order to deal with overflow during calculation.
Furthermore, the calculation time remains constant without being affected by overflow.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a conventional pipeline arithmetic device, FIG. 2 is an example of a data format used in the present invention, and FIG. 3 is a block diagram of a pipeline arithmetic device according to the present invention. FIG. 4 is a block diagram showing the embodiment; FIG. 4 is a conceptual diagram showing the operation when the digits are out of order; and FIG. 5 is a graph showing the correspondence between the true value of the adder and the input data of the latch register. 11...Adder, 12...Latch register, 13.
... Overflow detection circuit, 74... Selector. Representative Patent Attorney Takehiko Nishikie Figure 1 Figure 3

Claims (1)

[Claims] Input data is sequentially added in synchronization with a latch clock, and is a combination of an adder, a latch register that holds the sum output from this adder, and the most significant bit of the input data. An overflow detection circuit that outputs overflow information is connected between the adder and the latch register, and when an overflow occurs, the overflow detection signal obtained by the overflow detection circuit is used as a selection signal, and the overflow detection circuit outputs overflow information. A pipeline arithmetic device characterized in that either the maximum value or the minimum value that can be expressed by the output of is supplied to the latch register as a sum at that time.