JPS6388639A - Pipeline adding circuit - Google Patents

Abstract

PURPOSE:To reduce a circuit in scale by changing the bit allocation of a pipeline processing in an adder circuit. CONSTITUTION:Latches 35 and 36 to match the timing of an input signal A and a latch 37 to delay one step of a high order (m) bit, namely, one clock of a reference clock pulse in order to execute the pipeline processing are provided. The latch of latches 49-51 is the same as respective latches 35-37. Next, the output of latches 36 and 50 of an (n) bit is added by an (n) bit adder circuit 38, a carry enters an adder circuit 40 of a high-order (m) bit after one clock is delayed by a latch 39, is added and the result of an (m+n+1) bit is obtained. Next, an LSB is thrown away, an (m+n) bit is obtained, and the then method of the allocation of the bit is a high-order (m+1) bit and a low- oder (n-1). Thus, though the LSB is thrown away and the number of bits is dropped, the result of the high order adder circuit in the pipeline processing may not be dropped to a next step low order adder circuit, and the scale of the circuit becomes smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a pipeline adder circuit that allocates bits in an adder during pipeline processing in digital signal processing.

BACKGROUND OF THE INVENTION In recent years, delay time in adders and the like has become a problem in digital digital processing, and pipeline processing has begun to be used.

Hereinafter, the above-mentioned vibra-in processing circuit will be explained with reference to the drawings. 2nd 'J, &i'j: This is a circuit using the adder circuit sound of Western and American examples, and the 3rd [1] is a circuit that uses pie graphing processing. .

Figure 2 Cζ, 27, 28, 30, 32°3
3.34 is a B+n bit latch, 29, 31! ″
;j: m + n bit adder. Also, this second
The circuit shown in the figure (i:, D == ((A+B)/200 +/2 is performed in two lines. However, when handling high frequency data, etc., the addition circuit of 29.31) 1114 becomes a problem. Therefore, the adder circuit has all m bits and n bits.
Bits
Uyo [te. It's t.

3rd Me 1 (/7: put, 1.3.13.10,15
゜1, 19, 20, 22, 24, 26 are m
Bit latch, 2, 7, 9.14g16, 18, 21
.

23, 255J: n-bit latch, 5, 12 are 1
Bit: 1 latch, 4.11 bit adder circuit.

6, t:] is an m-bit m-pi addition circuit. Also,
Latch 1.2d is a latch that aligns the timing of the input input amount A, and latch 3p is a latch that delays by -stage in order to process all the upper m bits of the vibe line.

17, 18 and 19 are also latches similar to latches 1, 2 and 3, and their outputs enter adder circuits 4 and 6. The n-bit adder circuit 4 adds the lower n bits, and the carry is delayed by one stage in the latch 5 and enters the m-bit adder circuit 6. Then, the result, I-t m + n-i-'I bit Kl, is changed to z+n bits by discarding the LSB, that is, (Jinshi B)/2, and goes to the next adder circuit 11.13, and the same Addition is performed, and 4 calculations of [(A+B)/27C)/2 are performed to obtain an m+n-bit result.

Problems to be Solved by the Invention However, the circuit configuration shown in FIG. 3 has a problem in that the number of launch stages increases and the circuit scale becomes extremely large.

In view of the above-mentioned problems, the present invention provides a practical adder circuit that uses a small number of latch stages and can perform vibe line processing.

Means for Solving the Problems In order to solve all of the above problems, the pipeline addition circuit of the present invention has the following features: Second. For the third m+n bit digital signal, m bit latch, n bit latching,
m+1 bit latch, n bit latch, m-1-2
Bit latch, n-2 bit, 1 latch, 1 bit latch, n bit addition circuit, m bit addition circuit, n bit addition circuit, m and 1 bit addition [flat 1 circuit] to use? 0Special, -.

Effect 5? C; - Ming (Well, the above-mentioned purchase 5 sentence (・ζ Therefore, the addition circuit is above A; : and -1; So, conventionally [
・Tekaribeteu・Buchi uses fewer stages and is next to it.

Embodiment 9I of the present invention will be described below with reference to all the drawings l') Figure 1 shows the block 'Uf of the high line processing circuit in Embodiment 1-11 of the present invention. . 1st l-1r, - treasure, 35, 37,
49゜51;'Xm bit ○ latch, 3 et al., 60 i
':! , ``Pinto, Chi, 41.52.54,56
;j: m-1 bit latch, 42.53.55 is n-bit latch, 4A U m -t-2 bit latch%
46°48 is n-2 bit latch, 39.44 is 1
Bit latch, 38Un bit adder circuit, 40Bam
bit addition circuit, 43jdn bit addition circuit, 45
is an m+ bit adder circuit.

The adder circuit for vibe line processing configured as above will be explained. 36.36 is a latch that adjusts the timing of the input signal, and 36 is a latch that delays all the upper m bits by one stage, that is, one reference clock pulse, for vibe line processing.

It is Chi. The latches 49.50 and 51 are also similar to the latches 35.36 and 3. Next, the output of the n-bit latch 36. Then, the LSB is discarded and the result is m+n+1 bits.However, the distribution of the bits at that time is more of a problem, and conventionally, they are divided into upper m bits and lower n bits. However, in the configuration of FIG. 1, the upper In -+-1 bead and the lower n-1 beft are used.

Therefore, even though the LSB money is discarded and the number of focuses is reduced to 6K, the result of the upper adder circuit in pipeline processing does not have to be transferred to the lower adder circuit in the next stage. Therefore, adder circuit 6 and adder circuit 11 in FIG.
will no longer be necessary.

1-7 Therefore, when entering the next stage 7JQ arithmetic circuit 43.45, the third place m → -1% lower n-1 bits, and it is added with the lower n bits of the eight power signal C. circuit 43
0', and the upper m+1 bits are added in the adder circuit 45, and the results of each adder circuit 43.45 are also 1 out of focus, the upper m-1-2 bits, the lower n-2 bits.
The result is D=((A+B)/2+Cl/2).

As described above, according to this embodiment, by changing the allocation of vias in pipeline processing, the launch of the negative stage can be achieved, and the scale of the circuit can be reduced.

As described above (and by virtue of non-invention), the size of the circuit can be reduced by changing the pick-up ratio of pipeline processing using the adder circuit, which has a great practical effect. There is something.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a pipeline adder circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams of conventional adder circuits. 37.51... m-bit latch, 38, 4
0. 43.45...addition circuit, 39.44...
...1-bit latch, 41...m-bit latch, 42...n-bit latch, 46...
... n-2 bit lunch, 56...m −
i-1 bit latch.

Claims (1)

[Claims] A latch that delays the upper m bits of the first, second, and third digital signals of m+n bits by one reference clock pulse, and the upper m bits of the third digital signal. a latch that delays m+1 bits by one clock; and a latch that delays m+1 bits by one clock; and a latch that delays m+1 bits by one clock;
a first adder circuit that adds bits and the lower n bits of the second digital signal; a latch that delays the carry of the first adder circuit by one clock; and a latch that delays the carry of the first adder circuit by one clock; a second adder circuit that adds the upper m bits of the digital signal, a latch that delays the n-1 bits of the result of the first adder circuit by one clock, and the upper m+1 bits of the result of the second adder circuit. a latch that delays bits by one clock; a third adder circuit that adds the lower n-1 bits of the first addition result and the lower n-1 bits of the third digital signal; and the third adder circuit. a latch that delays the carry of the second digital signal by one clock; a fourth adder circuit that adds the upper m+1 bits obtained by delaying the result of the second adder circuit by one clock to the upper m+1 bits of the third digital signal; A pipeline adder circuit comprising: a latch that delays the lower n-2 bits of the result of the third adder circuit by one clock.