JP2001036383A - Fir digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To deal with the case of making the input interval of data exceeding the speed of a computing element as well, when sampling of data is accelerated. SOLUTION: This finite impulse response(FIR) digital filter is constituted to perform filtering processing of data provided by sampling of a fixed cycle. In this case, this filter is provided with a converter 2 for devidedly outputting the input of one system to two systems and simultaneously lowering transfer clock rate, and an FIP filter chip 4 for simultaneously receiving data divided to two systems, applying an output of y(m) when the input of x(m) is applied and performing filtering processing, which is expressed as y(m)=Σa(k)*x(m-k), where a (k) is defined as coefficient and M is defined as the number to taps on the condition of (k) being from 1 to M-1, through plural latches, multipliers and adders.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FIR (finite
The present invention relates to an FIR digital filter that realizes real-time FIR filter processing on data that is sampled at a high speed even when a device for realizing an impulse response (finite impulse response) filter is slow.

[0002]

2. Description of the Related Art A conventional FIR digital filter will be described. For example, in a conventional FIR digital filter disclosed in JP-A-63-248217, MPX11 and MPX2 are used as shown in FIG.
By taking a multistage configuration of 1, MPX31 and MPX64, the time until the output of the FIR filter is obtained is shortened.

[0003]

In the above-mentioned conventional FIR digital filter, there is a restriction that the arithmetic unit in the FIR filter must operate faster than the clock interval of the input signal, and therefore, the arithmetic unit in the FIR filter must operate faster than the speed of the arithmetic unit. There is a problem that data input at a fast time interval cannot be filtered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an FIR digital filter which can cope with a case where data sampling is performed at a high speed and a data input interval exceeds the speed of an arithmetic unit is provided. The purpose is to gain.

[0005]

According to a first aspect of the present invention, there is provided an FIR digital filter for performing a filtering process on data obtained by sampling at a fixed period.
In a digital filter, a converter that divides one system input into a plurality of systems and simultaneously lowers the transfer clock rate, and simultaneously receives data that is divided into a plurality of systems, and when the input is given by x (m), the output is given by y (m), where a (k) is a coefficient and M is the number of taps, k = 0
ＭM−1, y (m) = Σa (k) * x (m−
and a FIR filter chip for performing the filter processing represented by k) with a plurality of latches, multipliers and adders.

According to a second aspect of the present invention, there is provided an FIR digital filter, wherein the converter receives one system input consisting of continuous first data, second data, third data, and fourth data. , A first output system consisting of the first data and the third data, and a second output system consisting of the second data and the fourth data. And the FIR filter chip has a first latch that holds the data of the first output system for a unit time, and a second latch that holds the data of the second output system for a unit time. , A first multiplier for multiplying the third data before the input of the first latch by a first coefficient, and a second coefficient for multiplying the second data after the output of the second latch by a second coefficient A second multiplier for doubling the first multiplier and the first A third multiplier for multiplying the first data after output of the second latch by the second coefficient, and a fourth multiplication for multiplying the second data after output of the second latch by the first coefficient. And a first adder for adding the output values of the first and second multipliers, and a second adder for adding the output values of the third and fourth multipliers. is there.

According to a third aspect of the present invention, in the FIR digital filter, when the delay time of the operation performed by the FIR filter chip is longer than the clock interval at which data is received from the converter, the number of divisions in the converter may be reduced. 4
By increasing the number as described above, the clock interval is reduced.

According to a fourth aspect of the present invention, in the FIR digital filter, the converter divides an input of the aligned data array into a data array that is not aligned in each system and outputs the divided data array. The filter processing is performed based on unaligned data arrays of simultaneous inputs from each system of the device.

According to a fifth aspect of the present invention, in the FIR digital filter, when the delay time of the operation performed by the FIR filter chip is longer than a clock interval for receiving data from the converter, the FIR filter chip may be used. , And a second latch inserted between adders for executing the addition operation of the above expression.

According to a sixth aspect of the present invention, in the FIR digital filter, when the delay time of the operation performed by the FIR filter chip is longer than a clock interval when receiving data from the converter, , A second latch inserted between the multiplier performing the multiplication operation of the above equation and the adder performing the addition operation.

According to a seventh aspect of the present invention, there is provided an FIR digital filter, wherein when the delay time of the operation performed by the FIR filter chip is longer than a clock interval when receiving data from the converter, the addition operation of the above expression is performed. In a tree structure.

According to another aspect of the present invention, there is provided an FIR digital filter, wherein the FIR filter chip adds an output of a multiplier for executing the multiplication operation of the above equation and an externally supplied zero. A plurality of latches, multipliers and adders having the same configuration as the FIR filter chip,
And a second FIR filter chip having a second adder.

According to a ninth aspect of the present invention, in the FIR digital filter, the FIR filter chip and the second FIR filter chip each have a second latch inserted into an external output line. .

According to a tenth aspect of the present invention, the FIR digital filter includes the FIR filter chip and the second
FIR filter chips each have a bypassable third latch inserted into an external input line.

An FIR digital filter according to claim 11 of the present invention changes the position of the latch.

According to a twelfth aspect of the present invention, the FIR digital filter further includes a second converter that merges a plurality of inputs from the last stage into one output and simultaneously increases a transfer clock rate. is there.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An FIR digital filter according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 shows Embodiment 1 of the present invention.
FIG. 2 is a diagram showing a configuration of an FIR digital filter according to FIG.
In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, 1 is an input data line for receiving data, 2 is a converter for outputting two times of input data simultaneously at half the clock cycle, 3a and 3b are outputs of the converter 2, and the next FIR digital A transfer line for transferring a value which is also an input of the filter, 4 is an FIR filter chip, 5a,
5b is a latch for holding the input value of the previous clock, 6b
a, 6b, 6c, 6d are multipliers, 7a, 7b are adders,
8a and 8b are outputs of the FIR digital filter.

The FIR digital filter has an input signal x
When given by (m), y (m) in the following equation (1) is output. Note that k = 0 to M-1 (M: the number of taps).

Y (m) = Σa (k) * x (mk) Expression (1)

As the coefficient a (k), a coefficient received from outside the FIR digital filter is held and used. FIG. 1 shows a case where M (the number of taps) = 2 and this FIR
2 shows a configuration of a digital filter.

Next, the operation of the FIR digital filter according to the first embodiment will be described with reference to the drawings. FIG. 2 is a timing chart showing the operation of the FIR digital filter according to Embodiment 1 of the present invention.

The converter 2 changes the transfer interval of the data received from the input data line 1 shown in FIG. 2A as shown in FIGS. 2B and 2C. As a result, the data input interval speed of the data in the FIR filter chip 4 becomes half that at the time of input.

At this time, in the FIR filter chip 4, the multipliers 6a to 6d and the adders 7a and 7b are always operating.

As shown in FIGS. 2B and 2C, data x (0) and x (1) flow through the transfer lines 3a and 3b. Next, data x (0) and x (1) are input to the latches 5a and 5b.

Next, as shown in FIGS. 2B and 2C, the data x (2) and x (3) flow through the transfer lines 3a and 3b, and the output values of the latches 5a and 5b become the data x ( 0), x
(1).

Next, each of the multipliers 6a to 6d performs multiplication. That is, the multiplier 6a sets the value x (2) of the transfer line 3a to a
(0) times. The multiplier 6b outputs the output value x of the latch 5b.
(1) is multiplied by a (1). The multiplier 6c is provided with a latch 5
The output value x (0) of a is multiplied by a (1). The multiplier 6d multiplies the output value x (1) of the latch 5b by a (0) times.

Next, each of the adders 7a and 7b performs addition. That is, the adder 7a adds the output values of the multipliers 6a and 6b, and the adder 7b adds the output values of the multipliers 6c and 6d.

Then, 8 which is the output of the adders 7a and 7b
a and 8b are output as the outputs of the FIR filter chip 4. At this time, according to the above equation (1), y is added to 8b.
(1), y (2) is output to 8a. From the above,
An FIR digital filter for M = 2 is obtained.

That is, the FIR according to the first embodiment
The digital filter is a FIR digital filter that performs filtering of data obtained by sampling at a fixed period, splits and outputs one system input into a plurality of systems, and simultaneously converts the input into one system into a plurality of systems. Has an FIR filter chip 4 for simultaneously receiving the filtered data and performing a filtering process.
R filter chip 4 has a latch 5 for holding a unit time value.
a, 5b, multipliers 6a to 6d, and adders 7a and 7b.

Embodiment 2 Embodiment 2 An FIR digital filter according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 3 is a diagram showing an F-mode according to Embodiment 2 of the present invention.
FIG. 3 is a diagram illustrating a configuration of an IR digital filter.

In FIG. 3, 5c and 5d are latches, 6
e to 6h are multipliers, 7c to 7f are adders, and the other components are the same as those in FIG.

In the first embodiment, the configuration where M = 2 has been described. As shown in the second embodiment, M = 4
In the case of (1), the FIR filter chip 4 can be created with the same configuration. FIG. 3 shows a configuration in the case of M = 4 based on FIG.

Embodiment 3 An FIR digital filter according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 4 is a diagram showing an F-mode according to Embodiment 3 of the present invention.
FIG. 3 is a diagram illustrating a configuration of an IR digital filter.

In the second embodiment shown in FIG. 3, for example, the end of multiplication by the multiplier 6a, the end of addition by the adder 7a, and the end of adder 7c during two input clocks. Is completed, and the output 8a is obtained through the four stages of terminating the addition of the adder 7e.

Conversely, since the above four operations must be completed within the time of two clocks, a case where the input clock is fast may not be able to be handled by the configuration of FIG.

In FIG. 3 showing the configuration of the second embodiment, the output of the converter 2 is divided into two systems,
The clock frequencies of a and 3b were halved.

Therefore, if the output of the converter 2 is set to four systems as in the third embodiment, the clock frequency on the transfer line can be reduced to one fourth, and the time until the end of the operation can be extended to four clocks. be able to. FIG. 4 shows the input of the multiplier and the like at a certain timing.

That is, the FIR according to the third embodiment
When the delay time of the operation performed by the FIR filter chip 4 is longer than the clock interval at which the filter chip 4 receives data, the digital filter reduces the clock interval by increasing the number of divisions in the converter 2. And

Embodiment 4 FIG. Embodiment 4 An FIR digital filter according to Embodiment 4 of the present invention will be described with reference to the drawings. 5 and 6 show Embodiment 4 of the present invention.
FIG. 2 is a diagram showing a configuration of an FIR digital filter according to FIG.

In the configuration of the third embodiment, the converter 2
As shown in FIG. 4, the output order of x (0),
x (1), x (2), and x (3).

Even if this ordering is not performed, a configuration can be implemented by changing the order in the subsequent FIR filter chip 4.

For example, FIG.
This is a configuration in a case where a method of exchanging in the input part is adopted.

FIG. 6 is a diagram in which the latch positions of the second and third columns in the FIR filter chip 4 and the arguments of the multipliers are interchanged.

That is, the FIR according to the fourth embodiment
The digital filter is characterized in that a data array of simultaneous input is arranged in the FIR filter chip 4.

Embodiment 5 FIG. Embodiment 5 An FIR digital filter according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 7 is a diagram showing an F-mode according to a fifth embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an IR digital filter.

In FIG. 7, 10a to 10d are multipliers,
11a to 11c represent adders, 12a to 12d and 13a and 13b represent latches, and 14a to 14d represent outputs.

Latches 12a to 12d, 13a and 13b
In the configuration where there is no, between four input clocks,
The end of the multiplication of the multiplier 10a, the end of the addition of the adder 11a, the end of the addition of the adder 11b, and the adder 1
After the four stages of 1c addition completion, the output 14a
Is obtained.

In other words, since the above four operations must be completed within the time of four clocks, when the input clock is fast, this configuration may not be able to cope.

FIG. 7 shows the structure of the latches 12a to 12d, 1
By the insertion of 3a and 13b, two stages of “the end of the multiplication of the multiplier 10a and then the end of the addition of the adder 11a” and “the end of the addition of the adder 11b and then the end of the addition of the adder 11c” Each of the two stages of operation is clock 4
It only has to finish within one minute. For this reason, the restriction on time can be relaxed. The latches 13a and 13b in FIG. 7 are for adjusting the delay of the operation result generated by the latches 12a to 12d.

That is, the FIR according to the fifth embodiment
When the delay time of the operation performed by the FIR filter chip 4 is longer than the clock interval when the filter chip 4 receives data, the digital filter shortens the delay time by inserting latches 12a to 12d between the adders. It is characterized by the following.

Embodiment 6 FIG. Embodiment 6 An FIR digital filter according to Embodiment 6 of the present invention will be described with reference to the drawings. FIG. 8 is a diagram showing an F-mode according to the sixth embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an IR digital filter.

In FIG. 8, 10a to 10d are multipliers,
11a to 11c are adders, 14a to 14d are outputs, 15
Reference numerals a to 15d denote latches, respectively.

In the configuration without the latches 15a to 15d, the multiplication of the multiplier 10a is completed, the addition of the adder 11a is completed, and the addition of the adder 1 is completed during four input clocks.
The output 14a is obtained through the four stages of the completion of the addition of 1b and the completion of the addition of the adder 11c.

To put it the other way around, the above four operations must be completed within the time of four clocks, so that if the input clock is fast, this configuration may not be able to cope.

In the configuration shown in FIG. 8, the "end of multiplication in multipliers 10a to 15d" and the "end of addition by adder 11a,
Completion of the addition of b and completion of the addition of the adder 11c "may be completed within four clock periods. When the operation delay in the multiplier is larger than the operation delay in the adder, the division of the multiplication and the addition can relax the restriction on time.

That is, the FIR according to the sixth embodiment
When the delay time of the operation performed by the FIR filter chip 4 is longer than the clock interval at which the filter chip 4 receives data, the digital filter has latches 15a to 15d that hold a unit time value between the adder and the multiplier. Is inserted to reduce the delay time.

Embodiment 7 FIG. Embodiment 7 An FIR digital filter according to Embodiment 7 of the present invention will be described with reference to the drawings. FIG. 9 is a diagram showing an F-mode according to the seventh embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an IR digital filter.

In FIG. 9, 10a to 10d are multipliers,
14a to 14d represent outputs, and 16a to 16c represent adders.

This configuration is different in that the connection of the adder is a binary tree connection. For this reason, the delay generated in the FIR digital filter is such that the serial connection type is “delay of one multiplier and one adder M−1”, while the binary tree connection is “delay of one multiplier and one adder”. Log (M) delays. "

In the example of M = 4 shown in FIG. 9, the series connection has a delay of two adders to a delay of three adders. Be shorter.

That is, the FIR according to the seventh embodiment
When the delay time of the operation performed by the FIR filter chip 4 is longer than the clock interval at which the filter chip 4 receives data, the digital filter shortens the delay time by making the connection between the adders a tree structure. It is characterized by.

Embodiment 8 FIG. An FIR digital filter according to Embodiment 8 of the present invention will be described with reference to the drawings. FIG. 10 shows a configuration of an FIR digital filter according to Embodiment 8 of the present invention.

In FIG. 10, 10a to 10d are multipliers, 14a to 14d are outputs, 15a to 15d are latches,
16a to 16c represent adders, and 17a and 17b represent latches.

In this configuration, the adder has a binary tree connection,
Further, a latch is inserted between the output and the input of each arithmetic unit. In the configuration of FIG. 10, each of the end of multiplication by one multiplier and the end of addition by one adder is the input clock 4.
It only has to finish within one minute.

That is, the FIR according to the eighth embodiment
When the delay time of the operation performed by the FIR filter chip 4 is longer than the clock interval when the filter chip 4 receives data, the digital filter performs doubling of the number of input systems, insertion of a latch, and connection of a tree structure of an adder. The combination is characterized in that a delay time with respect to a clock interval when data is received is reduced.

Embodiment 9 Embodiment 9 An FIR digital filter according to Embodiment 9 of the present invention will be described with reference to the drawings. FIG. 11 is a diagram showing a configuration of an FIR digital filter according to Embodiment 9 of the present invention.

In FIG. 11, 1 is an input data line, 2 is a converter, 3a and 3b are transfer lines, 5a to 5d are latches,
6a to 6h are multipliers, 7a to 7f are adders, 8a and 8
b is the output of the FIR digital filter, 20a and 20b
Is an adder, 21a and 21b are intermediate value input lines of the FIR digital filter, and 22a and 22b are core blocks of the FIR filter chip.

When the circuit shown in the second embodiment (FIG. 3) cannot be constituted by one chip, the circuit scale can be reduced to about half by simply dividing the inside into two.

An FIR digital filter can be constructed by creating and connecting two different circuits as separate chips, respectively. However, as shown in FIG. 11, adders 20a and 20b and an intermediate value input line are provided. By preparing 21a and 21b and giving 0 as the input,
An FIR digital filter can be configured by connecting two identical core blocks 22a and 22b. As a result, the number of types of chips to be created can be reduced to one.

That is, the FIR according to the ninth embodiment
The digital filter is a zero-value input line 21 from outside the chip.
a, 21b, the divided chips 22a,
22b is characterized by having the same circuit configuration.

Embodiment 10 FIG. Embodiment 1 of the present invention
The FIR digital filter according to 0 will be described with reference to the drawings. FIG. 12 shows Embodiment 10 of the present invention.
FIG. 2 is a diagram showing a configuration of an FIR digital filter according to FIG.

In FIG. 12, 1 is an input data line, 2 is a converter, 3a and 3b are transfer lines, 5a to 5d are latches,
6a to 6h are multipliers, 7a to 7f are adders, 8a and 8
b is the output of the FIR digital filter, 20a and 20b
Is an adder, 21a and 21b are intermediate value input lines of FIR digital filters, 22a and 22b are core blocks of FIR filter chips, 23a to 23d and 24a to 2
4d is a latch.

In the configuration of FIG. 12, since the latch is inserted on the output side of the core blocks 22a and 22b, the FI
The timing at which the output value of the R digital filter switches can be adjusted when the clock is input.

That is, the FI according to the tenth embodiment
The R digital filter has a large circuit size of the FIR filter chip. When the circuit is divided and mounted as separate chips 22a and 22b, latches 23a to 23
d, 24a to 24d are inserted.

Embodiment 11 FIG. FIG. 12 showing the tenth embodiment has a configuration in the case of M = 4. However, the configuration in which the output of the core block 22a is connected to the core block 22b is repeated, and only by increasing the number of core blocks, M = 6, 8 , 1
0,... Can be configured.

That is, the FI according to the eleventh embodiment
The R digital filter is characterized in that a change in the number of taps is handled only by a connection outside the chip.

Embodiment 12 FIG. Embodiment 1 of the present invention
2 will be described with reference to the drawings. FIG. 13 shows a twelfth embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of an FIR digital filter according to FIG.

In FIG. 13, reference numerals 25a to 25d denote latches which can be bypass-controlled.

By incorporating bypassable latches 25a to 25d in core blocks 22a to 22d, an M = 4 FIR digital filter that receives data from transfer lines 3a and 3b once every two input clocks as in FIG. In this case, an M = 4 FIR digital filter that receives data from the transfer lines 3a to 3d once every four input clocks in FIG. 13 can be realized only by the same combination of the core blocks.

That is, the FI according to the twelfth embodiment
The R digital filter is characterized in that by providing bypass control of the latches 25a to 25d, a change in the number of simultaneous inputs can be handled only by connection outside the chip.

Embodiment 13 FIG. Embodiment 10
12, a device for constructing an FIR digital filter is required, although conversion by a converter is necessary due to connection of a binary tree of adders, insertion of latches between arithmetic units, doubling of the number of simultaneous inputs, and the like. It is possible to process fast input data without improving the speed of the input data.

That is, the FI according to the thirteenth embodiment
In the tenth to twelfth embodiments, when the delay time of the operation performed by the FIR filter chip is longer than the clock interval when the filter chip receives data, the R digital filter doubles the number of input systems and inserts a latch. ,
By combining the tree structure connection of the adders, the delay time with respect to the clock interval when receiving data is reduced.

Embodiment 14 FIG. Embodiment 1 of the present invention
The FIR digital filter according to No. 4 will be described with reference to the drawings. FIG. 14 shows Embodiment 14 of the present invention.
FIG. 2 is a diagram showing a configuration of an FIR digital filter according to FIG.

In the configuration of FIG. 4 showing the third embodiment, after data up to x (7) is input to the FIR filter chip 4, the operation is performed, and y (3) to y (3)
(6) is output.

In the fourteenth embodiment, by changing the internal latch configuration as shown in FIG. 14, the data up to x (3) is input to the FIR filter chip 4, the operation is performed, and y ( 3) can be changed to the output mechanism. In this case, the delay until y (4) to y (6) is obtained remains unchanged, but y (3), y (7),.
As for, the result can be obtained at a faster time.

That is, the FI according to the fourteenth embodiment
In each of the above embodiments, the R digital filter is characterized in that by changing the latch position, the delay time until a partial filter output is obtained is reduced.

Embodiment 15 FIG. Embodiments 1 to 1 above
In configurations up to 4, the output of the FIR digital filter is
Although a plurality of systems have been used, a converter for increasing the clock rate is provided on the output side of the FIR digital filter by merging the inputs of the plurality of systems into an output of one system, and a low-speed clock is used during the FIR digital filter processing. The input / output with the outside may be configured to exchange data with a high-speed clock.

[0089]

As described above, in the FIR digital filter according to the first aspect of the present invention, in a FIR digital filter for performing a filtering process on data obtained by sampling at a fixed period, one system input is divided into a plurality of systems. A converter that divides the output and simultaneously lowers the transfer clock rate, and simultaneously receives the data divided into a plurality of systems, and when the input is given by x (m), the output is y (m)
Where a (k) is a coefficient and M is the number of taps,
An expression in which k = 0 to M-1, y (m) = Σa (k) * x
Since there is provided an FIR filter chip for performing a filtering process represented by (mk) using a plurality of latches, multipliers, and adders, when data sampling is performed at a high speed, the data input interval is equal to the speed of the arithmetic unit. The effect that it can respond also in the case of exceeding.

In the FIR digital filter according to claim 2 of the present invention, as described above, the converter is composed of continuous first data, second data, third data, and fourth data. A first output system comprising the first data and the third data,
A second data comprising the second data and the fourth data
And the transfer clock rate is set to 入 力 of the input at the same time, and the FIR filter chip includes a first latch that holds the data of the first output system for a unit time, A second latch for holding the data of the output system for a unit time, a first multiplier for multiplying the third data before input of the first latch by a first coefficient, A second multiplier for multiplying the second data after output by a second coefficient, and a third multiplier for multiplying the first data after output of the first latch by the second coefficient; ,
A fourth multiplier for multiplying the second data after output of the second latch by the first coefficient, and a first adder for adding output values of the first and second multipliers. , And a second adder for adding the output values of the third and fourth multipliers, so that when the data sampling speed is increased, the case where the data input interval exceeds the speed of the arithmetic unit is also supported. It has the effect of being able to.

As described above, in the FIR digital filter according to the third aspect of the present invention, when the delay time of the operation performed by the FIR filter chip is longer than the clock interval when receiving data from the converter, Since the clock interval is reduced by increasing the number of divisions in the converter to four or more, when the data sampling speed is increased, it is possible to cope with the case where the data input interval exceeds the operation unit speed.

As described above, in the FIR digital filter according to the fourth aspect of the present invention, the converter divides the input of the aligned data array into a data array that is not aligned in each system and outputs the divided data array. Since the chip performs the filtering process based on the unaligned data array of the simultaneous input from each system of the converter, if the data sampling is made faster, the data input interval exceeds the speed of the arithmetic unit. This also has the effect of being able to deal with

As described above, in the FIR digital filter according to the fifth aspect of the present invention, when the delay time of the operation performed by the FIR filter chip is longer than the clock interval when receiving data from the converter, The F
Since the IR filter chip has the second latch inserted between the adders that execute the addition operation of the above expression, an effect is provided that the allowable delay time of the operation can be increased.

As described above, the FIR digital filter according to the sixth aspect of the present invention is configured such that when the delay time of the operation performed by the FIR filter chip is longer than the clock interval when receiving data from the converter, The F
Since the IR filter chip has the second latch inserted between the multiplier performing the multiplication operation of the above expression and the adder performing the addition operation, the effect that the allowable delay time of the operation can be increased. To play.

As described above, the FIR digital filter according to claim 7 of the present invention has a structure in which the delay time of the operation performed by the FIR filter chip is longer than the clock interval at the time of receiving data from the converter. Since the connection between the adders that execute the addition operation of the above equation has a tree structure, the delay time can be reduced.

As described above, in the FIR digital filter according to claim 8 of the present invention, the FIR filter chip adds the output of the multiplier for executing the multiplication operation of the above equation and zero given from the outside. A chip to be created because it further includes a plurality of latches, multipliers and adders having the same configuration as that of the FIR filter chip, and a second FIR filter chip having the second adder; The effect is that the number of types can be reduced to one.

As described above, in the FIR digital filter according to the ninth aspect of the present invention, the second latch in which the FIR filter chip and the second FIR filter chip are respectively inserted into an external output line is provided. Therefore, there is an effect that the timing at which the output value of the filter is switched can be synchronized with the input of the clock.

As described above, in the FIR digital filter according to claim 10 of the present invention, the FIR filter chip and the second FIR filter chip are each capable of being bypassed by being inserted into an external input line. Since there are 3 latches, the change in the number of simultaneous inputs
This has the effect of being able to respond only to connections outside the chip.

In the FIR digital filter according to the eleventh aspect of the present invention, as described above, since the position of the latch is changed, the delay time until a partial filter output is obtained can be reduced. To play.

As described above, the FIR digital filter according to the twelfth aspect of the present invention includes a second converter that merges a plurality of inputs from the last stage into one output and simultaneously increases a transfer clock rate. As we prepared more,
There is an effect that data can be exchanged between the external input and output with a high-speed clock.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an FIR digital filter according to Embodiment 1 of the present invention.

FIG. 2 is a timing chart showing an operation of the FIR digital filter according to Embodiment 1 of the present invention.

FIG. 3 is a diagram showing a configuration of an FIR digital filter according to Embodiment 2 of the present invention.

FIG. 4 is a diagram showing a configuration of an FIR digital filter according to Embodiment 3 of the present invention.

FIG. 5 is a diagram showing a configuration of an FIR digital filter according to Embodiment 4 of the present invention.

FIG. 6 is a diagram showing a configuration of an FIR digital filter according to Embodiment 4 of the present invention.

FIG. 7 is a diagram showing a configuration of an FIR digital filter according to Embodiment 5 of the present invention.

FIG. 8 is a diagram showing a configuration of an FIR digital filter according to Embodiment 6 of the present invention.

FIG. 9 is a diagram showing a configuration of an FIR digital filter according to Embodiment 7 of the present invention.

FIG. 10 is a diagram showing a configuration of an FIR digital filter according to Embodiment 8 of the present invention.

FIG. 11 is a diagram showing a configuration of an FIR digital filter according to Embodiment 9 of the present invention.

FIG. 12 is a diagram showing a configuration of an FIR digital filter according to Embodiment 10 of the present invention.

FIG. 13 is a diagram showing a configuration of an FIR digital filter according to Embodiment 12 of the present invention.

FIG. 14 is a diagram showing a configuration of an FIR digital filter according to Embodiment 14 of the present invention.

[Explanation of symbols]

1 input data line, 2 converter, 3a, 3b transfer line,
4 FIR filter chips, 5a, 5b, 5c, 5d
Latches, 6a, 6b, 6c, 6d, 6e, 6f, 6g,
6h multiplier, 7a, 7b, 7c, 7d, 7e, 7f
Adders, 8a, 8b outputs, 10a, 10b, 10c,
10d multiplier, 11a, 11b, 11c adder, 1
2a, 12b, 12c, 12d Latch, 13a, 13
b latch, 14a, 14b, 14c, 14d output,
15a, 15b, 15c, 15d latch, 16a, 16
b, 16c adder, 17a, 17b latch, 20
a, 20b adder, 21a, 21b intermediate value input line,
22a, 22b core block, 23a, 23b, 23
c, 23d Latch, 24a, 24b, 24c, 24d
Latch, 25a, 25b, 25c, 25d Latch.

Claims (12)

[Claims] 1. An FIR digital filter for filtering data obtained by sampling at a fixed period, comprising: a converter that divides and outputs one input to a plurality of systems and simultaneously lowers a transfer clock rate; When the input is given by x (m) and the output is given by y (m), a (k) is a coefficient and M is the number of taps, k = 0 to 0
An FIR filter chip that performs a filtering process represented by an expression of M−1, y (m) = Σa (k) * x (mk) by a plurality of latches, multipliers, and adders. A featured FIR digital filter. 2. The method according to claim 1, wherein the converter comprises:
One system input including second data, third data, and fourth data is input to the first output system including the first data and the third data, and the second data,
And outputs the divided data to a second output system composed of the fourth data, and simultaneously sets the transfer clock rate to 入 力 of the input, and the FIR filter chip holds the data of the first output system for a unit time. A first latch and the second latch;
A second latch for holding the data of the output system for a unit time, and a third data before the input of the first latch to the first latch.
A first multiplier for multiplying the second data after the output of the second latch by a second coefficient, and a second multiplier for multiplying the second data after the output of the second latch by a second coefficient. A third multiplier for multiplying the first data by the second coefficient, a fourth multiplier for multiplying the second data after the output of the second latch by the first coefficient, 2. The apparatus according to claim 1, further comprising a first adder for adding output values of the first and second multipliers, and a second adder for adding output values of the third and fourth multipliers. 2. The FIR digital filter according to 1. 3. When the delay time of the operation performed by the FIR filter chip is longer than the clock interval for receiving data from the converter, the clock interval is increased by increasing the number of divisions in the converter to four or more. The FIR digital filter according to claim 1, wherein the FIR digital filter is lowered. 4. The converter outputs the input of the aligned data array by dividing it into data arrays that are not aligned in each system, and the FIR filter chip aligns the simultaneous input from each system of the converter. 2. The FIR digital filter according to claim 1, wherein a filter process is performed based on a data array that is not present. 5. When the delay time of the operation performed by the FIR filter chip is longer than a clock interval for receiving data from the converter, the FIR filter chip performs an addition operation of the equation. 2. The FIR digital filter according to claim 1, further comprising a second latch interposed therebetween. 6. A multiplier for performing a multiplication operation of the above expression, wherein a delay time of an operation performed by the FIR filter chip is longer than a clock interval when receiving data from the converter. 2. The FIR digital filter according to claim 1, further comprising a second latch inserted between the adder and the adder performing the addition operation. 7. When the delay time of the operation performed by the FIR filter chip is longer than a clock interval when receiving data from the converter, a connection between the adders executing the addition operation of the above equation is formed in a tree structure. 2. The FIR digital filter according to claim 1, wherein: 8. The FIR filter chip has a second adder for adding an output of a multiplier for performing a multiplication operation of the above expression and zero given from the outside, and has the same configuration as the FIR filter chip. Multiple latches,
The FIR digital filter according to claim 1, further comprising a second FIR filter chip having a multiplier, an adder, and a second adder. 9. The FIR filter chip and the second FIR filter chip
9. The FIR digital filter according to claim 8, wherein each of the FIR filter chips has a second latch inserted into an external output line. 10. The FIR filter according to claim 9, wherein each of said FIR filter chip and said second FIR filter chip has a bypassable third latch inserted into an external input line. Digital filter. 11. The FIR digital filter according to claim 1, wherein a position of the latch is changed. 12. The system according to claim 1, further comprising a second converter for merging a plurality of inputs from the last stage into an output of one system and simultaneously increasing a transfer clock rate.
An FIR digital filter according to any one of claims 1 to 11.